Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, particularly provides a semiconductor structure and a preparation method thereof, and aims to solve the technical problem that a longitudinal electric field at the tail end of a field plate greatly affects the upper limit value of breakdown voltage of a device in the prior art. To this end, the semiconductor structure of the present application comprises: a semiconductor substrate; a well region in the semiconductor substrate; the body region and the drift region are located in the well region; the source region and the contact region are located in the body region; the drain region is positioned in the drift region; the gate dielectric layer and the field oxide layer are located on the surface of the semiconductor substrate; a penetrating groove penetrating through the field oxide layer is formed in the field oxide layer, and a high-dielectric-constant dielectric material layer is arranged in the penetrating groove; and a gate on the gate dielectric layer extends to cover the dielectric material layer to serve as a field plate. According to the semiconductor structure provided by the invention, the electric field distribution on the surface of the semiconductor substrate is smoother, so that the surface breakdown voltage is closer to the internal breakdown voltage, and the breakdown voltage is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically providing a semiconductor structure and its fabrication method. Background Technology

[0002] LDMOS (Laterally Diffused MetalOxide Semiconductor) is a typical lateral power semiconductor device. Due to its high voltage tolerance, high current capability, strong drive capability, and good frequency characteristics, it is frequently used in power integrated circuits. Furthermore, as one of the two types of DMOS devices, LDMOS devices are widely used in BCD (Bipolar-CMOS-DMOS) processes due to their ease of compatibility with CMOS processes and low production costs.

[0003] To improve the application of LDMOS devices, increasing their breakdown voltage is an important research topic. In traditional technologies, adjusting the surface electric field of the device is one of the most effective ways to improve the breakdown voltage. The surface electric field of LDMOS devices is mainly achieved through methods such as... Figure 1 The field plate shown is adjusted to obtain a more uniform electric field distribution, thereby improving the breakdown voltage of the device. The field plate is a junction termination technology. The field plate generates an electric field perpendicular to the substrate surface, which works together with the electric field generated at the drain to reduce the electric field line density in the curved junction portion, thereby reducing the peak electric field in the curved portion of the PN junction and improving the breakdown voltage of the LDMOS device.

[0004] However, due to the small radius of curvature and high charge density at the edge of the field plate, the electric field lines concentrate at the edge, forming a sharp-corner electric field. This limits the increase in the device's breakdown voltage, preventing it from reaching the theoretical maximum value. Accordingly, the field requires a new semiconductor structure and its fabrication method to address these issues. Summary of the Invention

[0005] To overcome the above-mentioned defects, this application provides a semiconductor structure to solve or at least partially solve the technical problem that the longitudinal electric field at the end of the field plate in the prior art greatly affects the upper limit of the breakdown voltage of the device; this application also provides a method for fabricating the semiconductor structure.

[0006] To achieve the above object, the first aspect of the present application provides a semiconductor structure, comprising: a semiconductor substrate; a well region in the semiconductor substrate; a body region and a drift region in the well region; a source region and a contact region in the body region; a drain region in the drift region; a gate dielectric layer and a field oxide layer which are adjacent on the surface of the semiconductor substrate, the field oxide layer being between the gate dielectric layer and the drain region; a through slot in the field oxide layer, the through slot penetrating the field oxide layer and the through slot being filled with a dielectric material layer, wherein the dielectric constant of the dielectric material layer is greater than the dielectric constant of the field oxide layer; and a gate electrode on the gate dielectric layer, the gate electrode extending to cover the dielectric material layer as a field plate.

[0007] Further, the aforementioned semiconductor structure further comprises a doped region in the drift region, the doped region being adjacent to the dielectric material layer, wherein the doping type of the doped region is the same as the doping type of the drift region, and the doping concentration of the doped region is greater than the doping concentration of the drift region.

[0008] Further, the orthographic projection of the doped region on the semiconductor substrate corresponds to the orthographic projection of the dielectric material layer on the semiconductor substrate.

[0009] Further, the ratio a of the depth of the doped region to the depth of the drift region satisfies:

[0010] Further, the ratio b of the lateral width of the dielectric material layer to the lateral width of the field oxide layer satisfies:

[0011] Further, the ratio c of the lateral width of the area covered by the field plate on the dielectric material layer to the lateral width of the dielectric material layer satisfies:

[0012] The second aspect of the present application provides a method for manufacturing a semiconductor structure, comprising the following steps: forming a body region and a drift region in a well region of a semiconductor substrate; forming a source region and a drain region in the body region and the drift region respectively, and forming a contact region in the body region; forming a gate dielectric layer and a field oxide layer which are adjacent on the surface of the semiconductor substrate, wherein the orthographic projection of the field oxide layer on the surface of the semiconductor substrate is within the orthographic projection of the drift region on the semiconductor substrate, and the field oxide layer is between the gate dielectric layer and the drain region; forming a through slot which penetrates the field oxide layer; filling a dielectric material layer in the through slot, wherein the dielectric constant of the dielectric material layer is greater than the dielectric constant of the field oxide layer; and forming a gate electrode and a field plate, the gate electrode being on the gate dielectric layer and extending to cover the dielectric material layer as the aforementioned field plate.

[0013] Further, before forming the through slot penetrating the field oxide layer, further comprising: forming a doped region in the drift region, the doped region extending from the surface of the semiconductor substrate into the drift region, wherein the doped region and the drift region have the same doping type, and the doping concentration of the doped region is greater than the doping concentration of the drift region. Or, before filling the dielectric material in the through slot, further comprising: forming a doped region in the drift region, the doped region extending from the surface of the semiconductor substrate into the drift region, wherein the doped region and the drift region have the same doping type, and the doping concentration of the doped region is greater than the doping concentration of the drift region.

[0014] Further, the orthographic projection of the doped region on the semiconductor substrate corresponds to the orthographic projection of the dielectric material layer on the semiconductor substrate.

[0015] Further, the ratio a of the depth of the doped region to the depth of the drift region satisfies:

[0016] Further, the ratio b of the lateral width of the dielectric layer material layer to the lateral width of the field oxide layer satisfies:

[0017] Further, the ratio c of the lateral width of the region covered by the dielectric material layer by the field plate to the lateral width of the dielectric material layer satisfies:

[0018] The above one or more technical solutions of the present application have at least one or more of the following beneficial effects:

[0019] In the implementation of the technical solutions of the present application, by setting a through slot penetrating the field oxide layer in the field oxide layer and filling the through slot with a dielectric material having a dielectric constant higher than that of the field oxide layer, the depletion layer charge of the drift region can be effectively coupled to the field plate, making the surface electric field distribution more gentle, thereby making the surface breakdown voltage of the semiconductor structure closer to its bulk breakdown voltage, and ultimately achieving the effect of improving the breakdown voltage.

[0020] In particular, by reasonably controlling the lateral width of the dielectric material layer, especially the ratio of the lateral width of the dielectric material layer to the lateral width of the field oxide layer, the modulation effect of the field plate on the surface electric field of the drift region can be ensured, and the breakdown voltage can be maximized. By reasonably controlling the lateral width of the region covered by the dielectric material layer by the field plate, especially the ratio of the covered region to the lateral width of the dielectric material layer, the modulation effect of the field plate can be fully utilized, and the improvement of the breakdown voltage can be improved.

[0021] On this basis, by providing a doped region in the drift region, the doped region having the same doping type as the drift region and a doping concentration greater than that of the drift region, on one hand, the potential difference between the drift region below the field plate and the field plate can be reduced, and the peak electric field can be further weakened, so as to further improve the breakdown voltage; on the other hand, as the doping concentration of the surface of the drift region is increased, the on-resistance is also reduced, so as to reduce the on-resistance while improving the breakdown voltage.

[0022] Further, by arranging the doped region below the dielectric material layer, the doped region can cooperate with the dielectric material layer to further reduce the longitudinal electric field at the end of the field plate, and in the processing process, the same mask can meet the windowing requirements of forming the through groove and the doped region, so as to simplify the process flow.

[0023] By reasonably controlling the ratio between the depth of the doped region and the depth of the drift region, the breakdown voltage can be maximized while the on-resistance is sufficiently reduced. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structure schematic diagram of an LDMOS device in the prior art;

[0025] Figure 2 is a schematic diagram of a semiconductor structure provided by Embodiment One of the present application;

[0026] Figure 3 is a top view schematic diagram of a semiconductor structure provided by Embodiment One of the present application;

[0027] Figure 4 is a simulation curve diagram of the ratio between the lateral width of the dielectric material layer and the field oxide layer and the breakdown voltage in the semiconductor structure provided by Embodiment One of the present application;

[0028] Figure 5 is a simulation curve diagram of the ratio between the dielectric material layer covered area and the lateral width of itself and the breakdown voltage in the semiconductor structure provided by Embodiment One of the present application;

[0029] Figure 6 is a structure schematic diagram of a semiconductor structure provided by Embodiment Two of the present application;

[0030] Figure 7 is a simulation curve of the ratio between the depth of the doped region and the depth of the drift region and the breakdown voltage in the semiconductor structure provided by Embodiment Two of the present application;

[0031] Figure 8 is a schematic diagram of a semiconductor structure in Comparative Example One provided by the present application;

[0032] Figure 9 is a schematic diagram of a semiconductor structure in Comparative Example Two provided by the present application;

[0033] Figure 10 Simulation curves of the breakdown characteristics of semiconductor structures with different structures are shown;

[0034] Figure 11 Simulated Idlin current curves for different semiconductor structures are shown.

[0035] Figure 12 The simulation results of the on-resistance of semiconductor structures with different structures are shown;

[0036] Figures 13a to 13k This is a schematic diagram of the main steps in the semiconductor structure fabrication method provided in this application.

[0037] List of reference numerals in the attached diagram:

[0038] 1-Semiconductor substrate; 2-Well region; 3-Field oxide layer; 3a-Field oxide layer; 3b-Field oxide layer; 4-Bulk region; 5-Drift region; 6-Dielectric material layer; 6a-Dielectric material layer; 6b-Dielectric material layer; 7-Gate oxide layer; 81-Polysilicon gate; 82-Field plate; 9-Source region; 10-Contact region; 11-Drain region; 12-Doped region. Detailed Implementation

[0039] Some preferred embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical solutions and principles of this application and are not intended to limit the scope of protection of this application.

[0040] In the description of semiconductor structures, particularly their vertical structures, in the embodiments of this application, the accompanying drawings all show two axisymmetric cells (the axis of symmetry is shown in the figures). Figure 2 (The figure shown is in dashed form.) It should be understood that this figure is only for better reflecting the actual product and is not intended to be limiting. Alternatively, it could show only the structure of a single cell on one side of the axis of symmetry, which would also be sufficient to explain the technical concept of this application. Furthermore, in actual products, the number of cells is not limited to two. In this art, doping types include P-type and N-type. In the description of this application, the first doping type and the second doping type are opposite types. If the first doping type is N-type, then the second doping type is P-type, and vice versa.

[0041] Figure 2 This is a schematic diagram of the semiconductor structure provided in Embodiment 1 of this application. Please refer to the appendix. Figure 2The semiconductor structure provided by the embodiment one comprises a semiconductor substrate 1; a well region 2 is arranged in the semiconductor substrate 1; a body region 4 and a drift region 5 are arranged in the well region 2; a source region 9 and a contact region 10 are arranged in the body region 4, and a drain region 11 is arranged in the drift region 5; a gate dielectric layer 7 and a field oxide layer 3 are arranged on the surface of the semiconductor substrate 1 in abutment, and the field oxide layer 3 is located between the gate dielectric layer 7 and the drain region 11; a through slot is formed in the field oxide layer 3, and a dielectric material layer 6 is arranged in the through slot, wherein the dielectric constant of the dielectric material layer 6 is greater than the dielectric constant of the field oxide layer 3; a gate electrode 81 is arranged on the gate dielectric layer 7 in a stacked manner, and the gate electrode 81 extends to cover the dielectric material layer 6 on the side facing the drain region 11, and the extended part serves as a field plate 82.

[0042] In the embodiment, the semiconductor substrate 1 can be a substrate commonly used in the field of semiconductor to manufacture LDMOS devices, such as a silicon substrate, a silicon carbide substrate, etc. The semiconductor substrate is of a first doping type. For convenience of description, the embodiment is explained by taking a P-type silicon substrate as an example. In other embodiments, the semiconductor substrate can also be a substrate commonly used in BCD technology, such as an SOI substrate.

[0043] The doping type of the well region 2 is opposite to the doping type of the semiconductor substrate 1. In the embodiment, the well region 2 is N-type doped. As a voltage-withstanding base, the well region 2 is generally a high-voltage deep well, and the doping concentration thereof is greater than the doping concentration of the semiconductor substrate 1 but less than the doping concentration of the body region 4.

[0044] The body region 4 and the drift region 5 are both located in the well region 2 and extend from the surface of the semiconductor substrate 1 into the well region 2. The doping type of the body region 4 is the same as the doping type of the well region 2. In the embodiment, the body region 4 is N-type. In order to form an effective conductive channel, the doping concentration of the body region 4 should be greater than the doping concentration of the well region 2. The doping type of the drift region 5 is the same as the doping type of the semiconductor substrate 1. In the embodiment, the drift region 5 is P-type. In order to reduce the on-resistance and improve the current capability, the doping concentration of the drift region 5 can be greater than the doping concentration of the well region 2.

[0045] In one embodiment, the doping concentration of the well region 2 can be 5 to 10 times the doping concentration of the semiconductor substrate 1, the doping concentration of the body region 4 can be 10 to 100 times the doping concentration of the well region 2, and the doping concentration of the drift region 5 can be 5 to 10 times the doping concentration of the well region 2. For example, the doping concentration of a P-type semiconductor substrate (P-sub) can be in the order of E15, the doping concentration of an N-type well region (HVNW) can be in the order of E15 to E16, the doping concentration of an N-type body region (NW) can be in the order of E17 to E18, and the doping concentration of a P-type drift region (Pdrift) can be in the order of E16 to E17.

[0046] The doping type of the source region 9 and the drain region 11 is opposite to that of the body region 4, and in this embodiment, the doping type of the source region 9 and the drain region 11 is P type. The doping type of the contact region 10 is the same as that of the body region 4, and in this embodiment, the contact region 10 is N type. In order to form a good ohmic contact with the external lead, the contact region 10, the source region 9 and the drain region 11 are all heavily doped.

[0047] The field oxide layer 3 is used to realize device isolation, and in this embodiment, the material of the field oxide layer 3 is silicon oxide, but the present application is not limited thereto. In fact, in the present application, the field "oxide" layer is a concept in a broad sense, and its material is not limited to "oxide", but can also be other materials with insulation properties, such as silicon nitride and the like. The field oxide layer 3 is located on the drift region 5, and more specifically, the orthogonal projection of the field oxide layer 3 on the surface of the semiconductor substrate 1 is located in the orthogonal projection of the drift region 5 on the surface of the semiconductor substrate 1.

[0048] The dielectric constant of the dielectric material layer 6 is greater than that of the field oxide layer 3, which can weaken the peak electric field at the edge of the field plate 82. Taking the material of the field oxide layer 3 as an example, the material of the dielectric material layer 6 can include, but is not limited to, one or a combination of the following high-K dielectric materials: silicon nitride, hafnium oxide, zirconium oxide, hafnium silicon oxynitride, etc. Of course, if the material of the field oxide layer 3 is other material with insulation properties, the material of the dielectric material layer 6 can be determined according to the dielectric constant.

[0049] When the gate voltage applied to the gate 81 exceeds the threshold voltage, the channel region below the gate dielectric layer 7 forms an inversion layer, and a conductive channel is formed between the source region 9 and the drain region 11. In this embodiment, the gate 81 and the field plate 82 belong to two parts with different functions in the same structural entity. For example, after dry etching of the deposited polysilicon layer, the polysilicon layer located above the gate dielectric layer 7 and capable of controlling the formation of the channel and the conductive state is the gate 81, and the polysilicon layer above the field oxide layer 3 and the dielectric material layer 6 and capable of realizing the function of electric field modulation is the field plate 82.

[0050] In the prior art, as a junction termination technology, the purpose of providing the field plate in the semiconductor structure such as LDMOS is to improve the breakdown voltage. However, due to the electrostatic induction effect, the edge of the field plate (the side edge close to the drain region, the same below) will induce high-density charges, resulting in the concentration of electric lines at the edge of the field plate and the formation of edge sharp corner electric field, so that the improvement amplitude of the breakdown voltage of the semiconductor structure is limited and does not reach the theoretical maximum value.

[0051] To solve the above problems, in the embodiment, by locally filling the dielectric material layer 6 in the field oxide region below the field plate 82, actually replacing part of the field oxide layer with the dielectric material layer, and extending the edge of the field plate 82 above the dielectric material layer 6, that is, the field plate 82 covers the dielectric material layer 6, the longitudinal electric field at the end of the field plate 82 can be reduced, the longitudinal electric field distribution on the field plate 82 tends to be more uniform, the total electric field at the edge of the field plate 82 is reduced, and the surface breakdown voltage of the device is closer to the bulk breakdown voltage.

[0052] On this basis, the inventors have found that reasonable control of the lateral width of the dielectric material layer 6, in particular, reasonable control of the ratio (denoted as b) between the lateral width of the dielectric material layer 6 and the lateral width of the field oxide layer 3, is beneficial to better exert the modulation effect of the field plate 82 and effectively improve the breakdown voltage. Specifically, if the ratio is too small, it means that the filling area of the dielectric material layer 6 is too narrow, which is presumed to cause insufficient effective range of the field plate 82 to modulate the electric field, failing to cover and weaken the peak electric field region at the edge of the field plate 82, resulting in limited decline of the peak electric field and poor improvement effect on the breakdown voltage. On the contrary, if the filling area of the dielectric material layer 6 is too wide, the dielectric material layer 6 is presumed to excessively weaken the overall longitudinal electric field below the field plate 82, which is equivalent to shielding the modulation effect of the field plate 82 on the electric field.

[0053] The above-mentioned lateral width refers to the size along the length direction of the channel region, that is, the size in the direction from the source region to the drain region or from the drain region to the source region, that is, the lateral direction in Figure 2 .

[0054] Figure 3 is a top view of the semiconductor structure provided in the embodiment, and the structural identifiers are omitted in the figure for the purpose of simply and clearly showing the lateral size. In combination with Figure 2 , in Figure 3 , L1 is the lateral width of the dielectric material layer 6, L2 is the lateral width of the field oxide layer 3 (ignoring the dielectric material layer), and L3 is the lateral width of the region covered by the field plate 82 on the dielectric material layer 6. Through further simulation, as shown in the simulation results in Figure 4 , the optimal ratio b of the lateral width L1 of the dielectric material layer 6 to the lateral width L2 of the field oxide layer 3 is set to to That is, when the lateral width L1 of the dielectric material layer 6 and the lateral width L2 of the field oxide layer 3 satisfy the following relationship: 1 / 6L2≤L1≤1 / 3L2, or 1 / 6≤b≤1 / 3, b=L1 / L2, the breakdown voltage can be sufficiently improved.

[0055] In this embodiment, the field plate 82 covers a portion of the surface of the dielectric material layer 6. The inventors have discovered that by reasonably controlling the size of the area of ​​the dielectric material layer 6 covered by the field plate 82, particularly the ratio (denoted as c, c = L3 / L1) between the lateral width L3 of the dielectric material layer 6 covered by the field plate 82 and the lateral width L1 of the dielectric material layer 6 itself, the breakdown voltage can be significantly improved. If the ratio is too small, it means that most of the upper part of the dielectric material layer 6 is not covered by the field plate 82; that is, the dielectric material layer 6 extends excessively relative to the edge of the field plate 82. It is speculated that, on the one hand, the portion of the dielectric material layer 6 far from the edge of the field plate 82 cannot effectively weaken the peak electric field; on the other hand, the end of the dielectric material layer 6 far from the edge of the field plate 82 may itself become a new peak electric field point. If the ratio of the two is too large, it indicates that most of the dielectric material layer 6 is covered by the field plate 82. That is, relative to the edge of the field plate 82, the dielectric material layer 6 is excessively recessed below the field plate 82. It is speculated that the dielectric material layer 6 cannot effectively cover the edge region of the field plate 82 where the electric field is strongest, thus resulting in poor attenuation of the peak electric field. After further simulation, such as Figure 5 As shown, the optimal ratio of the lateral width L3 of the area covered by the field plate in the dielectric material layer 6 to the lateral width L1 of the dielectric material 6 itself is set at... to That is, 1 / 2≤c≤2 / 3, or 1 / 2L1≤L3≤2 / 3L1, can significantly improve the breakdown voltage.

[0056] refer to Figure 3 In this embodiment, along the width direction of the channel, i.e. Figure 3 In the longitudinal direction of the channel, the through-groove does not penetrate the entire field oxide layer, and the length of the through-groove is less than the length of the field oxide layer. In other words, the orthographic projection of the field oxide layer on the semiconductor substrate surface completely surrounds the orthographic projection of the through-groove on the semiconductor substrate surface; or, in other words, neither end of the through-groove along the width direction penetrates the field oxide layer, and these two ends are "non-penetrated ends". However, it is not limited to this. In another embodiment, along the width direction of the channel, the through-groove penetrates the entire field oxide layer, that is, the length of the through-groove is equal to the length of the field oxide layer. In yet another embodiment, the through-groove along the width direction... Figure 3 In the longitudinal direction, only one end penetrates the field oxide layer, while the other end is not penetrated. In the above embodiment, if the field oxide layer is not penetrated at only one end or at both ends of the through-hole, the not-penetrated end of the through-hole should extend beyond the gate or be flush with the gate.

[0057] Embodiment 2 of this application provides a semiconductor structure, which is a further improvement based on Embodiment 1. Compared with Embodiment 1, refer to... Figure 6In the semiconductor structure provided by Embodiment Two, the drift region 5 is provided with a doped region 12, which has the same doping type as the drift region 5. In this embodiment, the doping type of the doped region 12 and the drift region 5 is both P type, and the doping concentration of the doped region 12 is greater than that of the drift region 5. By providing the doped region 12 in the drift region 5, the doping concentration of the drift region 5 is locally increased, thereby reducing the on-resistance. In particular, the doped region 12 can be arranged near the surface of the semiconductor substrate 1, i.e., the doped region 12 extends from the surface of the semiconductor substrate 1 into the drift region 5 by a certain distance, and the depth of the doped region 12 is less than the depth of the drift region 5. In this way, the heavily doped doped region 12 increases the ion concentration near the surface of the semiconductor substrate 1, changes the potential distribution of the surface of the semiconductor substrate 1 below the edge of the field plate 82, thereby reducing the potential difference between the edge of the field plate 82 and the underlying drift region 5, and weakening the peak electric field of the edge of the field plate 82. In one embodiment, the doping concentration of the doped region 12 can be 10 to 100 times the doping concentration of the drift region 5.

[0058] In order to better cooperate with the dielectric material layer 6 to achieve the purpose of weakening the peak electric field of the edge of the field plate 82 and improving the device withstand voltage, further reference is made to Figure 6 , the doped region 12 is preferably located directly below the dielectric material layer 6, and the lateral width of the doped region 12 is equal to or greater than the lateral width of the dielectric material layer 6.

[0059] On this basis, the inventors have found that the depth of the doped region 12, or more precisely the ratio of the depth of the doped region to the depth of the drift region 5 (denoted as a), also affects the breakdown voltage to some extent. It is speculated that if the depth of the doped region 12 is too large, it means that too much local heavy doping is introduced into the drift region 5, which will seriously hinder the lateral depletion of the drift region 5 under high voltage, and thus will lead to a decrease in the breakdown voltage. The above speculation is verified by simulation results, as shown in Figure 7 , when the lateral width of the doped region 12 is substantially the same as the lateral width of the through groove, the breakdown voltage decreases when the ratio between the depth of the doped region 12 and the depth of the drift region 5 exceeds 1 / 15. Conversely, if the depth of the doped region 12 is too small, the reduction in on-resistance will be limited, so the ratio a is generally controlled within the range of 1 / 30 to 1 / 15, i.e., 1 / 30≤a≤1 / 15.

[0060] To further highlight the advantages of the semiconductor structure provided by the embodiments of the present application, the applicant provides two structures as comparative examples, Figure 8 and Figure 9 are schematic diagrams of the semiconductor structures in Comparative Example One and Comparative Example Two, respectively. Compared with the embodiments of the present application, in the two comparative examples, the dielectric material layer is no longer filled in the through groove of the through field oxide layer, but is stacked with the "field oxide layer" in a layer structure. Specifically, Figure 8In the shown semiconductor structure, the dielectric material layer 6a is located below the field oxide layer 3, and the lateral width of the dielectric material layer 6a is substantially the same as the lateral width of the field oxide layer 3. Figure 9 In the shown semiconductor structure, the dielectric material layer 6b is located above the field oxide layer 3 and adjacent to the field plate 82, i.e. the field oxide layer 3 is located between the dielectric material layer 6b and the semiconductor substrate 1. For the convenience of comparison, in Example Two and the two above-mentioned Comparative Examples Two, the maximum thickness of the dielectric layer below the field plate is the same, and the volume ratio of the dielectric material layer to the field oxide layer is also substantially the same.

[0061] The simulation results show that the structure of the dielectric material layer in the above two Comparative Examples can improve the breakdown voltage to a certain extent, but compared with the semiconductor structure provided in Example Two of the present application, the semiconductor structure provided in Example Two of the present application has better performance in the three parameters of breakdown voltage, linear region current Idlin and on-resistance Rds(ON), respectively, as shown in Figures 10 to 12 , in which "structure 1" represents the structure shown in Figure 6 (Example Two), "structure 2" represents the structure shown in Figure 8 (Comparative Example One), "structure 3" represents the structure shown in Figure 9 (Comparative Example Two), and "existing technology" represents the structure shown in Figure 1 .

[0062] The above examples take LDMOS devices as examples to explain the semiconductor structure claimed in the present application, but are not limited thereto. In practice, the semiconductor structure can also be an integrated circuit including LDMOS, such as a direct current converter (DCDC), a battery management system (BMS) and the like made by BCD process.

[0063] On the other hand, the present application also provides a preparation method of a semiconductor structure, taking the preparation of an LDMOS device as an example, in combination with Figure 2 and Figure 6 , which specifically includes the following steps:

[0064] Step S1, forming a well region 2 of a second doping type in a semiconductor substrate 1 of a first doping type. In one embodiment, this step can specifically include forming a high-voltage deep N well on a P-type silicon substrate: first forming a 100-200 angstrom thick silicon dioxide film at a temperature of about 1000°C by using high-purity oxygen, then etching the silicon dioxide film to form an ion implantation window, and then implanting phosphorus ions with a concentration of 5-10 times the substrate concentration through the ion implantation window and annealing to obtain a structure as shown in Figure 13a .

[0065] Step S2, forming a field oxide layer 3 on the semiconductor substrate 1. In one embodiment, this step can specifically include growing an isolation oxide layer on the silicon substrate: growing a thick layer of silicon dioxide by means of a furnace tube thermal oxidation, and because the efficiency of wet oxidation is higher, the silicon is generally oxidized by means of H2 and O2 at a temperature of about 1000°C to form 1000-2000 angstroms of silicon dioxide (LOCOS) as the field oxide layer, to obtain a structure as shown in Figure 13b .

[0066] Step S3, forming a body region 4 of the second doping type and a drift region 5 of the first doping type in the well region 2, wherein the orthographic projection of the drift region 5 on the semiconductor substrate 1 encloses the orthographic projection of the field oxide layer 3 on the semiconductor substrate 1.

[0067] The present embodiment does not particularly limit the order of formation of the body region and the drift region, and in one implementation, this step can specifically include forming an N-type body region in the high-pressure deep N well, with the purpose of forming a P-type channel in the low-doped high-pressure deep N well, specifically: after spin-coating photoresist, performing a patterning process to form a mask, and then implanting phosphorus ions with a concentration of 10-100 times that of the high-pressure deep N well, to obtain a structure as shown in Figure 13c ; forming a P-type drift region in the high-pressure deep N well: spin-coating photoresist and performing a patterning process, and then performing boron ion implantation, with the P-type drift region having an implantation concentration of 5-10 times that of the high-pressure deep N well, and after implantation, annealing, to obtain a structure as shown in Figure 13d .

[0068] Step S4, forming a through slot that penetrates the field oxide layer 3. In the present embodiment, this step can specifically include spin-coating photoresist and performing a patterning process to expose part of the area of the LOCOS surface, etching the LOCOS by means of dry etching, with the silicon substrate as the etching stop layer, to form a through slot that penetrates the thickness of the LOCOS, and then removing the photoresist, to obtain a structure as shown in Figure 13e .

[0069] wherein, along the lateral direction in Figure 13e , the ratio between the lateral width of the through slot and the lateral width of the field oxide layer 3 can be set to

[0070] ​Step S5, filling the through slot with a dielectric material to form a dielectric material layer 6, wherein the dielectric constant of the dielectric material layer 6 is greater than that of the field oxide layer 3. As mentioned above, the material of the field oxide layer 3 is silicon dioxide, and the material of the dielectric material layer 6 can include, but is not limited to, one or a combination of the following materials: silicon nitride, hafnium oxide, zirconium oxide, hafnium silicon oxynitride, etc. Taking silicon nitride as an example of the dielectric material, this step can specifically include depositing silicon nitride by a CVD process or the like, and then etching the silicon nitride layer using the remaining field oxide layer 3 as an etching stop layer, so that the dielectric material layer 6 is substantially flush with the surface of the field oxide layer 3, and the dielectric material layer 6 is substantially consistent with the surface of the field oxide layer 3, thereby obtaining a structure as shown in FIG. 6. Figure 13f

[0071] Step S6, forming a gate dielectric layer 7 on the body region 4. In this embodiment, this step can specifically include obtaining the gate dielectric layer 7 by furnace tube thermal oxidation and patterning, thereby obtaining a structure as shown in FIG. 7, wherein the gate dielectric layer 7 is connected to the field oxide layer 3. Figure 13g

[0072] Step S7, forming a gate electrode 81 on the gate dielectric layer 7, and forming a field plate 82 on the dielectric material layer 6 and the field oxide layer 3. In this embodiment, this step can specifically include depositing polysilicon with a thickness of about 2000 angstroms by LPCVD, and then patterning the polysilicon to form the gate electrode 81 covering the gate dielectric layer 7, and the field plate 82 covering the dielectric material layer 6 and the field oxide layer 3, thereby obtaining a structure as shown in FIG. 8. The gate electrode 81 and the field plate 82 are an integral structure, and can be regarded as the gate electrode 81 extending to the field oxide layer 3 and covering the dielectric material layer 6 on the side of the N-type body region. Figure 13h

[0073] Figure 13h

[0074] Step S8, forming a source region 9 and a drain region 11 of a second doping type in the body region 4 and the drift region 5, respectively, and forming a contact region 10 of a first doping type in the body region 4, wherein the drain region 11 is located on the side of the field oxide layer 3 away from the contact region 10. In this embodiment, this step can specifically include first defining an ion implantation window of the source / drain region by a photolithography process, implanting heavily doped P-type impurities into the body region 4 and the drift region 5 to form the source region 9 and the drain region 11, respectively; then defining an ion implantation window of the contact region 10 by a photolithography process, implanting heavily doped N-type ions into the body region 4 through the ion implantation window to form the contact region 10, and finally obtaining a structure as shown in FIG. 9. Figure 13i ​​​​​​The structure shown. In other embodiments, the contact region can also be formed first, and then the source / drain region is formed, without particular limitation.

[0075] Using the process route described above, the semiconductor structure in Embodiment One can be prepared, and on this basis, the process steps can be adjusted to obtain the semiconductor structure in other embodiments.

[0076] For example, for the semiconductor structure in Embodiment Two, after the aforementioned step S3, ion implantation is performed through the field oxide layer 3 to form a doped region 12 of the first doping type in the drift region 5, to obtain a structure as shown in Figure 13j The doping concentration of the doped region 12 is greater than the doping concentration of the drift region 5. This step can specifically include spin-coating photoresist and performing a patterning process to expose part of the surface of the field oxide layer 3, and then performing ion implantation and annealing to form the doped region 12 in the drift region 5. In order to prevent the doped region from excessively affecting the ion concentration on the surface of the drift region after annealing, rapid thermal annealing (RTP) is used, and the implantation concentration of the doped region can be 10-100 times the concentration of the drift region. The mask used in this embodiment can be the same mask as in subsequent step S4.

[0077] The ratio between the depth of the doped region 12 and the depth of the drift region 5 can be set to to so as to maximize the breakdown voltage. Moreover, in actual production, too large or too small implantation energy will lead to an increase in process difficulty, and therefore, by controlling the depth ratio of the doped region 12 within the above range, the process difficulty will not be increased, which is conducive to actual mass production.

[0078] In addition to forming the doped region between steps S3 and S4, in another implementation, the doped region 12 can also be formed first after step S4 by using the through slot, i.e., the doped region 12 is formed before the filling of the dielectric material, specifically: ion implantation is performed through the through slot to form a doped region 12 of the first doping type in the drift region 5, as shown in Figure 13k Then the aforementioned step S5 is continued. This implementation is particularly suitable for the case where the thickness of the field oxide layer is high.

[0079] It should be noted that, Figure 13k The doped region 12 is consistent with the width of the through slot, but is not limited thereto, and in the subsequent thermal annealing process, due to the diffusion of ions, especially lateral diffusion, the lateral width of the doped region 12 is slightly greater than the lateral width of the through slot and the dielectric material layer 6.

[0080] It should be noted that although the steps in the above embodiments are described in a specific order, those skilled in the art can understand that, in order to achieve the effects of the present application, the different steps do not have to be executed in such an order, and they can be executed simultaneously (in parallel) or in other orders, and these changes are within the protection scope of the present application.

[0081] So far, the technical solution of the present application has been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical solutions after these changes or replacements will all fall within the protection scope of the present application.

Claims

1. A semiconductor structure, characterized by, Comprising: a semiconductor substrate; a well region in the semiconductor substrate; a body region and a drift region in the well region; a source region and a contact region in the body region; a drain region in the drift region; a gate dielectric layer and a field oxide layer on the surface of the semiconductor substrate, the field oxide layer being between the gate dielectric layer and the drain region; a through slot in the field oxide layer, the through slot penetrating the field oxide layer, the through slot being filled with a dielectric material layer, wherein the dielectric constant of the dielectric material layer is greater than the dielectric constant of the field oxide layer; a gate on the gate dielectric layer, the gate extending to cover the dielectric material layer as a field plate.

2. The semiconductor structure of claim 1, wherein, Further comprising a doped region in the drift region, the doped region being adjacent to the dielectric material layer, wherein the doped region is of the same doping type as the drift region and has a doping concentration greater than the doping concentration of the drift region.

3. The semiconductor structure of claim 2, wherein, The orthogonal projection of the doped region on the surface of the semiconductor substrate corresponds to the orthogonal projection of the dielectric material layer on the surface of the semiconductor substrate.

4. The semiconductor structure according to claim 2 or 3, characterized in that The ratio a of the depth of the doped region to the depth of the drift region satisfies:

5. The semiconductor structure of any of claims 1-4, wherein, In the direction from the source region to the drain region, the dielectric material layer satisfies at least one of the following conditions: The ratio b of the lateral width of the dielectric material layer to the lateral width of the field oxide layer satisfies: The ratio c of the lateral width of the field plate covering area to the lateral width of the dielectric material layer satisfies:

6. A method of fabricating a semiconductor structure, characterized by, Comprising the following steps: forming a body region and a drift region in a well region of a semiconductor substrate; forming a source region and a drain region in the body region and the drift region, respectively, and forming a contact region in the body region; forming a gate dielectric layer and a field oxide layer on the surface of the semiconductor substrate, wherein the orthogonal projection of the field oxide layer on the surface of the semiconductor substrate is within the orthogonal projection of the drift region on the surface of the semiconductor substrate, and the field oxide layer is between the gate dielectric layer and the drain region; forming a through slot penetrating the field oxide layer; filling the through slot with a dielectric material to obtain a dielectric material layer, wherein the dielectric constant of the dielectric material layer is greater than the dielectric constant of the field oxide layer; forming a gate and a field plate, the gate being on the gate dielectric layer and extending to cover the dielectric material layer as the field plate.

7. The production method according to claim 6, characterized by, Before forming the through slot penetrating the field oxide layer, or before filling the through slot with a dielectric material, further comprising: forming a doped region in the drift region, the doped region extending from the surface of the semiconductor substrate into the drift region, wherein the doped region is of the same doping type as the drift region and has a doping concentration greater than the doping concentration of the drift region.

8. The production method according to claim 7, characterized by, The orthogonal projection of the doped region on the semiconductor substrate corresponds to the orthogonal projection of the dielectric material layer on the semiconductor substrate.

9. The production method according to claim 7 or 8, characterized by, The ratio a of the depth of the doped region to the depth of the drift region satisfies:

10. The method of any one of claims 6-9, wherein, The dielectric material layer satisfies at least one of the following conditions: The ratio b of the lateral width of the dielectric layer material layer to the lateral width of the field oxide layer satisfies: The ratio c of the lateral width of the area of the dielectric material layer covered by the field plate to the lateral width of the dielectric material layer satisfies:

Images