Semiconductor device and method of manufacturing the same
By introducing a high-density shielding design into the semiconductor device, the reverse leakage current problem is solved, the power consumption of the component is reduced, and the current efficiency and reliability are improved.
Patent Information
- Application Number
- CN202410867913.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-01
- Publication Date
- 2026-01-09
AI Technical Summary
In semiconductor devices, as size shrinks and well depth becomes shallower, reverse leakage current (IDSS) problems occur frequently, affecting device performance.
In semiconductor devices, a high-concentration first and second shielding region is introduced. The carrier concentration gradient design of the shielding region forms a barrier to reduce reverse leakage current, especially when a shielding region is set between the junction field-effect transistor region and the well region.
It significantly reduces reverse leakage current, reduces component power consumption, and improves the current efficiency and reliability of semiconductor devices.
Smart Images
Figure CN121310595A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. BACKGROUND
[0002] With the rapid development of semiconductor industry in recent years, the size of semiconductor devices is getting smaller and smaller, and the design depth of the well region is getting shallower (less than one micron). In this case, the reverse drain-source leakage current (IDSS) often becomes a big problem for semiconductor elements. Therefore, there is a need for a semiconductor element that can solve the problem of reverse drain-source leakage current. SUMMARY
[0003] One technical aspect of the present disclosure is a semiconductor device.
[0004] According to one embodiment of the present disclosure, a semiconductor device includes a substrate, a drift region, a well region, a first shield region, a junction field effect transistor region, a source region, and a gate structure. The drift region is located within the substrate. The well region is located within the drift region. The first shield region is located within the drift region, wherein a bottom surface of the first shield region is lower than a bottom surface of the well region and a carrier concentration of the first shield region is higher than a carrier concentration of the well region. The junction field effect transistor region is located within the drift region, wherein a bottom surface of the junction field effect transistor region is lower than a bottom surface of the first shield region, and a first portion of the first shield region is located between the well region and the junction field effect transistor region. The source region is adjacent to the well region. The gate structure is located on the drift region.
[0005] In one embodiment of the present disclosure, a second portion of the first shield region extends to the bottom surface of the well region.
[0006] In one embodiment of the present disclosure, the semiconductor device further includes a second shield region. The second shield region is located within the drift region.
[0007] Another technical aspect of the present disclosure is a semiconductor device.
[0008] According to one embodiment of the present disclosure, a semiconductor device includes a substrate, a gate structure, a plurality of well regions, a plurality of first shield regions, a plurality of second shield regions, a junction field effect transistor region, and a source region. The gate structure is located on the substrate. The well regions are located within the substrate and on both sides of the gate structure. The first shield regions are located within the substrate and on both sides of the gate structure, wherein a bottom surface of the first shield regions is lower than a bottom surface of the well regions and a carrier concentration of the first shield regions is higher than a carrier concentration of the well regions. The second shield regions are located within the substrate and on both sides of the gate structure, wherein a bottom surface of the second shield regions is lower than a bottom surface of the first shield regions and a carrier concentration of the second shield regions is higher than a carrier concentration of the first shield regions. The junction field effect transistor region is located within the substrate, wherein a bottom surface of the junction field effect transistor region is lower than a bottom surface of the second shield regions. The source region is adjacent to the well regions.
[0009] In one embodiment of the present disclosure, the carrier concentration of the second shielding region is approximately twice that of the first shielding region.
[0010] In one embodiment of the present disclosure, the sidewall of one of the second shielding regions is cut to the sidewall of one of the first shielding regions.
[0011] In one embodiment of the present disclosure, the top surface of one of the second shielding regions is lower than the top surface of the substrate.
[0012] In one embodiment of the present disclosure, the top surface of one of the second shielding regions is lower than the top surface of one of the first shielding regions.
[0013] Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.
[0014] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a drift region in a substrate; forming a first shielding region in the drift region; forming a second shielding region in the drift region, wherein the carrier concentration of the first shielding region is higher than that of the second shielding region; forming a well region in the drift region, wherein the carrier concentration of the second shielding region is higher than that of the well region; forming a source region in the well region; forming a junction field effect transistor region in the drift region; and forming a gate structure on the drift region.
[0015] In one embodiment of the present disclosure, the second shielding region is formed in the drift region such that the sidewall of a portion of the second shielding region is cut to the sidewall of the first shielding region.
[0016] In the above-mentioned embodiments of the present disclosure, since the shielding region is provided between the junction field effect transistor region and the well region, the problem of reverse leakage current can be significantly solved, reducing the impact of reverse leakage current on the power consumption of the element. BRIEF DESCRIPTION OF DRAWINGS
[0017] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art(s) to make and use the applications. Figure One The aspects of the disclosure will be best understood by reference to the following embodiments. It should be noted that various features will not be discussed with respect to each and every embodiment, but various specific details are set forth herein to cast a light on realizing the aspects of the present disclosure. In actual practice, the dimensions of the features can be arbitrarily increased or decreased for the sake of clarity in the description.
[0018] Figures 1 to 4 FIG. 1 shows a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure during a manufacturing process.
[0019] Figure 5 FIG. 2 shows a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.
[0020] Figure 6 FIG. 3 shows a cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure.
[0021] Figure 7 A cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown. Detailed Implementation
[0022] The following description of embodiments provides numerous different implementations, or examples, for carrying out various features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity purposes and does not in itself specify the relationship between the various embodiments and / or configurations discussed.
[0023] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.
[0024] As used herein, “about,” “approximately,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” or “substantially” may be used to select a more acceptable range of deviations or standard deviations depending on the optical, etched, or other properties, and not necessarily apply to all properties with a single standard deviation.
[0025] Figures 1 to 4 A cross-sectional view is shown to illustrate the manufacturing process of a semiconductor device 100 according to an embodiment of this disclosure. (Refer to...) Figure 1 and Figure 2 The semiconductor device fabrication process first forms a drift region 112 within a substrate 110. Next, a first shielding region 120 is formed within the drift region 112. The first shielding region 120 can be formed using diffusion, ion implantation, or any suitable method. Then, a second shielding region 130 is formed within the drift region 112, wherein the carrier concentration of the first shielding region 120 is higher than the carrier concentration of the second shielding region 130. In some embodiments, the carrier concentration of the first shielding region 120 is approximately twice the carrier concentration of the second shielding region 130. For example, the carrier concentration of the second shielding region 130 is 1 × 10⁻⁶.17 cm -3 Up to 1×10 19 cm -3 Within the range, the carrier concentration in the first shielding region 120 is 2 × 10⁻⁶. 17 cm -3 Up to 2×10 19 cm -3 Within the range. The second shielding region 130 can be formed using diffusion, ion implantation, or any suitable method. Furthermore, a portion 124 of the first shielding region 120 extends below the bottom surface 131 of the second shielding region 130.
[0026] Reference Figure 2 Next, a well region 140 is formed within the drift region 112, wherein the carrier concentration of the second shielding region 130 is higher than that of the well region 140. For example, the carrier concentration of the well region 140 is 5 × 10⁻⁶. 16 cm -3 Up to 1×10 18 cm -3 Within the range. That is, in some embodiments, the dopant concentration of the first shielding region 120 is higher than the dopant concentration of the second shielding region 130, and the dopant concentration of the second shielding region 130 is higher than the dopant concentration of the well region 140. In some embodiments, the first shielding region 120, the second shielding region 130, and the well region 140 may have the same first conductivity type, such as a P-type region, and may contain P-type dopants. The well region 140 may be formed using diffusion, ion implantation, or any suitable method. Furthermore, the second shielding region 130 has a first portion 132 located between the well region 140 and the first shielding region 120.
[0027] Reference Figure 3 Next, a source region 150 is formed within the well region 140. The source region 150 can be formed using diffusion, ion implantation, or any suitable method. Next, a junction field-effect transistor region 160 is formed within the drift region 112. In some embodiments, the bottom surface 161 of the junction field-effect transistor region 160 is lower than the bottom surface 121 of the first shielding region 120, and a first portion 122 of the first shielding region 120 is located between the well region 140 and the junction field-effect transistor region 160. In some embodiments, the drift region 112 and the junction field-effect transistor region 160 may have the same second conductivity type, such as an N-type region, and may contain N-type doped species.
[0028] Reference Figure 4Next, a gate structure 170 is formed on the drift region 112. The gate structure 170 includes a gate conductive layer 172 and a gate dielectric layer 174. In some embodiments, the gate dielectric layer 174 is first uniformly deposited on the drift region 112 by deposition or other suitable methods, followed by the deposition of the gate conductive layer 172. Then, the gate conductive layer 172 and the gate dielectric layer 174 are patterned to form the gate structure 170. In some embodiments, the gate conductive layer 172 comprises a conductive material, such as a metal or polysilicon, but is not limited thereto. In some embodiments, the gate dielectric layer 174 comprises a dielectric material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or a high dielectric constant dielectric material, but is not limited thereto.
[0029] Next, a dielectric layer 173 is formed to cover the gate structure 170. In some embodiments, the dielectric layer 173 may include a suitable dielectric material, such as silicon oxide, silicon nitride, or the like.
[0030] Next, a source pad 190 is formed on the gate structure 170 and the drift region 112. In some embodiments, the source pad 190 comprises a conductive material, such as metal or polysilicon, but is not limited thereto. Next, a drain pad 180 is formed on the side of the substrate 110 opposite to the drift region 112. At this point, the semiconductor device 100 is manufactured. In some embodiments, the drain pad 180 comprises a conductive material, such as metal or polysilicon, but is not limited thereto.
[0031] Because a shielding region (e.g., a first shielding region 120 and a second shielding region 130) is provided between the junction field-effect transistor region 160 and the well region 140, the problem of reverse leakage current can be significantly solved, reducing the impact of reverse leakage current on the power consumption of the device.
[0032] In the following description, different types of semiconductor devices will be described.
[0033] Figure 5 A cross-sectional view of a semiconductor device 100a according to another embodiment of this disclosure is shown. (Refer to...) Figure 5Semiconductor device 100a includes a substrate 110, a gate structure 170, a plurality of well regions 140, a plurality of first shielding regions 120a, a plurality of second shielding regions 130, a junction field-effect transistor region 160, and a source region 150. The gate structure 170 is located on the substrate 110. The well regions 140 are located within the substrate 110 and on both sides of the gate structure 170. The second shielding regions 130 are located within the substrate 110 and on both sides of the gate structure 170, wherein the bottom surface 131 of the second shielding region 130 is lower than the bottom surface 141 of the well region 140, and the carrier concentration of the second shielding region 130 is higher than that of the well region 140. The first shielding regions 120a are located within the substrate 110 and on both sides of the gate structure 170, wherein the bottom surface 121a of the first shielding region 120a is lower than the bottom surface 131 of the second shielding region 130, and the carrier concentration of the first shielding region 120a is higher than that of the second shielding region 130. A junction field-effect transistor region 160 is located within the substrate 110, wherein the bottom surface 161 of the junction field-effect transistor region 160 is lower than the bottom surface 121a of the first shielding region 120a. A source region 150 is adjacent to a well region 140. A gate structure 170 includes a gate conductive layer 172, a dielectric layer 173, and a gate dielectric layer 174. Furthermore, the semiconductor device 100a also includes a drain pad 180 and a source pad 190. The drain pad 180 is located on the surface of the substrate 110 relative to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170. Additionally, in this embodiment, the top surface 123a of the first shielding region 120a is lower than the top surface 113 of the substrate.
[0034] Figure 6 A cross-sectional view of a semiconductor device 100b according to yet another embodiment of this disclosure is shown. (Refer to...) Figure 6Semiconductor device 100b includes a substrate 110, a gate structure 170, a plurality of well regions 140, a plurality of first shielding regions 120b, a plurality of second shielding regions 130, a junction field-effect transistor region 160, and a source region 150. The gate structure 170 is located on the substrate 110. The well regions 140 are located within the substrate 110 and on both sides of the gate structure 170. The second shielding regions 130 are located within the substrate 110 and on both sides of the gate structure 170, wherein the bottom surface 131 of the second shielding region 130 is lower than the bottom surface 141 of the well region 140, and the carrier concentration of the second shielding region 130 is higher than that of the well region 140. The first shielding regions 120b are located within the substrate 110 and on both sides of the gate structure 170, wherein the bottom surface 121b of the first shielding region 120b is lower than the bottom surface 131 of the second shielding region 130, and the carrier concentration of the first shielding region 120b is higher than that of the second shielding region 130. A junction field-effect transistor region 160 is located within the substrate 110, wherein the bottom surface 161 of the junction field-effect transistor region 160 is lower than the bottom surface 121b of the first shielding region 120b. A source region 150 is adjacent to a well region 140. A gate structure 170 includes a gate conductive layer 172, a dielectric layer 173, and a gate dielectric layer 174. Furthermore, the semiconductor device 100a also includes a drain pad 180 and a source pad 190. The drain pad 180 is located on the surface of the substrate 110 relative to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170. In this embodiment, the sidewall 125b of the first shielding region 120b is flush with the sidewall 133 of the second shielding region 130.
[0035] Figure 7This is a cross-sectional view illustrating a semiconductor device 100c according to another embodiment of the present disclosure. The semiconductor device 100c includes a substrate 110, a drift region 112, a well region 140, a first shielding region 120, a junction field-effect transistor region 160, a source region 150, and a gate structure 170. The drift region 112 is located within the substrate 110. The well region 140 is located within the drift region 112. The first shielding region 120 is located within the drift region 112, wherein the bottom surface 121 of the first shielding region 120 is lower than the bottom surface 141 of the well region 140, and the carrier concentration of the first shielding region 120 is higher than the carrier concentration of the well region 140. A junction field-effect transistor (FET) region 160 is located within a drift region 112, wherein the bottom surface 161 of the FET region 160 is lower than the bottom surface 121 of a first shielding region 120, and a first portion 122 of the first shielding region 120 is located between the well region 140 and the FET region 160. A second portion 124 of the first shielding region 120 extends to the bottom surface 141 of the well region 140. A source region 150 is adjacent to the well region 140. A gate structure 170 is located on the drift region 112. The gate structure 170 includes a gate conductive layer 172, a dielectric layer 173, and a gate dielectric layer 174. Furthermore, the semiconductor device 100a also includes a drain pad 180 and a source pad 190. The drain pad 180 is located on the surface of the substrate 110 on one side relative to the drift region 112. The source pad 190 is located on the drift region 112 and the gate structure 170.
[0036] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.
[0037] [Symbol Explanation]
[0038] 100, 100a, 100b, 100c: Semiconductor devices
[0039] 110:Substrate
[0040] 112: Drift Zone
[0041] 113: Top surface
[0042] 120, 120a, 120b: First shielding zone
[0043] 121, 121a, 121b: Bottom surface
[0044] 122: Part One
[0045] 123a: Top surface
[0046] 124: Part
[0047] 125b: Sidewall
[0048] 130: Second shielding zone
[0049] 131: Bottom surface
[0050] 132: Part One
[0051] 133: Sidewall
[0052] 140: Tunnel
[0053] 141: Bottom
[0054] 150: Source Region
[0055] 160: Junction Field-Effect Transistor Region
[0056] 161: Bottom
[0057] 170: Gate structure
[0058] 172: Gate conductive layer
[0059] 173: Dielectric layer
[0060] 174: Gate dielectric layer
[0061] 180: Drain pad
[0062] 190: Source pad.
Claims
1. A semiconductor device, characterized in that, Include: substrate; The drift region is located within the substrate; The trap region is located within the drift region; A first shielding region is located within the drift region, wherein the bottom surface of the first shielding region is lower than the bottom surface of the well region and the carrier concentration of the first shielding region is higher than the carrier concentration of the well region. A junction field-effect transistor region is located within the drift region, wherein the bottom surface of the junction field-effect transistor region is lower than the bottom surface of the first shielding region, and a first portion of the first shielding region is located between the well region and the junction field-effect transistor region. The source region is adjacent to the well region; as well as The gate structure is located on the drift region.
2. The semiconductor device according to claim 1, characterized in that, The second part of the first shielding zone extends to the bottom surface of the trap area.
3. The semiconductor device according to claim 1, characterized in that, It also includes a second shielding zone, located within the drift zone.
4. A semiconductor device, characterized in that, Include: substrate; The gate structure is located on the substrate; Multiple well regions are located within the substrate and on both sides of the gate structure; A plurality of first shielding regions are located within the substrate and on both sides of the gate structure, wherein the bottom surface of the plurality of first shielding regions is lower than the bottom surface of the plurality of well regions and the carrier concentration of the plurality of first shielding regions is higher than the carrier concentration of the plurality of well regions; Multiple second shielding regions are located within the substrate and on both sides of the gate structure, wherein the bottom surface of the multiple second shielding regions is lower than the bottom surface of the multiple first shielding regions and the carrier concentration of the multiple second shielding regions is higher than the carrier concentration of the multiple first shielding regions; A junction field-effect transistor region is located within the substrate, wherein the bottom surface of the junction field-effect transistor region is lower than the bottom surface of the plurality of second shielding regions; as well as The source region is adjacent to the plurality of well regions.
5. The semiconductor device according to claim 4, characterized in that, The carrier concentration in the plurality of second shielding regions is approximately twice the carrier concentration in the plurality of first shielding regions.
6. The semiconductor device according to claim 4, characterized in that, The sidewall of one of the plurality of second shielding zones is flush with the sidewall of one of the plurality of first shielding zones.
7. The semiconductor device according to claim 4, characterized in that, The top surface of one of the plurality of second shielding areas is lower than the top surface of the substrate.
8. The semiconductor device according to claim 7, characterized in that, The top surface of one of the plurality of second shielding zones is lower than the top surface of one of the plurality of first shielding zones.
9. A method for manufacturing a semiconductor device, characterized in that, Include: A drift region is formed within the substrate; A first shielding zone is formed within this drift zone; A second shielding region is formed within the drift region, wherein the carrier concentration of the first shielding region is higher than that of the second shielding region; A trap region is formed within the drift region, wherein the carrier concentration in the second shielding region is higher than the carrier concentration in the trap region; A source region is formed within this trap region; A junction field-effect transistor region is formed within this drift region; and A gate structure is formed on this drift region.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The second shielding area is formed within the drift zone such that a portion of the sidewall of the second shielding area is flush with the sidewall of the first shielding area.