Wideband amplifier with bulk resistance

Abstract

The invention relates to a broadband amplifier with bulk resistance. An integrated circuit includes a first transistor (M1, Fig. 1) and a second transistor (M2). A first current path terminal (M2 source) of the second transistor is coupled to a reference voltage terminal (AVss). A first current path terminal (source of M1) of the first transistor is coupled to a second current path terminal (drain of M2) of the second transistor. A second current path terminal (drain of M1) of the first transistor is coupled to a first differential output terminal (Vop). The control terminal (M2 gate) of the second transistor is coupled to the first differential input terminal (Vip). The integrated circuit includes a first resistor (202) having a first terminal and a second terminal. The first terminal is coupled to the body terminal (M1 body or main body) of the first transistor, and the second terminal is coupled to a reference voltage terminal (AVss). A first resistor (202) is disposed in the dielectric layer (i.e., 406 of figures 4 and 5) over the first and second transistors.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of Indian Provisional Application No. 202441053406, filed July 12, 2024, entitled “RX-TX PORT COMBINED WIDE BAND LNA & PA USING BULK RESISTANCE IN PA,” the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to an electronic system, and in particular embodiments, to a wideband amplifier with bulk resistance. BACKGROUND

[0004] Amplifiers are common components in many fields, such as in the field of communication circuitry. In some cases, amplifiers are implemented with a wide operating bandwidth. SUMMARY

[0005] According to embodiments, an integrated circuit includes a first transistor disposed in or over a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a bulk terminal, wherein the second current path terminal of the first transistor is coupled to a first differential output terminal of a pair of differential output terminals; a second transistor disposed in or over the semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a bulk terminal, wherein the control terminal of the second transistor is coupled to a first differential input terminal of a pair of differential input terminals, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and the first current path terminal of the second transistor is coupled to a reference voltage terminal; and a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the bulk terminal of the first transistor, and the second terminal of the first resistor is coupled to the reference voltage terminal, and wherein the first resistor is disposed in a dielectric layer over the first transistor and the second transistor.

[0006] According to an embodiment, an amplifier includes a first output terminal and a second output terminal; a first input terminal and a second input terminal; a semiconductor substrate; a first transistor disposed in or over the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal, and a control terminal, the second current path terminal of the first transistor coupled to the first output terminal; a second transistor disposed in or over the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal, and a control terminal, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and wherein the control terminal of the second transistor is coupled to the first input terminal; a first resistor disposed in a dielectric layer over the semiconductor substrate, the first resistor having a first terminal and a second terminal, the first terminal coupled to the body terminal of the first transistor, wherein the first resistor is disposed between the first transistor and the second transistor in a first direction as viewed from a top view; a third transistor disposed in or over the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal, and a control terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the first transistor; a fourth transistor disposed in or over the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal, and a control terminal, wherein the second current path terminal of the fourth transistor is coupled to the first current path terminal of the third transistor; and a second resistor disposed in the dielectric layer and having a first terminal and a second terminal, the first terminal coupled to the body terminal of the third transistor, wherein the first resistor is disposed between the third transistor and the fourth transistor in the first direction as viewed from a top view, and wherein the first transistor and the second transistor are each laterally offset from the third transistor and the fourth transistor, respectively, by a first distance as viewed from a top view and in a second direction perpendicular to the first direction.

[0007] According to an embodiment, a circuit includes an antenna terminal; a first amplifier having an input coupled to the antenna terminal; a balun; a switch coupled between the balun and the antenna terminal; and a second amplifier having an output coupled to the antenna terminal through the balun and the switch, and wherein the output of the second amplifier is coupled to the input of the first amplifier through the balun and the switch, the second amplifier includes: a first transistor pair having a first differential input terminal, a first differential output terminal, a first bulk terminal, and a second bulk terminal, wherein the first bulk terminal of the first transistor pair is coupled to a reference voltage terminal; a second transistor pair coupled to the first transistor pair, the second transistor pair having a second differential input terminal, a second differential output terminal, a first bulk terminal, and a second bulk terminal, wherein the first bulk terminal of the second transistor pair is coupled to the reference voltage terminal; a first resistor having a first terminal coupled to the second bulk terminal of the first transistor pair and a second terminal coupled to the reference voltage terminal; and a second resistor having a first terminal coupled to the second bulk terminal of the second transistor pair and a second terminal coupled to the reference voltage terminal, wherein the first differential output terminal and the second differential output terminal are coupled to the balun. BRIEF DESCRIPTION OF DRAWINGS

[0008] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

[0009] Figure 1 Illustrating a transceiver having transmit (Tx) circuitry, receive (Rx) circuitry, and an antenna;

[0010] Figure 2 Illustrating a circuit having an amplifier with a bulk resistance;

[0011] Figure 3 Illustrating Figure 2 a top view of an amplifier having a resistor coupled between a bulk terminal of a transistor and a reference voltage;

[0012] Figures 4 to 6 Illustrating a cross-sectional view of a semiconductor device having a transistor and an associated resistor from Figures 2 to 3

[0013] Figure 7 Illustrating a system having a transceiver including an impedance and bandwidth matching system; and

[0014] Figure 8 showing Figure 7 a plot of simulated reflection coefficients for a system.

[0015] ​Corresponding reference characters in different drawings indicate corresponding parts unless otherwise indicated. Drawings are drawn for clarity of relevant aspects of the preferred embodiments and the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0016] The making and using of the disclosed embodiments are discussed in detail below. It should be appreciated that the disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure and do not limit the scope of the disclosure.

[0017] The following description sets forth various specific details, relationships, and methods, to provide a thorough understanding of the present disclosure. The present disclosure, however, can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In some instances, well-known structures, materials, or operations have not been shown or described in detail in order to avoid obscuring aspects of the embodiments. Reference throughout this description to "embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearances of the phrase "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular forms, structures, or features described in this description are meant to be illustrative only and not limiting as the particular forms, structures, or features can vary in other embodiments.

[0018] Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the present disclosure. The present disclosure is not limited to the

[0019] Some embodiments herein relate to amplifiers that use body resistance to improve operating bandwidth.

[0020] Wireless communication systems benefit from operating over a wide instantaneous bandwidth. In particular, port combined transceivers can employ shared antenna ports for both transmission (Tx) and reception (Rx) operations, enabling wideband operation without the need to provide separate ports for each function. Wideband operation enables higher data transfer rates, reduced latency, and increased capacity and connectivity. However, since power amplifiers (PAs) and low noise amplifiers (LNAs) in port combined transceivers support a wider bandwidth, several challenges can arise that impede operation.

[0021] For example, a transmit amplifier and a low noise amplifier (LNA) for reception can share a common port in a transceiver connected to an antenna, facilitating operation in either a Tx mode or a Rx mode. However, during the Rx mode, the transmit amplifier can reduce the input impedance of the LNA in wide bandwidth applications. In some implementations, a capacitive load associated with the transmit amplifier can limit the bandwidth of the LNA, constraining overall transceiver performance in the Rx mode. Accordingly, techniques for reducing the quality factor (Q) of the transmit amplifier over a wide bandwidth, as observed at the LNA input, can improve the bandwidth of a port-combined transceiver.

[0022] Various aspects described herein relate to amplifiers that include a resistance between the body terminal (or bulk terminal) of one or more transistors and a reference voltage terminal (ground terminal) to reduce the quality factor (Q-factor) of the amplifier and reduce insertion loss in a receive mode over a wide bandwidth. Some techniques described herein provide an arrangement in which the spacing between transistors within a semiconductor substrate establishes an impedance that is greater than the resistance between the body terminal of the transistors and the reference voltage terminal. Accordingly, crosstalk between the transistors is mitigated, and voltage is coupled through the resistance, reducing the capacitive load of the amplifier as observed by the LNA when the LNA is configured for reception.

[0023] The resistance can be implemented using one or more resistors formed from conductive traces within a dielectric layer of an interconnect structure above the semiconductor substrate. Accordingly, a via or wire can connect the body terminal of a transistor to a corresponding resistor, which in turn is connected to the reference voltage terminal. In some embodiments, the resistors can be polysilicon resistors. This arrangement can advantageously provide a compact footprint for the amplifier without the need to introduce or use additional processing steps to form a deep well, such as a deep n-well or a deep p-well, to reduce the capacitive load of the amplifier. Accordingly, in some embodiments, a manufacturing process without a deep n-well or a deep p-well can be used while still mitigating crosstalk between the transistors. Aspects described herein can be beneficial for Wifi applications, for example spanning 5 gigahertz (GHz) to 7 GHz bands, and other wireless communication protocols, such as Ultra-Wideband (UWB), such as using IEEE 802.15.4z.

[0024] Figure 1 A transceiver 100 is shown having transmit (Tx) circuitry 102, receive (Rx) circuitry 104, and an antenna 106.

[0025] The Tx circuitry 102 includes an amplifier 110 (also referred to as a power amplifier or a transmission amplifier) having differential input terminals Vip, Vin and having differential output terminals Vop, Vom. A pair of capacitors 112 are connected in series with each other between the output terminals (Vop, Vom) of the amplifier 110. The pair of capacitors 112 are connected in parallel with a balun 114 (also referred to as a transformer). A switch 108 is connected between the Tx circuitry 102 and the Rx circuitry 104 to facilitate an Rx mode of operation or a Tx mode of operation with the antenna 106. Further, a capacitor 118 is coupled between the antenna 106 and the Rx circuitry 102. Thus, signals to and / or from the antenna 106 can be coupled through two separate branches: one branch includes the capacitor 118 to the Rx circuitry 104, and the other branch from the balun 114 to the Tx circuitry 102.

[0026] In the Tx mode, the switch 108 is closed, connecting the Tx circuitry 102 to the antenna 106 through an antenna terminal 116 (such as an input / output pin). The pair of capacitors 112, together with the balun 114, are configured as part of a matching network to optimize power transfer from the amplifier 110 to the antenna 106. The balun 114 can facilitate signal conversion from the amplifier 110 to the antenna 106 to optimize power transfer to the antenna 106. In the Tx mode, the Rx circuitry 104 can be in a deactivated or non-receiving state.

[0027] In the Rx mode, the switch 108 is open, and the Rx circuitry 104, including a LNA, can be activated and connected to the antenna 106 through the antenna terminal 116. Thus, the transceiver 100 can be described as a port-combined transceiver, as the antenna 106 is connected to both the Tx circuitry 102 and the Rx circuitry 104 through the antenna terminal 116 that is common to both circuits. However, in wideband applications, the balun 114, the pair of capacitors 112, and the amplifier 110 can act as a load with respect to the Rx circuitry 104 in the port-combined configuration, introducing a residual impedance effect that degrades the LNA performance of the Rx circuitry 104.

[0028] Specifically, the amplifier 110 can present a capacitive load at the antenna terminal 116 shared with the input of the LNA (through the pair of capacitors 112 and the balun 114), which affects the input impedance of the LNA and reduces its effective bandwidth. Even when the switch 108 is open, parasitic capacitance from the Tx circuitry 102 can allow coupling or noise into the receive path, which can increase insertion loss and reduce the effective gain of the LNA. While the switch 108 can provide isolation between the Tx circuitry 102 and the Rx circuitry 104, at high frequencies in wide bandwidth applications, parasitic capacitance and limited switch isolation can allow residual coupling between the circuits. Furthermore, the impedance presented by the Tx circuitry 102 to the antenna terminal 116 can create reflection and mismatch effects, which reduce signal transfer from the antenna 106 to the LNA of the Rx circuitry 104. These effects can collectively contribute to increased noise figure, reduced signal amplification, and potential receiver desensitization in the receive path.

[0029] As further discussed herein, the loading effects of the Rx circuitry 104 on the Tx circuitry 102 can be minimized by adding a bulk resistance to the amplifier 110. For example, a resistor can be added between the bulk terminal of the transistor of the amplifier 110 and a reference voltage, such as ground or bulk ground. By adding the resistor, the bulk current from the transistor of the amplifier 110 can pass through the resistor before reaching the reference voltage. The added series resistance can reduce the loading effects of the capacitance from the transistor, as seen by the Rx circuitry 104, minimizing the loading effects and enhancing the operational bandwidth of the Rx circuitry 104.

[0030] Figure 2 A circuit 200 is shown that has an amplifier with a bulk resistance.

[0031] The circuit 200 shows features of the amplifier 110 of Figure 1 The circuit 200 includes a first transistor Ml and a second transistor M2 configured as a first pair of transistors. A third transistor M3 and a fourth transistor M4 are configured as a second pair of transistors. A fifth transistor M5 and a sixth transistor M6 are configured as a third pair of transistors and are coupled between the first pair of transistors and the second pair of transistors.

[0032] The circuit 200 has a first input terminal Vip (also referred to as a first differential input terminal) and a second input terminal Vim (also referred to as a second differential input terminal) in a pair of differential input terminals. In some embodiments, the first input terminal Vip and the second input terminal Vim are excited by a differential signal from a signal source. The circuit 200 also has a first output terminal Vop and a second output terminal Vom. In some embodiments, the first output terminal Vop is a non-inverting output of the amplifier 110, and the second output terminal Vom is an inverting output of the amplifier 110.

[0033] The first transistor Ml has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the first transistor Ml is an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) transistor, and the first current path terminal is a source terminal (indicated as "S" in Figure 2 ), the second current path terminal is a drain terminal (indicated as "D" in Figure 2 ), the control terminal is a gate terminal (indicated as "G" in Figure 2 ), and the body terminal is a bulk terminal (indicated as "B" in Figure 2 ). The second current path terminal of the first transistor is coupled to the first output terminal Vop.

[0034] The second transistor M2 has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the second transistor M2 is an n-type MOSFET transistor, and the first current path terminal is a source terminal, the second current path terminal is a drain terminal, the control terminal is a gate terminal, and the body terminal is a bulk terminal. The first current path terminal of the first transistor Ml is coupled to the second current path terminal of the second transistor M2. The control terminal of the second transistor M2 is coupled to the first input terminal Vip. The first current path terminal and the body terminal of the second transistor M2 are coupled to a reference voltage terminal AVss (such as a voltage or ground).

[0035] The third transistor M3 has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the third transistor M3 is an n-type MOSFET transistor, and the first current path terminal is a source terminal, the second current path terminal is a drain terminal, the control terminal is a gate terminal, and the body terminal is a bulk terminal. The control terminal of the third transistor M3 is coupled to the control terminal of the first transistor Ml. The second current path terminal of the third transistor M3 is coupled to the second output terminal Vom. The control terminals of the first transistor Ml and the third transistor M3 are connected to a voltage bias terminal Vbias. The voltage bias terminal Vbias can be configured to provide a bias voltage to the first transistor Ml and the third transistor M3 such that a differential signal at the first input terminal Vip and the second input terminal Vim coupled through the second transistor M2 and the fourth transistor M4, respectively, is amplified.

[0036] The fourth transistor M4 has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the fourth transistor M4 is an n-type MOSFET transistor, and the first current path terminal is a source terminal, the second current path terminal is a drain terminal, the control terminal is a gate terminal, and the body terminal is a bulk terminal. The second current path terminal of the fourth transistor M4 is coupled to the first current path terminal of the third transistor M3. The control terminal of the fourth transistor M4 is coupled to the second input terminal Vim. The first current path terminal and the body terminal of the fourth transistor M4 are coupled to a reference voltage AVss.

[0037] The first output terminal Vop is coupled to a first terminal of a primary winding 114a of the balun 114, and the second output terminal Vom is coupled to a second terminal of the primary winding 114a. A center tap of the primary winding 114a is coupled to a supply voltage VDD. The balun 114 has a secondary winding 114b that can couple signals from the first output terminal Vop and the second output terminal Vom to the antenna terminal 116.

[0038] The first transistor Ml and the second transistor M2 form a first transistor pair, where the second transistor M2 acts as a common-source input transistor that converts a differential signal at the first input terminal Vip into a current signal. The first transistor Ml acts as a common-gate transistor that passes this current to the first output terminal Vop while improving isolation and reducing the Miller effect. Similarly, the third transistor M3 and the fourth transistor M4 form a second transistor pair, where the fourth transistor M4 converts a differential signal at the second input terminal Vim into a current signal. The third transistor M3 acts as a common-gate transistor that passes this current to the second output terminal Vom. The first and second transistor pairs can enhance the output impedance, provide gain, and improve bandwidth. The differential signals at the first and second output terminals Vop and Vom are then coupled to the primary winding 114a of the balun 114 for signal conversion. Thus, the first and third transistors Ml and M3 form a cascode configuration that can improve the gain, bandwidth, and linearity of the amplifier 110 by increasing the output impedance, reducing unwanted feedback, and minimizing parasitic capacitance effects for wideband and high frequency applications.

[0039] The fifth transistor M5 has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the fifth transistor M5 is an n-type MOSFET transistor, and the first current path terminal is a source terminal, the second current path terminal is a drain terminal, the control terminal is a gate terminal, and the body terminal is a bulk terminal. The first and second current path terminals of the fifth transistor M5 are both coupled to the first current path terminal of the third transistor M3 and the second current path terminal of the fourth transistor M4. The control terminal of the fifth transistor M5 is coupled to the control terminal of the second transistor M2. The body terminal of the fifth transistor M5 is coupled to the reference voltage AVss.

[0040] The sixth transistor M6 has a first current path terminal, a second current path terminal, a body terminal, and a control terminal. In some embodiments, the sixth transistor M6 is an n-type MOSFET transistor, and the first current path terminal is a source terminal, the second current path terminal is a drain terminal, the control terminal is a gate terminal, and the body terminal is a bulk terminal. The first and second current path terminals of the sixth transistor M6 are both coupled to the first current path terminal of the first transistor Ml and the second current path terminal of the second transistor M2. The control terminal of the sixth transistor M6 is coupled to the control terminal of the fourth transistor M4. The body terminal of the sixth transistor M6 is coupled to the reference voltage AVss.

[0041] The fifth transistor M5 and the sixth transistor M6 form a third transistor pair and can be configured to cancel out unwanted capacitance from the second transistor M2 and the fourth transistor M4. The fifth transistor M5 and the sixth transistor M6 help maintain constant gain, linearity, and symmetry at the first output terminal Vop and the second output terminal Vom. The third transistor pair, combined with the first and second transistor pairs, enhances the common-mode rejection ratio (CMRR), minimizes distortion, and improves amplifier performance in wideband applications.

[0042] Circuit 200 further includes a first resistor 202 and a second resistor 204. The first resistor 202 has a first terminal and a second terminal. The first terminal of the first resistor 202 is coupled to the body terminal of the first transistor M1, and the second terminal of the first resistor 202 is coupled to a reference voltage AVss. The second resistor 204 has a first terminal and a second terminal. The first terminal of the second resistor 204 is coupled to the body terminal of the third transistor M3, and the second terminal of the second resistor 204 is coupled to the reference voltage AVss.

[0043] The first resistor 202 and the second resistor 204 connect the body terminals of the first transistor pair and the second transistor pair to the reference voltage AVss, and thus the current from the body terminals is coupled through the first resistor and the second resistor.

[0044] exist Figure 1 In the context of amplifier 110, the first resistor 202 and the second resistor 204 can advantageously help mitigate the off-state capacitive load effect (e.g., caused by the CDB (drain-body capacitance) and CDG (gate-drain capacitance) of the first transistor M1 and the third transistor M3. Figure 4 (As illustrated in the diagram). In the port-combined transceiver architecture, even when amplifier 110 is inactive, the transistor pair in the off state remains electrically coupled to the antenna terminal 116 shared between Tx circuit system 102 and Rx circuit system 104. This coupling presents a parasitic capacitive load that can affect the impedance of Rx circuit system 104. These parasitic capacitances can degrade LNA performance by increasing insertion loss, introducing impedance mismatch, narrowing bandwidth, and reducing gain, especially in high-frequency bands such as the 5 to 13 GHz range, such as the 5 to 7 GHz range.

[0045] The disconnected capacitive load from the CDB and CDG manifests as impedance seen at antenna terminal 116, making broadband impedance matching challenging. By introducing a first resistor 202 and a second resistor 204 into the reference voltage AVss in the body terminal coupling path of the first transistor M1 and the third transistor M3, the path of the high-frequency signal through the body terminal is modified, effectively increasing the series resistance and thereby reducing the Q factor of the CDB resonance (e.g., reducing or suppressing the Q factor of the CDB resonance). This additional resistance limits the flow of high-frequency current through the body terminal, which reduces the effective CDB and minimizes its loading effect at the shared node. Therefore, insertion loss is reduced, and the impedance presented to the LNA input is improved. In addition, the first resistor 202 and the second resistor 204 help mitigate the effects of the CDG by ensuring that the body terminal does not act as a low-impedance reference, maintaining high output impedance for the first and second transistor pairs, and enhancing broadband performance. As discussed further herein, this approach may be particularly beneficial in standard n-well processes (e.g., without deep n-wells or deep p-wells). Shallow isolation techniques achieve the aforementioned benefits without relying on isolation techniques used in deep n-well processes, which involve additional processing steps during manufacturing that could increase costs. Therefore, some embodiments can advantageously reduce costs and space requirements.

[0046] Figure 3 A top view 300 of an amplifier 110 device is shown, the amplifier having a resistor coupled between the body terminal of a transistor and a reference voltage.

[0047] Top view 300 illustrates how the layout can be arranged according to some embodiments. Figure 2 The transistors and resistors. In some embodiments, the transistors are arranged to be sufficiently isolated from each other, such that the resistors suppress the Q factor of the parasitic capacitances of the first transistor M1 and the third transistor M3.

[0048] A first resistor 202 is disposed between a first transistor M1 and a second transistor M2 in a first direction (shown as line D-D'). A second transistor M2 is disposed between the first resistor 202 and a fifth transistor M5 in the first direction. A second resistor 204 is disposed between a third transistor M3 and a fourth transistor M4 in the first direction. A fourth transistor M4 is disposed between the second resistor 204 and a sixth transistor M6 in the first direction. The first resistor 202, along with the first transistor M1, the second transistor M2, and the fifth transistor M5, are laterally offset from the second resistor 204, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 in a second direction perpendicular to the first direction (shown as line A-A'). The first transistor M1 and the second transistor M2 are each laterally offset by a first distance D1 from the third transistor M3 and the fourth transistor M4, respectively, in the second direction. In some embodiments, the fifth transistor M5 is laterally offset by a first distance D1 from the sixth transistor M6 in the second direction. A first distance D1 is determined such that the impedance between the first transistor M1 and the third transistor M3, or between the second transistor M2 and the fourth transistor M4, within the semiconductor substrate is greater than or equal to the impedance of the first resistor 202 or the second resistor 204. In some embodiments, the impedance of the first resistor 202 or the second resistor 204 is related to the width W1 of the first resistor 202 or the second resistor 204 in a first direction. The width W1 of the first resistor 202 and the second resistor 204 may be less than the first distance D1.

[0049] In some embodiments, the width W1 is approximately half the distance D1. In some embodiments, the width W1 is approximately 10 micrometers (μm) to 25 μm, or approximately 5 μm to 30 μm, greater than approximately 10 μm, or approximately 15 μm. Other values ​​may be used.

[0050] Therefore, the impedance (or resistance) value of one or more of the first resistor 202 or the second resistor 204 is based on the first distance D1. In some embodiments, the resistance of the first resistor 202 or the second resistor 204 is approximately 20 ohms to 40 ohms, approximately 10 ohms to 50 ohms, approximately 30 to 100 ohms, greater than 20 ohms, or approximately 30 ohms. Thus, crosstalk between transistors can be mitigated, and the voltage or current from the first transistor M1 and the third transistor M3 are coupled through the first resistor 202 and the second resistor 204 respectively (instead of through the semiconductor substrate and through crosstalk generated by adjacent transistors), thereby reducing the capacitive load of the amplifier, such as through... Figure 1 The LNA of the Rx circuit system 104 is visible.

[0051] Figure 4 Figure 400 illustrates a cross-sectional view of a semiconductor device having one or more transistors and associated resistors.

[0052] Cross-sectional view 400 is shown from Figure 3 The cross-sections at lines A-A' and B-B' are shown. At line A-A', the cross-sections of the first transistor M1 and the third transistor M3 are shown. At line B-B', the cross-sections of the first resistor 202 and the second resistor 204 are shown. The first transistor M1 is disposed in or above the semiconductor substrate 402. The first transistor M1 has a first current path terminal 416, a second current path terminal 418, a body terminal 420, and a well region 422 disposed within the semiconductor substrate 402. The first transistor M1 has a control terminal 424 disposed within a first dielectric layer 404 on the semiconductor substrate 402.

[0053] The first transistor M1 and the other transistors discussed herein are shown as n-type MOSFET transistors. For example, the semiconductor substrate 402 may be p-type with p-type body doping. The first current path terminal 416 may be an n-doped source terminal, the second current path terminal 418 may be an n-doped drain terminal, the body terminal 420 may be a p-doped body terminal, and the well region 422 may be p-doped. In some embodiments, the body terminal 420 has a higher doping concentration than the semiconductor substrate 402 and the well region 422. In some embodiments, the well region 422 may have a higher doping concentration than the semiconductor substrate 402. However, it should be understood that the transistors discussed herein may alternatively be p-type MOSFETs (not shown) or another transistor type. Furthermore, as previously discussed, the transistors shown in the cross-sections herein have a single well region (or shallow well) and do not have deep wells (such as deep n-wells much lower than p-wells). That is, in region 426 extending from the bottom region of well region 422 to the bottom surface of semiconductor substrate 402, region 426 includes light p-type doping or the same doping concentration as semiconductor substrate 402. Therefore, in some embodiments, the transistors discussed herein can be formed using low-cost processes, while isolation between transistors can be achieved by a first distance D1 between the first transistor pair and the second transistor pair. Compared to other techniques that include a deep n-well 440 in the substrate, Figure 4 The single-well region described herein does not have a deep n-well 440, which can save additional mask and / or doping operations (such as ion implantation), and thus can advantageously simplify the manufacturing process.

[0054] The third transistor M3 is disposed in or above the semiconductor substrate 402. The third transistor M3 has a first current path terminal 430, a second current path terminal 428, a body terminal 432, and a well region 434 disposed within the semiconductor substrate 402. The third transistor M3 also has a control terminal 436 disposed within the first dielectric layer 404. The parasitic capacitances of the first transistor M1 and the third transistor M3 are shown as CDG from the drain to the gate of the transistor, and CDB from the drain to the body of the transistor (as per [reference needed]).Figure 2 (As discussed).

[0055] First resistor 202 and second resistor 204 are disposed in a second dielectric layer 406 above first transistor M1 and third transistor M3. First transistor M1 is coupled to first resistor 202 via a first interconnect structure 408. First interconnect structure 408 may include wires or vias in one or more layers of the first dielectric layer 404. Body terminal 420 of first transistor M1 is coupled to a first terminal of first resistor 202 via first interconnect structure 408. Third transistor M3 is coupled to second resistor 204 via third interconnect structure 412. Third interconnect structure 412 may include wires or vias in one or more layers of the first dielectric layer 404. Body terminal 432 of third transistor M3 is coupled to a first terminal of second resistor 202 via third interconnect structure 412.

[0056] In some embodiments, the first resistor 202 and the second resistor 204 may be or comprise polysilicon, and may each be a polysilicon resistor. The first resistor 202 and the second resistor 204 may be defined by traces within a second dielectric layer 406. A second terminal of the first resistor 202 is coupled to a reference voltage terminal 438, and a second terminal of the second resistor 204 is coupled to a reference voltage terminal 438. In some embodiments, the first resistor 202 is coupled to the reference voltage terminal 438 via a second interconnect structure 410, and the second resistor 204 is coupled to the reference voltage terminal 438 via a fourth interconnect structure 414. The reference voltage terminal 438 may be a wire or trace disposed within a third dielectric layer 409 disposed on the second dielectric layer 406. In other embodiments, the second terminal of the first resistor is coupled to a first voltage reference terminal, and the second terminal of the second resistor is coupled to a second voltage reference terminal. In some embodiments, the first voltage reference terminal and the second voltage reference terminal may have the same potential (such as voltage or ground). The first resistor 202 and the second resistor 204 can mitigate the capacitive load effect of CDB and CDG in the off-state.

[0057] The first resistor 202 and the second resistor 204 are separated from each other by a first distance D1, and the first transistor M1 and the third transistor M3 are separated from each other by a first distance D1. In some embodiments, the body terminal 420 of the first transistor M1 and the body terminal 432 of the third transistor M3 are spaced apart from each other by a first distance D1 within the semiconductor substrate 402. In other embodiments, the well region 422 of the first transistor M1 and the well region 434 of the third transistor M3 are spaced apart from each other by a first distance D1. In some embodiments, the first distance D1 is approximately 30 μm. In other embodiments, the first distance D1 is approximately 10 μm to 60 μm, or 60 μm to 120 μm, or greater than 60 μm. Other values ​​may be used.

[0058] In some embodiments, the first distance D1 is based on the values ​​of the first resistor 202 and the second resistor 204, such that isolation is achieved between the first transistor M1 and the third transistor M3, and current is transferred from the body terminals 420, 432 and through the first resistor 202 and the second resistor 204 to the reference voltage terminal 438.

[0059] Figure 5 Figure 500 illustrates a cross-sectional view of a semiconductor device having one or more transistors.

[0060] Cross-sectional view 500 is shown from Figure 3 The cross-section at line C-C' is shown. At line C-C', the cross-sections of the second transistor M2 and the fourth transistor M4 are shown. The second transistor M2 is disposed in or above the semiconductor substrate 402. The second transistor M2 has a first current path terminal 512, a second current path terminal 514, a body terminal 516, and a well region 520 disposed within the semiconductor substrate 402. The second transistor M2 has a control terminal 518 disposed within a first dielectric layer 404 above the semiconductor substrate 402. The fourth transistor M4 is disposed in or above the semiconductor substrate 402. The fourth transistor M4 has a first current path terminal 522, a second current path terminal 524, a body terminal 526, and a well region 530 disposed within the semiconductor substrate 402. The fourth transistor M4 has a control terminal 528 disposed within the first dielectric layer 404 above the semiconductor substrate 402.

[0061] The fifth interconnect structure 502 and the sixth interconnect structure 506 couple the second transistor M2 to the reference voltage terminal 438. The first current path terminal 512 and the body terminal 516 of the second transistor M2 are coupled to the reference voltage terminal 438 via the fifth interconnect structure 502 and the sixth interconnect structure 506, respectively. The seventh interconnect structure 508 and the eighth interconnect structure 510 couple the fourth transistor M4 to the reference voltage terminal 438. The first current path terminal 522 and the body terminal 526 of the fourth transistor M4 are coupled to the reference voltage terminal 438 via the seventh interconnect structure 508 and the eighth interconnect structure 510, respectively.

[0062] In some embodiments, the body terminal 516 of the second transistor M2 and the body terminal 526 of the fourth transistor M4 are spaced apart from each other by a first distance D1 within the semiconductor substrate 402. In other embodiments, the well region 520 of the second transistor M2 and the well region 530 of the fourth transistor M4 are spaced apart from each other by a first distance D1. In some embodiments, the first distance D1 is configured to achieve isolation between the second transistor M2 and the fourth transistor M4.

[0063] Figure 6 Figure 600 illustrates a cross-sectional view of a semiconductor device having one or more transistors and associated resistors.

[0064] Cross-sectional view 600 is shown from Figure 3 A cut at line D-D'. At line D-D', a cross-section is shown passing through the body terminal 420 of the first transistor M1 and through the body terminal 516 of the second transistor M2. The body terminal 516 of the second transistor M2 is coupled to the reference voltage terminal 438 via the sixth interconnect structure 506. The body terminal 420 of the first transistor M1 is coupled to the first terminal of the first resistor 202 via the first interconnect structure 408. The first resistor 202 has a width W1. The second terminal of the first resistor 202 is coupled to the reference voltage terminal 438 via the second interconnect structure 410.

[0065] As discussed above regarding the first transistor M1, the semiconductor substrate 402 may have a doping concentration of a first doping type. The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may each have a well region possessing the first doping type. The doping concentration of the semiconductor substrate 402 extends from the bottom region of the well region to the bottom surface of the semiconductor substrate 402.

[0066] Figure 7 This describes System 700, which features impedance and bandwidth matching.

[0067] Figure 7 This is from U.S. Patent Application No. 18 / 462,083, filed on September 6, 2023, entitled "Bandwidth Tuning Using a Single-Input Multi-Output Low-Noise Amplifier". Figure 1 A reproduction of A, the application of which is incorporated herein by reference in its entirety. Figure 7 The system includes an antenna 701, an amplifier 707, a low-noise amplifier (LNA) subcircuit 715, and a broadband tuning subcircuit 730. The LNA subcircuit 715 further includes a shunt inductor 716, a capacitor 720, a bias 722, a gate inductor 717, a transistor 718, and a source inductor 719. The broadband tuning subcircuit 730 is fed an impedance matching signal from the LNA subcircuit 715 and provides an output 731 to downstream subcircuits based on the signals supplied to the components of the broadband tuning subcircuit 730.

[0068] Figure 7 Antenna 701 can correspond to Figure 1 Antenna 106. System 700 includes antenna 106 corresponding to... Figure 1The Tx circuit system 102 includes a Tx circuit system 740. The Tx circuit system 740 includes an amplifier 707, capacitors 708 and 709, and a balun 710 (also called a transformer). System 700 includes components corresponding to... Figure 1 The Rx circuit system 104 includes an Rx circuit system 742. The Rx circuit system 742 includes a receive chain LNA (such as an LNA sub-circuit 715 and associated components). System 700 includes a switch 714 between the Tx circuit system 740 and the Rx circuit system 742. Switch 714 corresponds to... Figure 1 The switch 108 provides port combination functionality to the system 700.

[0069] System 700 refers to a circuit capable of receiving a signal from antenna 701, amplifying the signal, matching the impedance of the signal, and outputting a signal with various wideband bandwidths. For example, system 700 may generate an output signal with a bandwidth between 5 and 7 GHz or an output signal with a bandwidth of [missing information].

[0070] System 700 includes antenna terminal 703 (such as a pin or port that may be an input / output pin or port of a semiconductor chip). System 700 has a first amplifier (such as an LNA including an LNA sub-circuit 715 and an associated Rx circuit system 742). A second amplifier has an input coupled to the antenna terminal.

[0071] Amplifier 707 may also be referred to as second amplifier 707. Second amplifier 707 has an output coupled to antenna terminal 703 via a balun 710 and a switch 714. Balun 710 has an output coupled to a first differential output terminal (such as input 706, or...). Figure 2 The first output terminal (Vop) or the second output terminal (Vom) of the balancing-to-unbalancing converter 710 has a first winding. The balancing-to-unbalancing converter 710 has a second winding coupled to the antenna terminal 703. The input of the first amplifier is coupled to the antenna terminal 703 and the second winding of the balancing-to-unbalancing converter 710. A switch 714 is coupled between the second winding of the balancing-to-unbalancing converter 710 and the input of the first amplifier. Therefore, the output of the second amplifier 707 is coupled to the input of the first amplifier through the balancing-to-unbalancing converter 710 and the switch 714.

[0072] Switch 714 is coupled between balun 710 and antenna terminal 703. When switch 714 is closed, Tx circuitry 740 is activated and transmits signals through antenna terminal 703 via antenna 701. Therefore, system 700 includes a transceiver having a transmission path including a second amplifier 707 and a reception path including a first amplifier. During the transceiver's transmission mode, switch 714 is configured to be closed, Tx circuitry 740 is activated, and Rx circuitry 742 is deactivated. During the transceiver's reception mode, switch 714 is configured to be open, Tx circuitry 740 is deactivated (e.g., the second amplifier is disabled), and Rx circuitry 742 is activated.

[0073] When switch 714 is in the open state, Tx circuit system 740 can be deactivated, and the first amplifier can be activated in receive mode. In receive mode, the signal received by antenna 701 is coupled to the second amplifier through antenna terminal 703.

[0074] The second amplifier may include, according to Figures 2 to 6 Various components. For example, the second amplifier 707 may include a first transistor pair (such as the first transistor M1 and the second transistor M2) having a first differential input terminal, a first differential output terminal, a first body terminal, and a second body terminal (see...). Figure 2 The first body terminal of the first transistor pair may be coupled to a reference voltage terminal (such as reference voltage terminal AVss). The second amplifier 707 may include a second transistor pair (such as a third transistor M3 and a fourth transistor M4) coupled in parallel with the first transistor pair, the second transistor pair having a second differential input terminal, a second differential output terminal, a first body terminal, and a second body terminal (see...). Figure 2 The first body terminal of the second transistor pair is coupled to a reference voltage terminal. The first differential output terminal and the second differential output terminal are coupled to the balun 710. In some embodiments, the first transistor pair and the second transistor pair are n-type transistors without a deep n-well.

[0075] The second amplifier 707 includes a first resistor (such as first resistor 202) having a first terminal coupled to a second body terminal of a first transistor pair and a second terminal coupled to a reference voltage terminal. The second amplifier 707 includes a second resistor (such as second resistor 204) having a first terminal coupled to a second body terminal of a second transistor pair and a second terminal coupled to a reference voltage terminal. In some embodiments, the first and second resistors are defined by polysilicon traces disposed in a dielectric layer over a semiconductor substrate. The second amplifier 707 includes a third transistor pair (such as...) coupled between the first and second transistor pairs.Figure 2 (The fifth transistor M5 and the sixth transistor M6). The third transistor pair is coupled to the first resistor and the second resistor through the first transistor pair and the second transistor pair.

[0076] The loading effect of the first transistor of Rx circuit system 742 on the second transistor of Tx circuit system 740 is minimized by a first resistor and a second resistor connected to the body terminals of the first transistor pair and the second transistor pair within the second amplifier 707. The first resistor and the second resistor (e.g., in combination with the layout techniques discussed herein) couple the body current from the transistors before it reaches the reference voltage terminal. The resistors advantageously help reduce the loading effect from the self-capacitance of the transistors, as can be seen in Rx circuit system 104, thereby enhancing the operating bandwidth of Rx circuit system 742.

[0077] It should be understood that, from Figure 7 The reference numerals with the prefix "7" correspond to U.S. Patent Application No. 18 / 462,083. Figure 1 A is a figure reference numeral with the prefix "1". Therefore, Figure 7 The components / devices / circuit elements / features are described according to their corresponding reference numerals in U.S. Patent Application No. 18 / 462,083. Specifically, Figure 7 700 corresponds to U.S. Patent Application No. 18 / 462,083. Figure 1 For A's 100, similarly: 701 corresponds to 101, 702 corresponds to 102, 703 corresponds to 103, 704 corresponds to 104, 705 corresponds to 105, 706 corresponds to 106, 707 corresponds to 107, 708 corresponds to 108, 709 corresponds to 109, 710 corresponds to 110, 711 corresponds to 111, 712 corresponds to 112, 713 corresponds to 113, 714 corresponds to 114, 715 corresponds to 115, 716 corresponds to 116, 717 corresponds to 117, 718 corresponds to 118, 719 corresponds to 119, 720 corresponds to 120, 721 corresponds to 121, 722 corresponds to 122, 723 corresponds to 123, 724 corresponds to 124, 725 corresponds to 125, 730 corresponds to 130 and 731 corresponds to 131.

[0078] Figure 8 Display from during the receiving operation mode, for example, according to Figures 2 to 6 Implementing 707 Figure 7 The graph shows the simulated reflection coefficient of the system 700. The reflection coefficient is displayed as a value in decibels (dB) |S11|. The reflection coefficient indicates the first amplifier (such as...) when the Tx circuit system is deactivated. Figure 7The degree to which the Rx circuit system 742 (LNA) matches the antenna 701 during receive mode (such as |S11|, viewed from the angle of the antenna 701 in the direction of the inductor 702). Figure 8 Multiple S11 curves 802 are shown, representing the reflection coefficient under different gain and tuning states of the LNA (such as the tuning state of the broadband tuner sub-circuit 730). As seen in the multiple S11 curves 802, during receive mode, from approximately 4.25 GHz to 7.25 GHz, the reflection coefficient of the second amplifier is approximately -10 dB. Therefore, the first and second resistors of system 700 effectively minimize the load effect of Tx circuit system 740 on Rx circuit system 742, thereby achieving broadband coverage suitable for next-generation Wi-Fi applications.

[0079] Examples of embodiments of this disclosure are summarized herein. Other embodiments can also be understood from the entire specification and technical solutions submitted herein.

[0080] Example 1. An integrated circuit comprising: a first transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the second current path terminal of the first transistor is coupled to a first differential output terminal of a pair of differential output terminals; a second transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the control terminal of the second transistor is coupled to a first differential input terminal of a pair of differential input terminals, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and the first current path terminal of the second transistor is coupled to a reference voltage terminal; and a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the body terminal of the first transistor, and the second terminal of the first resistor is coupled to the reference voltage terminal, and wherein the first resistor is disposed in a dielectric layer above the first transistor and the second transistor.

[0081] Example 2. The integrated circuit according to Example 1 further comprises: a third transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the second current path terminal of the third transistor is coupled to a second differential output terminal of a pair of differential output terminals; and wherein the body terminal of the third transistor is laterally offset from the body terminal of the first transistor within the semiconductor substrate by a first distance.

[0082] Example 3. The integrated circuit according to any one of Examples 1 or 2 further comprises: a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the body terminal of the third transistor, and the second terminal of the second resistor is coupled to a reference voltage terminal.

[0083] Example 4. An integrated circuit according to any one of Examples 1 to 3, wherein a second resistor is disposed in a dielectric layer, and wherein a first resistor is laterally offset from the second resistor by at least a first distance.

[0084] Example 5. An integrated circuit according to any one of Examples 1 to 4, wherein the impedance value of one or more of the first resistor or the second resistor is based on a first distance.

[0085] Example 6. An integrated circuit according to any one of Examples 1 to 5, wherein the impedance between the first transistor and the third transistor within the semiconductor substrate is greater than or equal to the impedance of one or more of the first resistor or the second resistor.

[0086] Example 7. An integrated circuit according to any one of Examples 1 to 6, further comprising: a fourth transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the control terminal of the fourth transistor is coupled to a second differential input terminal of a pair of differential input terminals, wherein the first current path terminal of the third transistor is coupled to the second current path terminal of the fourth transistor, and the first current path terminal of the fourth transistor is coupled to a reference voltage terminal.

[0087] Example 8. An integrated circuit according to any one of Examples 1 to 7, wherein the body terminal of the fourth transistor is laterally offset from the body terminal of the second transistor within the semiconductor substrate by at least a first distance.

[0088] Example 9. An integrated circuit according to any one of Examples 1 to 8, further comprising: a fifth transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the first current path terminal and the second current path terminal of the fifth transistor are coupled to the first current path terminal of a third transistor, wherein the body terminal of the fifth transistor is coupled to a reference voltage terminal, and wherein the control terminal of the fifth transistor is coupled to the control terminal of the second transistor.

[0089] Example 10. An integrated circuit according to any one of Examples 1 to 9, further comprising: a sixth transistor disposed in or above a semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the first current path terminal and the second current path terminal of the sixth transistor are coupled to the second current path terminal of the first transistor, wherein the body terminal of the sixth transistor is coupled to a reference voltage terminal, and wherein the control terminal of the sixth transistor is coupled to the control terminal of the fourth transistor.

[0090] Example 11. An integrated circuit according to any one of Examples 1 to 10, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein: the first current path terminal of the first transistor is a source terminal; the second current path terminal of the first transistor is a drain terminal; the control terminal of the first transistor is a gate terminal; the first current path terminal of the second transistor is a source terminal; the second current path terminal of the second transistor is a drain terminal; the control terminal of the second transistor is a gate terminal; the first current path terminal of the third transistor is a source terminal; the second current path terminal of the third transistor is a drain terminal; the control terminal of the third transistor is a gate terminal; the first current path terminal of the fourth transistor is a source terminal; the second current path terminal of the fourth transistor is a drain terminal; the control terminal of the fourth transistor is a gate terminal; the first current path terminal of the fifth transistor is a source terminal; the second current path terminal of the fifth transistor is a drain terminal; the control terminal of the fifth transistor is a gate terminal; the first current path terminal of the sixth transistor is a source terminal; the second current path terminal of the sixth transistor is a drain terminal; and the control terminal of the sixth transistor is a gate terminal.

[0091] Example 12. An integrated circuit according to any one of Examples 1 to 11, wherein, viewed from a top view, a first resistor is disposed between a first transistor and a second transistor.

[0092] Example 13. An integrated circuit according to any one of Examples 1 to 12, wherein the body terminal of the first transistor is coupled to the first terminal of the first resistor via a first interconnect structure.

[0093] Example 14. An integrated circuit according to any one of Examples 1 to 13, wherein the second terminal of the first resistor is coupled to a reference voltage terminal via a second interconnect structure.

[0094] Example 15. An integrated circuit according to any one of Examples 1 to 14, further comprising: a transformer having a first winding and a second winding, the first winding being coupled to a first differential output terminal, wherein a center tap of the first winding is coupled to a supply voltage; an antenna terminal being coupled to the second winding of the transformer; and an amplifier having an input coupled to the antenna terminal and the second winding of the transformer.

[0095] Example 16. An integrated circuit according to any one of Examples 1 to 15, wherein the amplifier is a low-noise amplifier (LNA).

[0096] Example 17. The integrated circuit according to any one of Examples 1 to 16 further includes a switch coupled between a second winding of a transformer and the input of an amplifier.

[0097] Example 18. An integrated circuit according to any one of Examples 1 to 17, wherein the first resistor is a polysilicon resistor.

[0098] Example 19. An amplifier comprising: a first output terminal and a second output terminal; a first input terminal and a second input terminal; a semiconductor substrate; a first transistor disposed in or above the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the second current path terminal of the first transistor is coupled to the first output terminal; a second transistor disposed in or above the semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and wherein the control terminal of the second transistor is coupled to the first input terminal; a first resistor disposed in a dielectric layer above the semiconductor substrate, the first resistor having a first terminal and a second terminal, the first terminal being coupled to the body terminal of the first transistor, wherein, viewed from a top view, the first resistor is disposed in a first direction in the first transistor. Between the body transistor and the second transistor; a third transistor disposed in or above a semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the first transistor; a fourth transistor disposed in or above a semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the second current path terminal of the fourth transistor is coupled to the first current path terminal of the third transistor; and a second resistor disposed in a dielectric layer and having a first terminal and a second terminal, the first terminal being coupled to the body terminal of the third transistor, wherein, from a top view, the first resistor is disposed between the third transistor and the fourth transistor in a first direction, and wherein, from a top view and in a second direction perpendicular to the first direction, the first transistor and the second transistor are respectively laterally offset from the third transistor and the fourth transistor by a first distance.

[0099] Example 20. The amplifier according to Example 19, wherein in a first direction, the widths of the first resistor and the second resistor are less than a first distance.

[0100] Example 21. The amplifier according to any one of Examples 19 or 20, wherein the second terminal of the first resistor is coupled to a reference voltage terminal, and the second terminal of the second resistor is coupled to a reference voltage terminal.

[0101] Example 22. The amplifier according to any one of Examples 19 to 21, wherein the second terminal of the first resistor is coupled to the first reference voltage terminal, and the second terminal of the second resistor is coupled to the second reference voltage terminal.

[0102] Example 23. An amplifier according to one of Examples 19 to 22, wherein the first resistor and the second resistor are each polysilicon resistors defined by traces within a dielectric layer.

[0103] Example 24. An amplifier according to any one of Examples 19 to 23, further comprising: a first interconnect structure wherein the body terminal of a first transistor is coupled to a first terminal of a first resistor via the first interconnect structure; a second interconnect structure that couples a second terminal of the first resistor to a reference voltage terminal; a third interconnect structure wherein the body terminal of a third transistor is coupled to a first terminal of a second resistor via the third interconnect structure; and a fourth interconnect structure that couples a second terminal of the second resistor to the reference voltage terminal.

[0104] Example 25. The amplifier according to any one of Examples 19 to 24, further comprising: a fifth interconnect structure and a sixth interconnect structure, wherein the first current path terminal and the body terminal of the second transistor are coupled to a reference voltage terminal via the fifth interconnect structure and the sixth interconnect structure, respectively; and a seventh interconnect structure and an eighth interconnect structure, wherein the first current path terminal and the body terminal of the fourth transistor are coupled to the reference voltage terminal via the seventh interconnect structure and the eighth interconnect structure, respectively.

[0105] Example 26. The amplifier according to any one of Examples 19 to 25, wherein the impedance between the first transistor and the third transistor or between the second transistor and the fourth transistor in the semiconductor substrate is greater than the impedance of the first resistor or the second resistor.

[0106] Example 27. An amplifier according to any one of Examples 19 to 26, further comprising: a fifth transistor disposed in or above a semiconductor substrate and having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the first current path terminal and the second current path terminal of the fifth transistor are coupled to a first current path terminal of a third transistor and a second current path terminal of a fourth transistor, and wherein the control terminal of the fifth transistor is coupled to the control terminal of the second transistor; and a sixth transistor disposed in or above a semiconductor substrate, the sixth transistor having a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the first current path terminal and the second current path terminal of the sixth transistor are coupled to the first current path terminal of the first transistor and the second current path terminal of the second transistor, and wherein the control terminal of the sixth transistor is coupled to the control terminal of the fourth transistor, wherein, viewed from a top view, in a first direction, the second transistor is disposed between a first resistor and the fifth transistor, and the fourth transistor is disposed between a second resistor and the sixth transistor, and in a second direction, the fifth transistor is laterally offset from the sixth transistor by a first distance.

[0107] Example 28. An amplifier according to any one of Examples 19 to 27, wherein the semiconductor substrate has a doping concentration of a first doping type, and the first transistor, the second transistor, the third transistor and the fourth transistor each have a well region having the first doping type, and wherein the doping concentration of the semiconductor substrate extends from the bottom region of the well region to the bottom surface of the semiconductor substrate.

[0108] Example 29. A circuit comprising: an antenna terminal; a first amplifier having an input coupled to the antenna terminal; a balun; a switch coupled between the balun and the antenna terminal; and a second amplifier having an output coupled to the antenna terminal via the balun and the switch, wherein the output of the second amplifier is coupled to the input of the first amplifier via the balun and the switch, the second amplifier comprising: a first transistor pair having a first differential input terminal, a first differential output terminal, a first body terminal, and a second body terminal, wherein the first body terminal of the first transistor pair is coupled to a reference voltage terminal; a second transistor pair coupled to the first transistor pair, the second transistor pair having a second differential input terminal, a second differential output terminal, a first body terminal, and a second body terminal, wherein the first body terminal of the second transistor pair is coupled to the reference voltage terminal; a first resistor having a first terminal coupled to the second body terminal of the first transistor pair and a second terminal coupled to the reference voltage terminal; and a second resistor having a first terminal coupled to the second body terminal of the second transistor pair and a second terminal coupled to the reference voltage terminal, wherein the first differential output terminal and the second differential output terminal are coupled to the balun.

[0109] Example 30. The circuit according to Example 29 further includes a transceiver having a transmission path including a second amplifier and a reception path including a first amplifier, wherein: during the transmission mode of the transceiver, the switch is configured to be closed; and during the reception mode of the transceiver, the switch is configured to be open.

[0110] Example 31. The circuit according to any one of Examples 29 or 30, wherein during the receive mode, from 4.25 GHz to 7.25 GHz, the reflection coefficient of the second amplifier is approximately -10 dB.

[0111] Example 32. The circuit according to any one of Examples 29 to 31, wherein the second amplifier is deactivated during the receive mode.

[0112] Example 33. The circuit according to any one of Examples 29 to 32 further includes a third transistor pair coupled between the first transistor pair and the second transistor pair, wherein the third transistor pair is coupled to the first resistor and the second resistor through the first transistor pair and the second transistor pair.

[0113] Example 34. The circuit according to any one of Examples 29 to 33, wherein the first transistor pair and the second transistor pair comprise n-type transistors that do not have a deep n-well.

[0114] Example 35. The circuit according to any one of Examples 29 to 34, wherein the first resistor and the second resistor are defined by polysilicon traces disposed in a dielectric layer disposed above a semiconductor substrate, wherein the first transistor pair and the second transistor pair are disposed in or above the semiconductor substrate.

[0115] The above description of the illustrative examples, embodiments, aspects, etc., of this invention (including the content described in the abstract) is not exhaustive or intended to limit the described aspects to the precise forms described. Although specific examples, embodiments, aspects, etc., have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications considered to be within the scope of such examples, embodiments, aspects, etc., are possible.

[0116] The circuits or devices described herein as containing certain components may alternatively be adapted to couple to those components used to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may alternatively contain semiconductor elements (such as semiconductor dies and / or integrated circuit (IC) packages) within only a single physical device, and may be adapted to couple to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacturing by an end user and / or a third party.

[0117] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" can be understood as one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0118] Unless otherwise stated, "about," "approximately," or "generally" preceding a value indicates + / - 10% of that value, or, if the value is zero, a reasonable range of values ​​near zero. Within the scope of the technical solution, modifications are possible in the described examples, and other implementations are also possible.

Claims

1. An integrated circuit, comprising: A first transistor is disposed in or above a semiconductor substrate and has a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the second current path terminal of the first transistor is coupled to a first differential output terminal of a pair of differential output terminals. A second transistor is disposed in or above the semiconductor substrate and has a control terminal, a first current path terminal, a second current path terminal and a body terminal, wherein the control terminal of the second transistor is coupled to a first differential input terminal of a pair of differential input terminals, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and the first current path terminal of the second transistor is coupled to a reference voltage terminal. and A first resistor has a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the body terminal of the first transistor, and the second terminal of the first resistor is coupled to the reference voltage terminal, and wherein the first resistor is disposed in a dielectric layer above the first transistor and the second transistor.

2. The integrated circuit according to claim 1, further comprising: A third transistor is disposed in or above the semiconductor substrate and has a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the second current path terminal of the third transistor is coupled to a second differential output terminal of the pair of differential output terminals; and wherein the body terminal of the third transistor is laterally offset from the body terminal of the first transistor within the semiconductor substrate by a first distance.

3. The integrated circuit according to claim 2, further comprising: A second resistor has a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the body terminal of the third transistor, and the second terminal of the second resistor is coupled to the reference voltage terminal.

4. The integrated circuit of claim 3, wherein the second resistor is disposed in the dielectric layer, and wherein the first resistor is laterally offset from the second resistor by at least the first distance.

5. The integrated circuit of claim 4, wherein the impedance value of one or more of the first resistor or the second resistor is based on the first distance.

6. The integrated circuit of claim 4, wherein the impedance between the first transistor and the third transistor within the semiconductor substrate is greater than or equal to the impedance of one or more of the first resistor or the second resistor.

7. The integrated circuit according to claim 3, further comprising: A fourth transistor is disposed in or above the semiconductor substrate and has a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the control terminal of the fourth transistor is coupled to the second differential input terminal of the pair of differential input terminals, wherein the first current path terminal of the third transistor is coupled to the second current path terminal of the fourth transistor, and the first current path terminal of the fourth transistor is coupled to the reference voltage terminal.

8. The integrated circuit of claim 7, wherein the body terminal of the fourth transistor is laterally offset from the body terminal of the second transistor within the semiconductor substrate by at least the first distance.

9. The integrated circuit according to claim 7, further comprising: A fifth transistor disposed in or above the semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the first current path terminal and the second current path terminal of the fifth transistor are coupled to the first current path terminal of the third transistor, wherein the body terminal of the fifth transistor is coupled to the reference voltage terminal, and wherein the control terminal of the fifth transistor is coupled to the control terminal of the second transistor.

10. The integrated circuit of claim 9, further comprising: A sixth transistor disposed in or above the semiconductor substrate and having a control terminal, a first current path terminal, a second current path terminal, and a body terminal, wherein the first current path terminal and the second current path terminal of the sixth transistor are coupled to the second current path terminal of the first transistor, wherein the body terminal of the sixth transistor is coupled to the reference voltage terminal, and wherein the control terminal of the sixth transistor is coupled to the control terminal of the fourth transistor.

11. The integrated circuit of claim 10, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein: The first current path terminal of the first transistor is the source terminal; The second current path terminal of the first transistor is the drain terminal; The control terminal of the first transistor is a gate terminal; The first current path terminal of the second transistor is the source terminal; The second current path terminal of the second transistor is the drain terminal; The control terminal of the second transistor is the gate terminal; The first current path terminal of the third transistor is the source terminal; The second current path terminal of the third transistor is a drain terminal; The control terminal of the third transistor is a gate terminal; The first current path terminal of the fourth transistor is the source terminal; The second current path terminal of the fourth transistor is a drain terminal; The control terminal of the fourth transistor is a gate terminal; The first current path terminal of the fifth transistor is the source terminal; The second current path terminal of the fifth transistor is a drain terminal; The control terminal of the fifth transistor is a gate terminal; The first current path terminal of the sixth transistor is the source terminal; The second current path terminal of the sixth transistor is a drain terminal; and The control terminal of the sixth transistor is the gate terminal.

12. The integrated circuit of claim 1, wherein, viewed from a top view, the first resistor is disposed between the first transistor and the second transistor.

13. The integrated circuit of claim 1, wherein the body terminal of the first transistor is coupled to the first terminal of the first resistor via a first interconnect structure.

14. The integrated circuit of claim 13, wherein the second terminal of the first resistor is coupled to the reference voltage terminal via a second interconnect structure.

15. The integrated circuit of claim 1, further comprising: A transformer having a first winding and a second winding, the first winding being coupled to a first differential output terminal, wherein the center tap of the first winding is coupled to a supply voltage; Antenna terminal, which is coupled to the second winding of the transformer; and An amplifier having an input coupled to the antenna terminal and the second winding of the transformer.

16. The integrated circuit of claim 15, wherein the amplifier is a low-noise amplifier (LNA).

17. The integrated circuit of claim 15, further comprising a switch coupled between the second winding of the transformer and the input of the amplifier.

18. The integrated circuit of claim 1, wherein the first resistor is a polysilicon resistor.

19. An amplifier comprising: First output terminal and second output terminal; First input terminal and second input terminal; Semiconductor substrate; A first transistor is disposed in or above the semiconductor substrate and has a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the second current path terminal of the first transistor is coupled to the first output terminal. A second transistor is disposed in or above the semiconductor substrate and has a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the first current path terminal of the first transistor is coupled to the second current path terminal of the second transistor, and wherein the control terminal of the second transistor is coupled to the first input terminal. A first resistor is disposed in a dielectric layer above the semiconductor substrate. The first resistor has a first terminal and a second terminal. The first terminal is coupled to the body terminal of the first transistor. In a top view, the first resistor is disposed between the first transistor and the second transistor in a first direction. A third transistor is disposed in or above the semiconductor substrate and has a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the first transistor. A fourth transistor is disposed in or above the semiconductor substrate and has a first current path terminal and a second current path terminal, a body terminal and a control terminal, wherein the second current path terminal of the fourth transistor is coupled to the first current path terminal of the third transistor. and A second resistor is disposed in the dielectric layer and has a first terminal and a second terminal, the first terminal being coupled to the body terminal of the third transistor, wherein, viewed from the top view, the first resistor is disposed between the third transistor and the fourth transistor in the first direction, and wherein, viewed from the top view and in a second direction perpendicular to the first direction, the first transistor and the second transistor are each laterally offset from the third transistor and the fourth transistor by a first distance, respectively.

20. A circuit comprising: Antenna terminals; A first amplifier having an input coupled to the antenna terminal; Balanced-to-unbalanced converter; A switch, coupled between the balun and the antenna terminal; and A second amplifier having an output coupled to the antenna terminal via the balun and the switch, wherein the output of the second amplifier is coupled to the input of the first amplifier via the balun and the switch, the second amplifier comprising: A first transistor pair has a first differential input terminal, a first differential output terminal, a first body terminal, and a second body terminal, wherein the first body terminal of the first transistor pair is coupled to a reference voltage terminal; A second transistor pair coupled to the first transistor pair, the second transistor pair having a second differential input terminal, a second differential output terminal, a first body terminal and a second body terminal, wherein the first body terminal of the second transistor pair is coupled to the reference voltage terminal; A first resistor having a first terminal coupled to the second body terminal of the first transistor pair and a second terminal coupled to the reference voltage terminal; and The second resistor has a first terminal coupled to the second body terminal of the second transistor pair and a second terminal coupled to the reference voltage terminal, wherein the first differential output terminal and the second differential output terminal are coupled to the balun.

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