Signal converter from IEEE1149.10 to IEEE1500

Abstract

The invention provides an IEEE (Institute of Electrical and Electronic Engineers) 1149.10 to IEEE 1500 (Institute of Electrical and Electronic Engineers) signal The method specifically comprises the steps that a CONFIG packet, a TARGET packet, a CH-SELECT packet and an SCAN packet based on the IEEE Std 1149.10-2017 standard are received, after equipment configuration, target selection and channel locking are sequentially completed, the SCAN packet is decoded according to the IEEE 1149.10 rule, an IEEE1500 driving signal is generated by combining the mapping relation between a scanning channel and IEEE1500 registers (WIR, WBR and WBY), and communication control over the IEEE1500 interface chip equipment is achieved. Wherein the IEEE1500 driving signal covers a Wrapper clock signal (WRCK), a Wrapper serial input signal (WSI), an instruction / data selection signal (SelectWIR), a shift control signal (ShiftWR) and an update control signal (Update WR), and the IEEE1500 driving signal comprises a Wrapper clock signal (WRCK), a Wrapper serial input signal (WSI), an instruction / data selection signal (SelectWIR), a shift control signal (ShiftWR) and an update control signal (Update WR). According to the method, IEEE 1149.10 data packet interaction and time sequence constraints are followed, after test data are coded to generate a compliance packet, an IEEE1500 driving signal with an accurate time sequence can be generated through conversion, the data analysis and test requirements of a high-speed test port are met, and an efficient solution is provided for embedded core test of a system-on-chip (SoC).

Description

Technical Field

[0001] This invention relates to the field of chip testing, and in particular to an IEEE1149.10 to IEEE1500 signal converter, which is suitable for testing compatibility scenarios of embedded cores in system-on-a-chip (SoC), solves the signal adaptation problem between different testing standards, and realizes efficient docking between high-speed testing equipment and IEEE1500 architecture chips. Background Technology

[0002] The IEEE 1500 standard (Embedded Core Testing Standard, IEEE Std 1500-2022) is a core standard developed by IEEE specifically for embedded core testing. It aims to address three core issues in SoCs: independent testing of multiple heterogeneous embedded cores, core reuse compatibility, and inter-core interconnect verification. It plays an irreplaceable role in integrated circuit mass production testing, fault diagnosis, and R&D debugging. Existing mid-to-high-end SoCs are required to support the IEEE 1500 protocol. Its core components include the core test shell, Test Access Mechanism (TAM), Test Shell Instruction Register (WIR), and Test Shell Data Register (WDR). The WDR includes the Test Shell Boundary Register (WBR) and the Test Shell Bypass Register (WBY). Furthermore, mid-to-high-end SoCs require the use of a core test language (CTL, corresponding to IEEE Std 1450.6) to facilitate test information exchange between core designers and integrators.

[0003] The core test shell (Wrapper) is the core unit of the IEEE 1500 test architecture. Its core function is to isolate the embedded core from the SoC's external circuitry, ensuring that testing only affects the target core and does not interfere with other cores or system logic. The Wrapper's drive and control rely on dedicated Wrapper Serial Port (WSP) signals. The Wrapper Serial Port (WSP) signals are the core drive signals of the IEEE 1500 test architecture. According to the IEEE 1500-2022 standard, the WSP has eight drive signals: Wrapper Clock (WRCK), Wrapper Reset (WRSTN), Instruction / Data Select (SelectWIR), Shift Control (ShiftWR), Capture Control (CaptureWR), Update Control (UpdateWR), Wrapper Serial Input (WSI), and Wrapper Serial Output (WSO). These eight signals are mandatory in the IEEE 1500 standard. In addition, there are two optional signals: Wrapper Serial Output Rising Edge (WSOR) and Auxiliary Clock (AUXCK).

[0004] Among these WSP drive signals, WRCK provides a dedicated synchronization clock for the operation of the Wrapper, and all operations of the Wrapper are driven by this clock signal. The SelectWIR signal is used to control the selection of registers. When the level is high (1), WIR is selected, and when the level is low (0), WDR is selected. The SelectWIR signal works in conjunction with the WRCK clock edge. WSI is the interface for data and instruction input. All data or instructions to be input into a specific register are input serially bit by bit through the WSI interface. WSO is the interface for data output. All data to be output from a specific register is output serially bit by bit through the WSO interface. WRSTN can be used to reset the Wrapper and its associated registers. The Wrapper can also be reset by combining the sequence of SelectWIR and ShiftWR. ShiftWR, CaptureWR, and UpdateWR control the serial shifting of test data / instructions, kernel status capture, and register value latching, respectively. They must be strictly synchronized with the WRCK clock edge (ShiftWR and CaptureWR are effective on the rising edge of WRCK, and UpdateWR is effective on the falling edge of WRCK). WSOR is an optional serial output rising edge update port, which outputs the same data as WSO but updates on the rising edge of WRCK; AUXCK is an optional auxiliary clock used to adapt to the core-specific clock domain and can be shared with the system clock.

[0005] The core control logic of IEEE 1500 is implemented around the "Wrapper". Its state and operation design is entirely designed for "embedded core testing" scenarios and strictly follows the hardware rules and timing constraints of IEEE Std 1500™-2022. According to this standard, the Wrapper defines only two core states. State switching and test operations are achieved through standardized signal combinations and clock synchronization: WrapperDisabled (disabled state) is triggered by WRSTN=0 (active low), which is the initial state of the Wrapper. In this state, the Wrapper only responds to the WRSTN and WRCK signals, forcing Activating the WS_BYPASS instruction (bypass instruction) clears the Wrapper instruction register (WIR) and ensures it only maintains the functional signal path between the core and the system-on-a-chip (SoC), without interfering with the normal operation of the core. This state only applies to a single Wrapper. WrapperEnabled is triggered by WRSTN=1 (high level). In this state, the Wrapper can respond to the control signals (SelectWIR, ShiftWR, CaptureWR, UpdateWR) of the Wrapper serial port (WSP), supporting test-related operations. The WIR (W... Operations on the Wrapper instruction register require synchronization via the rising edge of SelectWIR=1+ShiftWR=1+WRCK. Kernel test instructions (such as "activate kernel scan chain" or "start internal kernel fault detection") are serially loaded into the WIR via WSI (Wrapper Serial Input). After loading, the WIR is updated via the falling edge of SelectWIR=1+UpdateWR=1+WRCK, latching the instructions as currently valid. This controls the Wrapper to enter the corresponding test mode (such as inward test IF or outward test OF). Furthermore, WIR instructions only apply to the currently active Wrapper. The core is connected; the WDR (Wrapper Data Register, including Wrapper Boundary Register WBR and Wrapper Bypass Register WBY) operation needs to determine the target WDR type based on the updated WIR instruction, and is synchronized by SelectWIR=0+ShiftWR=1+WRCK rising edge, and inputs test data (such as scan chain excitation data) to the WDR via WSI, or outputs core test results (such as fault codes) via WSO (Wrapper Serial Output). Among them, WBR can capture core output data through the CaptureWR signal, while WBY has no capture and update operation, and only provides the shortest serial bypass path;In terms of multi-Wrapper collaboration, the SoC-level controller can synchronously control the state switching and test operations of multiple wrappers through global WSP signals (such as unified WRSTN and WRCK) to achieve multi-core parallel testing. All wrapper operations must meet the constraint of "concurrency of Capture, Shift, and Update events". Test time and test efficiency are core indicators for SoC mass production and R&D debugging. IEEE Std1500™-2022 is optimized for embedded core testing scenarios. By standardizing the wrapper architecture (such as supporting the parallel test access mechanism WPP and scan chain segmented SIB) and clarifying the WIR / WDR operation timing, it solves the interoperability and reusability issues of core-level testing, forming a complete link of "SoC-level control - core-level testing". The IEEE 1149.10 standard (Supplemental Standard for Boundary Scan Testing) provides an efficient alternative: it employs a simplified hardware design of "differential receiver + differential transmitter," requiring only four differential pins, a system clock, and a power supply to achieve the same test data bandwidth as traditional test architectures. More importantly, through "virtual scan channel" technology, it allows for flexible balancing of scan rate, the number of concurrent active scan channels, and required test bandwidth during the test design phase, significantly improving multi-channel parallel testing capabilities, especially suitable for the high-throughput requirements of high-speed ATEs. This aligns perfectly with the "parallel TAM (Test Access Mechanism)" requirement of IEEE 1500 for multi-core SoC scenarios, but the signal architecture and protocol logic of the two are completely independent.

[0006] In the aforementioned IEEE 1149.10 test data transmission mechanism, all test data is packaged and encapsulated based on the IEEE 1149.10 protocol. However, when testing SoC chips supporting the IEEE 1500 architecture, it is necessary to first verify the functionality of the embedded core's test module using an IEEE 1500 wrapper before generating IEEE 1500-specific drive signals and sending them to the wrapper's serial port (WSP). Therefore, this process inevitably involves decoding IEEE 1149.10 data packets and converting the decoded information into IEEE 1500 drive signals—this is precisely the core adaptation problem that the "IEEE 1149.10 to IEEE 1500 signal converter" of this invention needs to solve. Summary of the Invention

[0007] This invention provides an IEEE 1149.10 to IEEE 1500 signal converter to solve the technical problem of quickly and accurately generating IEEE 1500 drive signals in IEEE 1500 testing when the test data conforms to IEEE Std 1149.10™-2017.

[0008] To address the aforementioned technical problems, this invention provides an IEEE 1149.10 to IEEE 1500 signal converter, the method comprising:

[0009] Receive test data packets (including CONFIG, TARGET, CH-SELECT, and SCAN packets) encoded according to the IEEE 1149.10 standard, and parse them according to packet type to obtain the corresponding information:

[0010] Parse the CONFIG packet to obtain the 16-bit TARGET_ID (value greater than 0), complete the IEEE1149.10 device configuration of the target chip, generate and return the CONFIG response packet (carrying the configured TARGET_ID and CRC32 check field).

[0011] Parse the TARGET packet to obtain the ARGET_ID of the target chip, lock the target device of the current interaction, and generate and return the TARGETR response packet;

[0012] Parse the CH-SELECT packet to obtain the SCAN_GROUP (16 bits) and Channel-Select word (16 bits / word), determine the scan channel mapped to the IEEE1500 registers (WIR, WBR, WBY), generate and return the CH-SELECTR response packet;

[0013] Parse the SCAN packet to obtain the 32-bit Cycle-Count (scan clock count) and the interleaved test data in the Payload (split by INTERLEAVE_SIZE), and synchronously receive clock information; before parsing all data packets, the SOP to CRC32 fields (excluding control characters) must be checked using CRC32 (following the IEEE802.3 standard). If the check fails, return ERROR_CHAR (including 3 bytes of padding).

[0014] Based on the clock information, the scan channel mapping relationship parsed from the CH-SELECT packet, and the test data parsed from the SCAN packet, the corresponding IEEE1500 drive signal is generated:

[0015] Based on the scanning channel mapping relationship, the IEEE1500 register corresponding to the SCAN packet test data is determined, and the number of WRCK clock cycles for test data transmission is determined by combining Cycle-Count.

[0016] Preferably, the received, packaged test data must undergo the "configuration-selection-channel locking" process specified in the IEEE 1149.10 standard before parsing:

[0017] Based on the target chip test requirements, determine the required TARGET_ID, scan-channel, and Cycle-Count, and encode them according to the IEEE 1149.10 standard to generate CONFIG, TARGET, CH-SELECT, and SCAN packets respectively.

[0018] The clock information is set by the test controller according to the IEEE1500 test requirements of the target chip and must match the transmission timing of the IEEE1149.10 data packets.

[0019] Preferably, the IEEE1500 drive signals include a Wrapper clock signal WRCK, a Wrapper serial input signal WSI, a command / data select signal SelectWIR, a shift control signal ShiftWR, a capture control signal CaptureWR, and an update control signal UpdateWR.

[0020] The WRCK signal is generated based on the clock information: the base clock is divided to ensure that the timing of WRCK and control signals such as SelectWIR and ShiftWR meets the IEEE1500 requirements, and the WRCK signal is provided to the Wrapper interface of the target chip.

[0021] If the scan channel is mapped to WIR: Based on the Cycle-Count of the SCAN packet (which is equal to the length of the WIR command), the combination of SelectWIR=1+ShiftWR=1 is synchronously output on the rising edge of WRCK to transmit the test data in the SCAN packet payload as a WSI signal to the WIR; after the transmission is completed, the combination of SelectWIR=1+UpdateWR=1 is output on the falling edge of WRCK to trigger the WIR command update;

[0022] If the scan channel is mapped to WBR: Based on the Cycle-Count of the SCAN packet (which is equal to the WDR data length), a signal combination of SelectWIR=0+ShiftWR=1 is synchronously output on the rising edge of WRCK to transmit the test data in the SCAN packet payload as a WSI signal to WBR; if WBR contains update storage elements, a signal combination of SelectWIR=0+UpdateWR=1 is output on the falling edge of WRCK to trigger WBR data update;

[0023] After the test data transmission and update are completed, the signal combination SelectWIR=0, ShiftWR=0, and UpdateWR=0 is output to keep the IEEE1500Wrapper in its current register configuration.

[0024] The beneficial effects of this invention include:

[0025] The IEEE 1149.10 to IEEE 1500 signal converter provided by this invention only requires generating CONFIG, TARGET, CH-SELECT, and SCAN packets according to the IEEE 1500 test content of the target chip, encoded in accordance with the IEEE Std 1149.10™-2017 standard, and sending them to the converter. The converter follows the IEEE 1149.10 data packet interaction process to complete parsing and verification, and generates drive signals that conform to the IEEE 1500 timing based on the scan channel mapping relationship and Cycle-Count. The clock information is set as needed by the test controller to ensure the timing consistency with the IEEE 1149.10 data packet transmission and the IEEE 1500 test operation, thereby improving the reliability of test data transmission and equipment compatibility. Attached Figure Description

[0026] Figure 1 Block diagram of standard test housing as specified in IEEE 1149.1 standard

[0027] Figure 2 A schematic flowchart illustrating an implementation method for an IEEE 1149.10 to IEEE 1500 signal converter provided in this embodiment of the invention; Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0029] Please refer to Figure 2 The diagram shown is a flowchart of an IEEE 1500 signal converter provided in an embodiment of the present invention. Figure 2 As shown, the IEEE 1500 signal converter provided in this embodiment of the invention includes:

[0030] Step 1: Receive the SCAN packet and decode it to obtain WIR command information and WDR data information;

[0031] Step 2: Parse the WIR instruction information and WDR data information to obtain the WIR instruction length, WIR instruction content, WDR data length, and WDR data content;

[0032] Step 3: Generate the IEEE 1500 signal based on the WIR instruction length, WIR instruction content, WDR data length, WDR data content, and the clock information provided by the system.

[0033] In this embodiment of the invention, the SCAN packet format is the format provided in the IEEE 1149.10 standard, which is: Start character (SOP) + Command character (CMD) + Identifier (ID) + Instruction Shift Capture Update (ICSU) + Data Payload Frames (#Payload-Frames) + Scan Clock Count (Cycle-Count) + Data (PAYLOAD) + Checksum character (CRC32) + End character (EOP).

[0034] Table 1 shows the exemplary SCAN package configuration provided in this embodiment. The following is an explanation of each part of the data.

[0035] The start character SOP indicates the beginning of a data packet. The content of the command character CMD, being 0x06, indicates that this is a SCAN packet, containing WIR command information and WDR data. The ID indicates the order of this data packet; 0x01 indicates the first SCAN packet received, and the response packet will also have the same ID value. The Instruction, Capture, Shift, and Update (ICSU) is composed of the first letters of Instruction, Capture, Shift, and Update, consisting of 4 bits. A 1 in the corresponding bit indicates that the corresponding operation is valid. A 1 in the high-order bits of ICSU indicates that this is a command packet, and the content of PAYLOAD contains WIR command information; otherwise, it indicates that this is a data packet. The LOAD section contains WDR test data. For example, 0b0110 indicates a data packet, and a capture-shift operation is performed. The data payload frame #Payload-Frames indicates the number of PAYLOAD data frames following it, with each frame consisting of 32 bits. #Payload-Frames of 0x01000000 indicates one PAYLOAD data frame. The scan clock Cycle-Count indicates the number of WRCK clock cycles required for the data. PAYLOAD is used to carry interleaved data that needs to be transmitted. The checksum character CRC32 indicates the hexadecimal data calculated according to the CRC32 checksum principle for the non-control characters excluding the start character. The end character EOP indicates the termination of a data packet.

[0036] Table 1

[0037] SCAN format content SOP 8'hfb CMD 8'h06 ID 4'h01 ICSU 4'b0110 #Payload_Frames 32'h01000000 Cycle-Count 32'hb0000000 PAYLOAD 32'h12600000 CRC32 32'h04d7009 EOP 32'hfdfdfdfd

[0038] Based on the above configuration description, the ICSU information is parsed to determine whether the SCAN packet is a command packet or a data packet, #Payload-Frames is parsed to confirm the PAYLOAD size, Cycle-Count is parsed to confirm the number of WRCK clock cycles required to perform the shift operation in the PAYLOAD, one WRCK clock cycle moves one bit, and the PAYLOAD is parsed to obtain the WIR command information or WDR data information.

[0039] The IEEE1500 drive signals mentioned in this embodiment of the invention include: WRCK signal, SelectWIR signal, ShiftWR signal, UpdateWR signal and WSI signal, which are respectively provided to the WRCK interface, SelectWIR interface, ShiftWR interface, UpdateWR interface and WSI interface of the target chip Wrapper module.

[0040] The generation of the five IEEE 1500 drive signals mentioned above will be explained below.

[0041] In this embodiment of the invention, the WRCK signal is divided on the base clock by the clock circuit module according to the WIR command information and WDR data information, and provided to the WRCK interface in the Wrapper module.

[0042] In this embodiment of the invention, the SelectWIR and ShiftWR signals are determined and provided by parsing ICSU information and Cycle-Count information. Specifically, parsing the ICSU information determines whether the PAYLOAD information carried by the data packet is WIR command information or WDR data information, thereby configuring SelectWIR and ShiftWR to enter the corresponding state; parsing the Cycle-Count information determines the duration of the data in the shift state.

[0043] In this embodiment of the invention, the WSI signal is determined and provided by parsing PAYLOAD information. Specifically, PAYLOAD is parsed to obtain WIR command information and WDR data information, which are provided to the WSI interface through a Wrapper state machine in a serial shift input manner.

[0044] The following is an exemplary description with reference to the embodiments provided in Table 1.

[0045] Assuming the main control system clock is 300MHz and the test circuit requires a 50MHz clock, the clock circuit module will divide the system clock by 6 and provide the divided clock to the WRCK interface of the Wrapper module. Driven by the WRCK clock, the SelectWIR and ShiftWR signals first output several clock cycles of 1 to ensure the Wrapper state machine enters the "WrapperReset" reset state to wait for data reception. Upon receiving an ICSU, the SCAN packet is confirmed to be a data packet. The information in the PAYLOAD is parsed, and the parsed data is provided as a WSI signal to the WSI interface of the Wrapper module. SelectWIR=0 and ShiftWR=1 are output, causing the Wrapper state machine to enter the "Shift-WDR" state. The Cycle-Count is then parsed to confirm the data length is 11 (converted from hexadecimal B to decimal), requiring 11 shifts. Since one shift operation has already been performed, the "Shift-WDR" state needs to be maintained for 10 cycles, outputting SelectWIR=0 and ShiftWR=1 for 10 WRCK cycles. After the WDR data is sent, the UpdateWR=1 is output to enter the "Update-WDR" state, updating the data in the tested structure. Then, SelectWIR=0, ShiftWR=0, and UpdateWR=0 are output to make the Wrapper state machine enter the "WrapperIdle" state to wait for the next data processing.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. An IEEE 1149.10 to IEEE 1500 signal converter, characterized in that, The method includes the following steps: receiving a data packet encoded based on the IEEE 1149.10 standard, and parsing out WIR command information, capture control information, shift control information, update control information, WDR data information (including WBR and WBY information) and clock information; wherein, based on the WIR command information, WDR data information, and clock information, a corresponding IEEE 1500 drive signal is generated.

2. The method as described in claim 1, characterized in that, Before receiving the data packet encoded based on the IEEE 1149.10 standard and parsing it to obtain WIR command information, WDR data information, and clock information, the process also includes: determining the SCAN packet based on the test requirements of the embedded core in the target chip under test.

3. The method as described in claim 1, characterized in that, The IEEE 1500 drive signal includes the Wrapper clock signal WRCK; The step of generating the corresponding IEEE1500 drive signal based on clock information, WIR command information, and WDR data information includes: generating a WRCK signal based on the clock information; wherein, the base clock is divided according to the clock division value carried in the clock information to obtain the WRCK signal, and the WRCK signal is provided to the Wrapper interface of the target chip.

4. The method as described in claim 2, characterized in that, The SCAN packet contains WIR command information or WDR data information, as well as capture, shift, and update control information.

5. The method as described in claim 4, characterized in that... The WIR instruction information is parsed to obtain the WIR instruction length and WIR instruction content, and the WDR data information is parsed to obtain the WDR data length and WDR data content; the parsed WIR instruction length, WIR instruction content, WDR data length, and WDR data content are temporarily stored.

6. The method as described in claim 5, characterized in that, The IEEE1500 drive signals also include the Wrapper serial input signal WSI and the Wrapper clock signal WRCK; Generating the corresponding IEEE1500 drive signal based on the clock information, WIR command information, and WDR data information includes: determining the number of WRCK clock cycles required for the Wrapper to perform a WIR shift operation based on the WIR command length; in the Wrapper enabled state (WRSTN=1), when SelectWIR=1, ShiftWR=1, and WRCK is a valid rising edge, providing the WIR command content as a WSI signal to the target chip's Wrapper interface in sync with the WRCK clock cycle until the shift operation corresponding to the WIR command length is completed; determining the Wrapper's corresponding IEEE1500 drive signal based on the WDR data length. The number of WRCK clock cycles required for the WDR shift operation, when Wrapper is enabled (WRSTN=1), and SelectWIR=0, ShiftWR=1, and WRCK is a valid rising edge, the WDR data content is synchronously provided as a WSI signal to the Wrapper interface of the target chip according to the WRCK clock cycle until the shift operation corresponding to the WDR data length is completed; wherein, WDR includes Wrapper Boundary Register (WBR) and Wrapper Bypass Register (WBY), and the selection of WDR is determined by the instruction that has been updated to Wrapper Instruction Register (WIR).

7. The method as described in claim 5, characterized in that, The IEEE1500 signals also include a command / data selection signal SelectWIR, a shift control signal ShiftWR, a capture control signal CaptureWR, and an update control signal UpdateWR. Based on the clock information, WIR command information, and WDR data information, the operation timing in the Wrapper enabled state is determined, and the control signals required to implement the operation timing are determined. The control signals are then provided to the target chip's Wrapper interface as SelectWIR, ShiftWR, CaptureWR, and UpdateWR signals.

8. The method as described in claim 7, characterized in that, Based on the clock information, WIR instruction information, and WDR data information, the operation timing in the Wrapper enabled state is determined, and the control signals required to implement the operation timing are determined. The control signals are provided to the Wrapper interface of the target chip as SelectWIR, ShiftWR, CaptureWR, and UpdateWR signals. This includes: based on the WIR instruction information, under WRCK clock synchronization, first outputting a signal combination of SelectWIR=1 and ShiftWR=1, and continuing this signal combination for the number of WRCK clock cycles corresponding to the WIR instruction length to complete the WIR shift operation; then outputting a signal combination of SelectWIR=1 and UpdateWR=1, and triggering a WIR update operation on the falling edge of WRCK to update the shifted WIR instruction content to the currently valid instruction; finally outputting a signal combination of SelectWIR=0, ShiftWR=0, and UpdateWR=0 to maintain the configuration corresponding to the currently valid instruction in the Wrapper. Based on the WDR data information (the target WDR type needs to be determined based on the updated WIR instructions), under WRCK clock synchronization, first output the signal combination SelectWIR=0 and ShiftWR=1, and continue this signal combination for the number of WRCK clock cycles corresponding to the WDR data length to complete the WDR shift operation; if the target WDR is a WBR and there is an updated storage element, then output the signal combination SelectWIR=0 and UpdateWR=1, and trigger the WBR update operation on the falling edge of WRCK; finally output the signal combination SelectWIR=0, ShiftWR=0, and UpdateWR=0 to keep the Wrapper in its current WDR configuration; WBY does not need to perform an update operation.

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