Reconfigurable ferroelectric transistor of CAA structure based on two-dimensional single-layer tungsten selenide and aluminum-scandium-nitrogen

Abstract

The invention discloses a reconfigurable ferroelectric transistor based on two-dimensional single-layer tungsten selenide and aluminum-scandium-nitrogen. The transistor adopts a CAA structure, programming pulse voltage is applied to a gate electrode, the polarization direction of a ferroelectric layer is changed, and a polarization electric field is coupled to a channel region; under the action of pulse programming voltage, the AlScN ferroelectric layer is subjected to polarization flipping, bound charges are induced to be generated on a channel interface, and the carrier type in a channel is changed; according to the polarization direction of the ferroelectric layer, electrons or holes are injected through the source electrode, and the channel layer adopts single-layer tungsten selenide as a channel material. According to the invention, a good nonvolatile characteristic can be maintained at an advanced process node, only a low programming voltage is needed, the power consumption is obviously reduced, the vertical integration level of the device is improved, the leakage current and the parasitic effect are obviously inhibited, and the device can be better compatible with internal programmable interconnection line resources and I / O blocks in the existing programmable logic device.

Description

Technical Field

[0001] This invention relates to the field of ferroelectric transistor technology, and specifically to a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure. Background Technology

[0002] Currently, the implementation methods of programmable logic blocks mainly fall into two categories: one uses a large number of non-programmable n-FET or p-FET transistors, and the other relies on the use of programmable transistors. Schemes using non-programmable transistors typically employ lookup tables, multiplexers, or large-scale transistor arrays to achieve logic reconfiguration. Among these, the large-scale array method achieves functional programming by controlling the switching states of transistors and their interconnection topology within the array, but often requires a large circuit area and relies on complex scheduling strategies. For example, the static circuit-based reconfigurable combinational logic unit in patent publication number CN111294040A uses 12 non-programmable n-FET and p-FET transistors to form pull-up and pull-down networks respectively. Different logic functions are achieved by controlling the switching state of each transistor. While this scheme is relatively intuitive and simple, it uses a large number of transistors, resulting in high area overhead and a lack of flexibility. In addition, the widely used FPGA is also a typical programmable device that uses a large number of non-programmable transistors to implement programmable logic. However, because FPGAs generally use SRAM as the storage unit, their logic states are volatile, requiring reloading and reprogramming configuration after power failure, which incurs additional power consumption.

[0003] The emergence of ferroelectric materials and programmable ferroelectric transistors (FFETs) offers a new solution to the aforementioned challenges. Ferroelectric materials possess polarization nonvolatility and can induce polarization electric fields in different directions depending on the polarity of the programming voltage. When combined with bipolar channel materials such as two-dimensional tungsten selenide (WSe2), the resulting ferroelectric transistors can simulate N-type field-effect transistors (n-FETs) and P-type field-effect transistors (p-FETs) under different programming conditions, thus achieving both nonvolatility and reconfigurable logic functions.

[0004] In existing ferroelectric transistors, such as the reconfigurable logic gate based on the FeFET+RRAM structure and its fabrication and usage method described in patent publication CN116456726A, the reconfigurable circuit topology is composed of a memristor as a pull-up resistor and a ferroelectric transistor as a pull-down network. Although this programmable device has the advantages of compact structure and compatibility with existing CMOS processes, it also has obvious limitations: First, the unipolarity of the transistor may cause both transistors to turn on or off simultaneously under different programming conditions, affecting the logic output differentiation and thus restricting the feasibility of building reconfigurable logic. Second, the planar transistor structure has weak leakage current suppression capability, making it difficult to apply to advanced small-size nodes and also limiting the integration density of the transistor. In addition, the hafnium oxide ferroelectric material used in this transistor has low remanent polarization intensity and weak threshold voltage modulation capability. Changing the circuit logic requires adjusting the resistance value of the memristor, which introduces additional power consumption and increases design complexity. One of the logic inputs of the transistor is the programming gate voltage, and the gate pulse needs to be maintained for up to 500ms during each programming, which severely limits the programming efficiency of the circuit.

[0005] For example, in a reconfigurable logic unit based on a ferroelectric reconfigurable transistor design, as disclosed in patent publication CN119584636A, the bipolar ferroelectric transistor requires the injection of corresponding charge carriers from the source electrode when switching channel polarity. However, WSe2 itself has a low charge carrier concentration, so the WSe2 channel not modulated by the gate exhibits poor conductivity, which greatly affects the source-drain movement process of charge carriers. There is still a part of the WSe2 channel region not covered by the gate between the PG gate and the Gate, which may hinder the movement of the corresponding charge carriers, thus challenging the feasibility of polarity switching through programming. In addition, the multi-layer stacked structure in the gate of the GAA structure may introduce additional parasitic capacitance and increase the contact resistance between the gate and the channel. Furthermore, the fully enclosed channel structure may exacerbate local heat accumulation and reduce the reliability of the device. Moreover, the presence of the PG gate further increases the complexity of the transistor, increases the difficulty of transistor fabrication, and introduces additional power consumption.

[0006] In summary, the existing related technologies have the following shortcomings: First, non-programmable devices often lead to increased logic block area overhead; second, the reliability of the devices is limited, usually only supporting a certain number of programming operations, or introducing additional parasitic capacitance and increased contact resistance at the process level; furthermore, some devices still have certain limitations in terms of fabrication difficulty, process compatibility, or basic principles. Summary of the Invention

[0007] To overcome the shortcomings and deficiencies of existing technologies, this invention provides a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitride (CAA) structure. The transistor uses a bipolar two-dimensional WSe2 as the channel layer and selects an ultrathin AlScN layer with high remanent polarization and a stable coercive field even under scaling as the ferroelectric material layer. This allows for good non-volatility while requiring only a low programming voltage. Combined with the bipolar two-dimensional WSe2 as the channel layer, non-volatile programming is achieved while significantly reducing power consumption. Furthermore, it employs a CAA process with better integration and process compatibility, and is based on a sub-5nm process. The process node features high integration and excellent CMOS process compatibility, ensuring that the WSe2 channel can be effectively modulated by the gate, further improving the vertical integration of the device, and significantly suppressing leakage current and parasitic effects. This transistor is well compatible with the internal programmable interconnect resources and I / O blocks in existing programmable logic devices, thus facilitating the rapid deployment of new programmable logic devices in actual production. The positive and negative programming voltages required by this transistor can be symmetrical in amplitude and both are below 3V. The inverters and other basic logic units formed by this transistor all exhibit good input-output characteristics at a power supply voltage of 0.5V.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] This invention provides a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitride (AlScN) CAA structure. The transistor adopts a CAA structure, specifically including: a gate electrode, an aluminum scandium nitride (AlScN) ferroelectric layer, a monolayer tungsten selenide (MLWSe2) channel layer, a source electrode, and a drain electrode.

[0010] The gate electrode adopts a T-shaped structure;

[0011] An aluminum scandium nitride (AlScN) ferroelectric layer is arranged in a ring around the vertical section of the gate electrode T-shaped structure and extends to the bend. The inner surface of the AlScN ferroelectric layer is in contact with the gate electrode, and part of the AlScN ferroelectric layer is exposed to air at the bend.

[0012] A monolayer tungsten selenide (ML WSe2) channel layer surrounds the outer surface of the aluminum scandium nitride (AlScN) ferroelectric layer, and the monolayer tungsten selenide (ML WSe2) channel layer is partially exposed to air at the bend.

[0013] The source and drain are respectively annularly surrounding the upper and lower halves of the vertical section of the monolayer tungsten selenide ML WSe2 channel layer. The source and drain are arranged along the extension direction of the vertical section, and there is a gap between the source and drain.

[0014] A programming pulse voltage is applied to the gate electrode to change the polarization direction of the ferroelectric layer and couple the polarization electric field to the channel region.

[0015] Under the action of pulse programming voltage, the polarization of the AlScN ferroelectric layer is reversed, which induces the generation of bound charges at the channel interface, reduces the Schottky barrier of the other polarity carriers, and thus changes the type of carriers in the channel.

[0016] The conductivity polarity can be switched by injecting electrons or holes into the source electrode.

[0017] As a preferred technical solution, the source and drain electrodes are made of titanium, indium, palladium, gold, platinum or graphite as electrode materials.

[0018] As a preferred technical solution, the gate electrode uses platinum, gold, molybdenum, titanium, aluminum or nickel as the electrode material.

[0019] As a preferred technical solution, when gate programming pulses of different sizes and polarities are applied to the gate electrode, the reconfigurable ferroelectric transistor can be configured as an n-type field-effect transistor or a p-type field-effect transistor with different threshold voltages.

[0020] As a preferred technical solution, the thickness of the aluminum scandium nitride (AlScN) ferroelectric layer decreases as the transistor size decreases, while the characteristics of coercive electric field, residual polarization intensity, and saturation polarization intensity remain stable.

[0021] The present invention also provides a method for fabricating a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure, comprising the following steps:

[0022] Source, drain, and silicon dioxide transition layer were prepared by two magnetron sputtering processes and one plasma-enhanced chemical vapor deposition process.

[0023] The channel and gate via are obtained by photolithography etching;

[0024] The channel layer is deposited by generating a tungsten selenide layer through organometallic chemical vapor deposition;

[0025] An aluminum scandium nitrogen (AlScN) film is deposited using a deposition process to fill the entire gate via. A uniform AlScN ferroelectric layer with sidewall thickness and a gate metal via are obtained by photolithography and inductively coupled plasma etching.

[0026] Deposit the gate electrode, and remove excess gate electrode material through chemical mechanical polishing to complete the planarization of the top of the transistor;

[0027] Excess tungsten selenide, scandium nitride, and gate electrode material are removed by photolithography.

[0028] Transistor fabrication is achieved by removing the silicon dioxide transition layer through wet etching.

[0029] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0030] The transistor of this invention uses a bipolar two-dimensional WSe2 as the channel layer and selects an ultrathin AlScN ferroelectric material layer that has a stable coercive electric field even with scaling (large remanent polarization intensity is used to better modulate the threshold voltage) and large remanent polarization intensity. This allows for good non-volatile characteristics while requiring only a low programming voltage. Combined with the bipolar two-dimensional WSe2 as the channel layer, it significantly reduces power consumption while achieving non-volatile programming. Furthermore, it employs the CAA process, which offers better integration and process compatibility, and is based on a sub-5nm process node, possessing high integration and excellent performance. The CMOS process compatibility not only ensures that the WSe2 channel can be effectively modulated by the gate, but also further improves the vertical integration of the device and significantly suppresses leakage current and parasitic effects. The transistor is well compatible with the internal programmable interconnect resources and I / O blocks in programmable logic devices, which is conducive to the rapid deployment of new programmable logic devices in actual production. The positive and negative programming voltages required by the transistor can be assigned symmetrically and are all below 3V. The inverters and other basic logic units formed by the transistor all exhibit good input and output characteristics at a power supply voltage of 0.5V. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall structure of the reconfigurable ferroelectric transistor based on the CAA structure of two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen of the present invention.

[0032] Figure 2 This is a cross-sectional view of the reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure of the present invention.

[0033] Figure 3 (a) is a schematic diagram of the principle of the reconfigurable ferroelectric transistor of the present invention simulating an n-type field-effect transistor after the application of a gate programming pulse;

[0034] Figure 3 (b) is a schematic diagram of the principle of the reconfigurable ferroelectric transistor of the present invention simulating a p-type field-effect transistor after the application of a gate programming pulse;

[0035] Figure 4 This is a schematic diagram of the transfer characteristic curves of the same transistor of the present invention after n / p type programming;

[0036] Figure 5 This is a schematic flowchart illustrating the fabrication method of the reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure according to the present invention.

[0037] Figure 6(a)-(g) are schematic diagrams of the key process steps in the fabrication method of the reconfigurable ferroelectric transistor based on the CAA structure of two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen in this invention.

[0038] Figure 7 (a)-(c) in the figure represent the circuit topology, truth table, and input / output curve diagram of the non-logic unit (inverter) of this invention.

[0039] Figure 8 (a)-(c) in the figure are schematic diagrams of the circuit topology, truth table and input / output curves of the AND / OR NOT logic unit of the present invention;

[0040] Figure 9 (a)-(c) in the figure represent the circuit topology, truth table, and input / output curve diagram of the XOR / XNOR logic unit of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] Example 1

[0043] like Figure 1 , Figure 2 As shown, this embodiment provides a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitride (CAA) structure. The transistor adopts a CAA structure, specifically including: a gate electrode, an aluminum scandium nitride (AlScN) ferroelectric layer, a monolayer tungsten selenide (MLWSe2) channel layer, a source electrode, and a drain electrode.

[0044] The gate electrode adopts a T-shaped structure;

[0045] An aluminum scandium nitride (AlScN) ferroelectric layer is arranged in a ring around the vertical section of the gate electrode T-shaped structure and extends to the bend. The inner surface of the AlScN ferroelectric layer is in contact with the gate electrode, and part of the AlScN ferroelectric layer is exposed to air at the bend.

[0046] A monolayer tungsten selenide (ML WSe2) channel layer surrounds the outer surface of the aluminum scandium nitride (AlScN) ferroelectric layer, and the monolayer tungsten selenide (ML WSe2) channel layer is partially exposed to air at the bend.

[0047] The source and drain are respectively annularly surrounding the upper and lower halves of the vertical section of the monolayer tungsten selenide ML WSe2 channel layer. The source and drain are arranged along the extension direction of the vertical section, and there is a gap between the source and drain.

[0048] Specifically, a molybdenum (Mo) gate electrode is used to apply a programmed pulse voltage, thereby changing the polarization direction of the ferroelectric layer and coupling the polarization electric field to the channel region.

[0049] The aluminum scandium nitride (AlScN) ferroelectric layer, with a ring-shaped surrounding structure about 2 nanometers thick, can undergo polarization reversal under a sufficiently large pulse programming voltage, thereby inducing bound charges at the channel interface, changing the type of charge carriers in the channel, and realizing the tunable non-volatile polarity of the ferroelectric transistor.

[0050] The channel layer is made of a two-dimensional monolayer tungsten selenide (ML WSe2) with a thickness of about 0.7 nanometers. This two-dimensional material has bipolar conductivity and can switch the conductivity polarity by injecting electrons or holes through the source electrode.

[0051] The source and drain metal electrodes, made of palladium (Pd), are located on the outermost side and are used to inject charge carriers. The work function of the selected source and drain electrode metals is close to the central energy level of the tungsten selenide WSe2 bandgap, which can make the contact barrier height of electrons and holes similar when forming metal-semiconductor contacts.

[0052] In this embodiment, the source / drain electrode metals, gate electrode metals, and the AlScN ferroelectric layer material used in the ferroelectric transistor all have a certain range of selectable compositions, exhibiting good material compatibility. The source / drain electrode metals can be made of materials such as titanium, indium, palladium, gold, platinum, and graphite (as previously added). Different choices directly affect the height of the contact barrier / well between electrons and holes, thereby modulating the injection efficiency of channel carriers and affecting the conductivity of the programmed n-type and p-type transistors. The gate electrode metal can include platinum, gold, molybdenum, titanium, aluminum, and nickel (as previously added). Differences in their work functions significantly affect the required positive and negative programming pulse voltage values ​​for the transistor (different initial threshold voltages). To facilitate the construction of digital gate-level circuits, this embodiment preferentially uses palladium, with its suitable work function, as the source / drain electrode material. This ensures that the two types of transistors obtained after programming have similar conduction currents in the circuit, which is beneficial for constructing an inverter. Molybdenum is chosen as the gate electrode metal to ensure that the voltage amplitudes for positive and negative pulse programming of the initial transistor are similar. The material composition of the AlScN ferroelectric layer affects key parameters such as its saturation polarization and remanent polarization, which in turn affect the amplitude and duration of the programming voltage. This embodiment preferably uses AlScN ferroelectric layers with excellent saturation polarization, remanent polarization, and coercive electric field. 0.68 Sc 0.32 N.

[0053] Taking a positive programming pulse as an example, when a positive voltage pulse of appropriate amplitude is applied to the gate, the ferroelectric domains in the AlScN thin film undergo polarization reversal, causing the polarization direction in the ferroelectric layer to change from pointing towards the gate to pointing towards the channel region. This change in polarization state forms a non-volatile, gate-oriented, built-in polarization electric field at the AlScN-WSe2 interface. This electric field further lowers the channel bandgap, thereby reducing the Schottky barrier for electrons. Given the bipolar characteristics of the selected WSe2 material, its source can typically inject a certain number of charge carriers into the channel through the Schottky barrier tunneling mechanism. This promotes further electron injection into the tungsten selenide WSe2 channel, thereby forming an N-type conductive channel with high electron density, achieving conduction between the source and drain. Figure 3 As shown in (a) and (b), the electrical characteristics in this state exhibit similar behavior to those of an n-FET, and it can be considered as an approximation of an n-FET transistor. Similarly, for a p-FET, the polarized built-in electric field generated by the negative voltage pulse lowers the Schottky barrier of holes, injecting a large number of holes into the source and forming a high-hole-density P-type channel.

[0054] In this embodiment, the transistor uses a single layer of tungsten selenide (WSe2) with bipolar characteristics as the channel layer and employs a channel-around-annular (CAA) structure and process. After applying gate programming pulses of different sizes and polarities, its electrical characteristics can be configured to simulate the behavior of an n-type or p-type field-effect transistor. When applied to logic blocks in programmable logic devices, this design typically offers greater design flexibility compared to non-programmable transistors and helps improve transistor reuse, thereby potentially reducing the total number of transistors required in the logic unit. This has a positive effect on reducing chip area and power consumption.

[0055] In this embodiment, the ferroelectric layer material of the transistor is Al. 0.68 Sc 0.32 N, compared to existing ferroelectric materials such as hafnium-based ferroelectric materials, exhibits higher remanent polarization intensity, stronger ability to modulate threshold voltage, and helps improve data retention characteristics. Programmable logic devices built based on these characteristics can maintain their programmed state after losing external power supply without the need for additional reinitialization. Meanwhile, Al... 0.68 Sc 0.32 The thickness of N can be reduced as the transistor size shrinks while maintaining stable polarization properties. According to the range provided in the IRDS prediction, it can better continue Moore's Law. Specifically, the characteristics of coercive electric field, remanent polarization intensity and saturation polarization intensity remain stable.

[0056] In this embodiment, the transistor uses a bipolar monolayer WSe2 as the channel material, which can switch the type of carrier injected from the source and drain electrodes under different gate voltage modulations, thereby changing the channel polarity. This effectively avoids the problem in traditional transistors where silicon channels need to be precisely re-doped to adjust the channel polarity. At the same time, ultrathin silicon often suffers severe hole mobility degradation due to scattering, while two-dimensional monolayer WSe2 with a similar thickness can significantly reduce the scattering probability and surface defect density through unique van der Waals bonds, maintaining a high carrier mobility. This makes it more suitable as a channel material for small-size programmable ferroelectric transistors.

[0057] In this embodiment, when the transistor is programmed, two pulse voltages with the same amplitude but opposite polarity can be used to achieve n-FET and p-FET configurations. Since the positive and negative programming voltage amplitudes are consistent, the logic blocks in the programmable logic device built based on this programming method only require a single reference voltage source to meet the programming power requirements. During operation, the connection relationship between the transistor gate, source, and voltage source or power ground can be quickly switched through internal programmable interconnects and other resources, thereby achieving the switching of different polarity programming voltages. Simultaneously, the selectable programming voltage of this transistor is typically below 3V, while its operating voltage is 0.5V, resulting in relatively low requirements for the external power supply. Furthermore, the operating voltage is very small compared to the programming voltage, causing minimal interference with the programming effect. Therefore, it shows certain application potential in the construction of low-power programmable logic devices. Figure 4 As shown, the transfer characteristic curve of the transistor is obtained. The curve shows the transfer characteristics measured under the condition of source-drain voltage of 0.25V after being programmed by positive and negative pulses respectively.

[0058] In this embodiment, the transistor employs CAA technology, which typically exhibits lower gate leakage current characteristics compared to existing planar FET and FinFET technologies, thereby helping to reduce static power consumption. Simultaneously, the transistor itself has a subthreshold swing of approximately 100mV / dec, a characteristic that helps reduce short-circuit current that may be generated during switching of logic units (such as inverters), thus reducing dynamic power consumption. The transistor achieves a drain-induced barrier reduction (DIBL) effect of less than 80mV / V across multiple small-size process nodes and under different programming conditions, demonstrating excellent insensitivity to source-drain voltage.

[0059] In this embodiment, the transistor is fabricated using a sub-5nm CAA process, exhibiting excellent three-dimensional integration potential and suitable for building high-density integrated circuits. Compared to existing planar FET, FinFET, and GAA processes, the CAA structure demonstrates better adaptability in vertical stacking, possessing the potential to maintain high current density while miniaturizing transistor size. In dual-transistor-based dynamic random access memory (DRAM) structures, dual-transistor cells can now be implemented using vertical stacking interconnects, integrating a dual-transistor cell within the area of ​​a single transistor. Therefore, this transistor offers advantages in integration density compared to transistors implemented using other processes, contributing to a significant reduction in the area of ​​the fabricated programmable logic circuits.

[0060] In this embodiment, the CAA structure used in the transistor is more conducive to realizing the function of a programmable bipolar transistor. Without a gate voltage applied, the carrier concentration of the bipolar WSe2 material is low, and its conduction characteristics are relatively limited. Therefore, during transistor turn-on, the WSe2 channel between the source and drain electrodes needs to be modulated through the gate, including applying a programming pulse and setting the programmed gate operating voltage, thereby forming a channel with a higher carrier concentration in WSe2 to achieve effective conduction between the source and drain electrodes. In existing GAA structures, a sidewall is usually provided between the gate and the source and drain electrodes to achieve electrical isolation. The portion of the WSe2 channel area covered by this sidewall is less affected by the gate electric field during gate modulation, making it difficult to effectively form a conductive channel. This easily leads to limited connectivity between the source and drain electrodes and a smaller channel current. In contrast, the WSe2 channel in the CAA structure of the transistor in this embodiment is essentially a back-gate structure, and there is no channel area lacking gate modulation, thus avoiding the above problems.

[0061] Example 2

[0062] like Figure 5 As shown, this embodiment provides a method for fabricating a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitride CAA structure. The reconfigurable ferroelectric transistor based on the two-dimensional monolayer tungsten selenide and aluminum scandium nitride CAA structure of Embodiment 1 includes the following steps:

[0063] S1: As Figure 6 As shown in (a), the source / drain electrodes and silicon dioxide transition layer were fabricated by two magnetron sputtering operations and one plasma-enhanced chemical vapor deposition (PECVD).

[0064] S2: As Figure 6 As shown in (b), a hard mask is etched by photolithography, and then the channel and gate via are etched.

[0065] S3: As Figure 6As shown in (c), a large-area thin layer of WSe2 is grown by metal-organic chemical vapor deposition (MOCVD) to achieve the deposition of the channel layer.

[0066] S4: As Figure 6 As shown in (d), since the existing AlScN deposition process is pulsed DC sputtering, the anisotropic growth cannot form a uniform thickness AlScN film on the sidewall. Therefore, it is necessary to first deposit a thicker AlScN film through this process so that AlScN fills the entire gate via. Then, the gate metal via is obtained through photolithography and inductively coupled plasma reactive etching (ICP-RIE).

[0067] S5: As Figure 6 As shown in (e), a molybdenum (Mo) electrode is deposited, and excess molybdenum (Mo) electrode is removed by chemical mechanical polishing (CMP) to complete the planarization of the top of the device;

[0068] S6: As Figure 6 As shown in (f), photolithography removes excess tungsten selenide (WSe2), AlScN, and molybdenum (Mo).

[0069] S7: As Figure 6 As shown in (g), the silicon dioxide transition layer is removed by wet etching to complete the device construction.

[0070] Example 3

[0071] To further verify that the reconfigurable ferroelectric transistor based on the CAA structure of two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen in Example 1 has programmable characteristics, this example provides several examples of reconfigurable logic circuits designed based on this transistor. The main functions implemented include NOT logic, NAND / NOR logic, and XOR / XNOR logic.

[0072] In this embodiment, the voltage of both the high-level logic signal and the voltage source (VDD) is set to 0.5V, and the voltage of both the low-level logic signal and the signal ground (GND) is set to 0V. Positive pulse programming is used for n-type transistors, while negative pulse programming is used for p-type transistors, and the pulse amplitudes can be equal. Switching the programming voltage polarity, and adjusting the VDD and GND access nodes during logic function reconfiguration, are configured using internal programmable interconnect resources.

[0073] like Figure 7As shown in (a)-(c), the circuit topology, truth table, and input / output curves of the non-logic unit are obtained. The basic circuit topology is a CMOS inverter, where the pull-up network consists of transistor T1 and the pull-down network consists of transistor T2. The gates of transistors T1 and T2 are connected, serving as the programming voltage input terminal and the logic signal input terminal V. i The drains of transistors T1 and T2 are connected, and the voltage at the interconnect node serves as the logic signal output V. o The source of transistor T1 and V DD The source of transistor T2 is connected to GND. During use, it is connected to V... i Inputting a logic signal at the terminal will result in output V. o The opposite logical signal is received.

[0074] like Figure 8 As shown in (a)-(c), the circuit topology, truth table, and input / output curves of the NAND / OR NOT logic unit are obtained. The basic circuit topology is as follows: Transistor T1 and transistor T2 are connected in parallel, with their gates serving as the input terminals for signals A and B, respectively. One end of the source and drain is marked as 'a', used to connect to the power rail (V). DD One end is connected to the ground rail (GND), and the other end is connected to the T3 transistor, which also serves as the signal output point V. o Transistor T3 and transistor T4 are connected in series, with their gates serving as the input terminals for signals A and B, respectively. One end of the source and drain of T3 serves as V. o It is connected to T1 and T2 in parallel, and the other end is connected to T4; one end of the source and drain portion of transistor T4 is connected to T3, and the other end is marked as b, which is used to connect to V. DD Or GND. When NAND logic is required, V... DD Connect GND to port a, and connect GND to port b. Program transistors T1 and T2 as p-type transistors, and transistors T3 and T4 as n-type transistors. When NOR logic is required, connect GND to port a, and connect V... DD Connect to port b to program transistors T1 and T2 as n-type transistors, and transistors T3 and T4 as p-type transistors.

[0075] like Figure 9As shown in (a)-(c), the circuit topology, truth table, and input / output curves of the XOR / XNOR logic unit are obtained. The basic circuit topology is as follows: transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8 are connected in series in pairs to form four groups, abbreviated as T1T2, T3T4, T5T6, and T7T8. The groups T1T2 and T3T4 are connected in parallel, and the groups T5T6 and T7T8 are connected in parallel, resulting in two parts, abbreviated as T1-T4 and T5-T8. One end of the T1-T4 part is marked 'a' and is used to connect to V. DD Alternatively, GND is connected to one end of section T5-T8, and the other end is connected to it, serving as the signal output point V. o One end of section T5-T8 is connected to section T1-T4 and serves as the signal output point V. o The other end is marked as b, used to connect V. DD Or GND. When XOR logic is required, V... DD Connect GND to port a, and connect GND to port b. Program T1-T4 as p-type transistors and T5-T8 as n-type transistors. When XNOR logic is required, connect GND to port a, and connect V... DD Connect to port b, and program T1-T4 as n-type transistors and T5-T8 as p-type transistors.

[0076] The transistor proposed in this embodiment has programmable characteristics, and is therefore suitable for constructing logic blocks in novel low-power programmable logic devices. The constructed logic blocks have good compatibility, and their design can interface with the programmable interconnect resources and I / O blocks inside existing programmable logic devices.

[0077] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure, characterized in that, The transistor adopts a CAA structure, specifically including: gate electrode, aluminum scandium nitride (AlScN) ferroelectric layer, single-layer tungsten selenide (MLWSe2) channel layer, source electrode, and drain electrode; The gate electrode adopts a T-shaped structure; An aluminum scandium nitride (AlScN) ferroelectric layer is arranged in a ring around the vertical section of the gate electrode T-shaped structure and extends to the bend. The inner surface of the AlScN ferroelectric layer is in contact with the gate electrode, and part of the AlScN ferroelectric layer is exposed to air at the bend. A monolayer tungsten selenide (ML WSe2) channel layer surrounds the outer surface of the aluminum scandium nitride (AlScN) ferroelectric layer, and the monolayer tungsten selenide (ML WSe2) channel layer is partially exposed to air at the bend. The source and drain are respectively annularly surrounding the upper and lower halves of the vertical section of the monolayer tungsten selenide ML WSe2 channel layer. The source and drain are arranged along the extension direction of the vertical section, and there is a gap between the source and drain. A programming pulse voltage is applied to the gate electrode to change the polarization direction of the ferroelectric layer and couple the polarization electric field to the channel region. Under the action of pulse programming voltage, the polarization of the AlScN ferroelectric layer is reversed, which induces the generation of bound charges at the channel interface, reduces the Schottky barrier of the other polarity carriers, and thus changes the type of carriers in the channel. The conductivity polarity can be switched by injecting electrons or holes into the source electrode.

2. The reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure according to claim 1, characterized in that, The source and drain electrodes are made of titanium, indium, palladium, gold, platinum or graphite.

3. The reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure according to claim 1, characterized in that, The gate electrode uses platinum, gold, molybdenum, titanium, aluminum, or nickel as the electrode material.

4. The reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure according to claim 1, characterized in that, When gate programming pulses of different sizes and polarities are applied to the gate electrode, the reconfigurable ferroelectric transistor can be configured as an n-type field-effect transistor or a p-type field-effect transistor with different threshold voltages.

5. The reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitrogen CAA structure according to claim 1, characterized in that, The thickness of the AlScN ferroelectric layer decreases as the transistor size decreases, while the characteristics of coercive electric field, remanent polarization intensity, and saturation polarization intensity remain stable.

6. The method for fabricating a reconfigurable ferroelectric transistor based on a two-dimensional monolayer tungsten selenide and aluminum scandium nitride CAA structure according to any one of claims 1-5, characterized in that, Includes the following steps: Source, drain, and silicon dioxide transition layer were prepared by two magnetron sputtering processes and one plasma-enhanced chemical vapor deposition process. The channel and gate via are obtained by photolithography etching; The channel layer is deposited by generating a tungsten selenide layer through organometallic chemical vapor deposition; An aluminum scandium nitrogen (AlScN) film is deposited using a deposition process to fill the entire gate via. A uniform AlScN ferroelectric layer with sidewall thickness and a gate metal via are obtained by photolithography and inductively coupled plasma etching. Deposit the gate electrode, and remove excess gate electrode material through chemical mechanical polishing to complete the planarization of the top of the transistor; Excess tungsten selenide, scandium nitride, and gate electrode material are removed by photolithography. Transistor fabrication is achieved by removing the silicon dioxide transition layer through wet etching.

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