Data path switching method and retiming chip
By detecting the device lockout status in the retimer controller and using the error injection function to switch the low-latency path, the problems of reduced link latency performance and high switching complexity of the Retimer chip are solved, achieving reliable low-latency path switching and improved stability.
Patent Information
- Application Number
- CN202511538886.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-01-16
AI Technical Summary
While existing retimer chips improve PCIe link signal quality and extend link length, they also lead to a decrease in link latency performance. Furthermore, low-latency path switching suffers from probabilistic failures and high complexity, limiting their application to specific types of servers.
By detecting whether the root device and terminal device are in the receiver locked state in the retiming controller, the error injection function of the ordered training set is enabled to keep the device in the locked state, and then the low-latency mode path is switched to. The error injection function is then turned off at an appropriate time, simplifying the switching process.
It achieves reliable low-latency path switching, reduces switching complexity, expands application scenarios, is suitable for various types of devices, and enhances link stability.
Smart Images
Figure CN121349936A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a data path switching method and a retiming chip. Background Technology
[0002] While retimer chips improve PCIe (Peripheral Component Interconnect Express) link signal quality and extend PCIe link length, they also increase link latency, leading to a decrease in link latency performance. To reduce the link latency introduced by the retimer chip, the retimer chip needs to support low-latency characteristics. Existing solutions typically perform low-latency path switching in the rcvrcfg (receiver configuration) state, which suffers from probabilistic switching failures and link instability. Furthermore, it requires collaborative processing from the root device, the retimer chip, and the end device, resulting in high complexity and limiting its applicability to specific server types.
[0003] Therefore, ensuring reliable low-latency path switching, reducing the complexity of low-latency path switching, and expanding application scenarios are technical problems that need to be solved by those skilled in the art. Summary of the Invention
[0004] In view of this, the purpose of this application is to provide a data path switching method and a retiming chip, which can reliably complete the switching of low-latency paths, reduce the complexity of low-latency path switching, and expand the application scenarios. The specific solution is as follows:
[0005] Firstly, this application provides a data path switching method applied to a retiming controller, comprising:
[0006] When the data path is in normal mode, it is detected whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiving end locked state. The normal mode path includes a forwarding mode path and an execution mode path.
[0007] If both the root device and the terminal device are in the receiver locked state, then the error injection function for the ordered training set is enabled so that both the root device and the terminal device remain in the receiver locked state.
[0008] Switch the data path to a low-latency mode and disable the error injection function.
[0009] Optionally, detecting whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiver-locked state includes:
[0010] Detect whether the retiming controller itself has completed rate switching, or whether both the root device and the terminal device have completed link balancing;
[0011] If the retiming controller completes its own rate switching, or if both the root device and the terminal device complete link balancing, then it is determined that both the root device and the terminal device are in the receiver-locked state.
[0012] Optionally, before enabling error annotation for ordered training sets, the following are also included:
[0013] Detect whether there is an ordered training set for upstream pseudo-ports and whether there is an ordered training set for downstream pseudo-ports;
[0014] When there is an ordered training set on the upstream pseudo-port, the error injection function for the ordered training set is enabled in the first direction, wherein the first direction is from the upstream pseudo-port to the downstream pseudo-port.
[0015] If there is an ordered training set for the downstream pseudo-port, enable the error injection function for the ordered training set in the second direction, where the second direction is from the downstream pseudo-port to the upstream pseudo-port.
[0016] Optionally, before switching the data path to a low-latency mode path, the following method is also included:
[0017] Detect whether the data path has been switched to a forwarding mode path. If the data path has been switched to a forwarding mode path, trigger the step of switching the data path to a low-latency mode path.
[0018] Optional, also includes:
[0019] When the data path is in low-latency mode, detect whether both the root device and the terminal device are at the switching rate.
[0020] If both the root device and the terminal device are at the switching rate, and the link between the root device and the terminal device is idle, and the retiming controller enters the switching rate state, then the data path is switched to a forwarding mode path.
[0021] Optional, also includes:
[0022] If the data path is in low-latency mode and the root device is detected to be in link balancing state, the data path is switched to forwarding mode.
[0023] Secondly, this application provides a retiming chip, including a retiming controller, which is used to execute the aforementioned data path switching method.
[0024] Optional, also includes:
[0025] A first selector and a second selector connected to the retiming controller;
[0026] The first selector includes a first control signal input terminal, a first input terminal, and a second input terminal. The first input terminal is used to input data of the normal mode path, and the second input terminal is used to input data of the low latency path. The first control signal input terminal is used to input the first path switching control signal output by the retiming controller. The first selector is used to select, under the control of the first path switching control signal, to output either the data of the normal mode path input by the first input terminal or the data of the low latency path input by the second input terminal to the root device.
[0027] The second selector includes a second control signal input terminal, a third input terminal, and a fourth input terminal. The third input terminal is used to input data of the normal mode path, and the fourth input terminal is used to input data of the low latency path. The second control signal input terminal is used to input the second path switching control signal output by the retiming controller. The second selector is used to select, under the control of the second path switching control signal, to output either the data of the normal mode path input by the third input terminal or the data of the low latency path input by the fourth input terminal to the terminal device.
[0028] Optional, also includes:
[0029] The first low-latency path processing module, which is connected to the second input terminal, is used to perform cross-asynchronous processing of transmitted data, obtain the data of the low-latency path, and output it to the first selector;
[0030] The second low-latency path processing module, connected to the fourth input terminal, is used to perform cross-asynchronous processing of the transmitted data, obtain the data of the low-latency path, and output it to the second selector.
[0031] Optional, also includes:
[0032] A first serial-to-parallel conversion module is connected to the output of the first selector, and the output of the first serial-to-parallel conversion module is connected to the root device;
[0033] A second serial-to-parallel conversion module is connected to the output of the second selector, and the output of the second serial-to-parallel conversion module is connected to the terminal device;
[0034] Accordingly, the first selector is specifically used, under the control of the first path switching control signal, to select and output the data of the low-latency path input at the first input terminal or the data of the low-latency path input at the second input terminal to the first serial converter module for transmission to the root device; the second selector is specifically used, under the control of the second path switching control signal, to select and output the data of the low-latency path input at the third input terminal or the data of the low-latency path input at the fourth input terminal to the second serial converter module for transmission to the terminal device.
[0035] Thirdly, this application provides a data path switching device applied to a retiming controller, comprising:
[0036] The detection module is used to detect whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiving-end locked state when the data path is a normal mode path. The normal mode path includes a forwarding mode path and an execution mode path.
[0037] The error-injection module is used to enable the error-injection function for the ordered training set if both the root device and the terminal device are in the receiving end locked state, so that both the root device and the terminal device remain in the receiving end locked state.
[0038] The switching module is used to switch the data path to a low-latency mode and disable the error injection function.
[0039] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned data path switching method.
[0040] Fifthly, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned data path switching method.
[0041] As can be seen from the above scheme, the present invention provides a data path switching method applied to a retiming controller, comprising: when the data path is a normal mode path, detecting whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiver-locked state, wherein the normal mode path includes a forwarding mode path and an execution mode path; if both the root device and the terminal device are in the receiver-locked state, then enabling the error injection function for the ordered training set so that both the root device and the terminal device remain in the receiver-locked state; switching the data path to a low-latency mode path and disabling the error injection function.
[0042] Therefore, the beneficial effects of this application are as follows: When the data path is in normal mode, if both the root device upstream of the retiming controller and the terminal device downstream are detected to be in a receiver-locked state, error injection is performed on the ordered training set to keep both the root device and the terminal device in the receiver-locked state. Switching to the low-latency path in this state reduces the robustness requirements of the devices during low-latency path switching, avoids switching failures, eliminates the need for complex processing, simplifies the circuit, eliminates the need for upstream and downstream device coordination, and is adaptable to various types of devices. This ensures reliable low-latency path switching, reduces the complexity of low-latency path switching, and expands the application scenarios.
[0043] Correspondingly, the retiming chip, data path switching device, readable storage medium, and product provided in this application also have the above-mentioned technical effects. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0045] Figure 1 A flowchart of a data path switching method provided in an embodiment of this application;
[0046] Figure 2 A control plane flowchart for switching a Retimer controller from FORWARDING_PATH / EXE_PATH to BYPASS_PATH is provided for embodiments of this application.
[0047] Figure 3A control plane flowchart for switching the Retimer controller from BYPASS_PATH to FORWARDING_PATH in a speed-changing scenario is provided in this application embodiment.
[0048] Figure 4 This application provides a control plane flowchart for switching the Retimer controller from BYPASS_PATH to FORWARDING_PATH in a non-speed-change redo EQ scenario.
[0049] Figure 5 This is a schematic diagram of a retiming chip structure provided in an embodiment of this application;
[0050] Figure 6 This is a circuit diagram of a data path switching based on a retiming chip, provided as an embodiment of this application. Detailed Implementation
[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0052] While retimer chips improve PCIe link signal quality and extend PCIe link length, they also increase link latency, leading to a decrease in link latency performance. To reduce the link latency introduced by the retimer, it needs to support low-latency features. In existing technologies, only specific server models support low-latency features in conjunction with downstream devices; other servers do not. Current low-latency path switching technologies select the switching time during the rcvrcfg state, which can lead to probabilistic switching failures and link instability. Furthermore, current low-latency path exit timing is inconsistent, causing the RC (Root Complex) and EP (Endpoint) to detect link anomalies upon exit, resulting in probabilistic problems. Therefore, this application provides a data path switching scheme to solve the aforementioned technical problems.
[0053] See Figure 1 As shown in the figure, this application discloses a data path switching method applied to a retiming controller, including:
[0054] Step S11: When the data path is in normal mode, detect whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiving-end locked state. The normal mode path includes a forwarding mode path and an execution mode path.
[0055] The data path, specifically the data path of the retiming chip equipped with the retiming controller, is used to realize data transmission between the root device and the terminal device. FORWARDING_PATH (the forwarding mode path) and EXE_PATH (the execution mode path) are two data paths of the retiming controller, responsible for signal relay and local processing, respectively. Recovery.RcvrLock (the receiver-locked state) is a sub-state within the Recovery state in the PCIe link training and state machine. Its main function is to ensure stable clock and data synchronization between the receiver and transmitter. In this state, it switches to a low-latency path, ensuring reliable data transmission while reducing latency.
[0056] This application embodiment can detect whether the retiming controller itself has completed rate switching, or whether the root device and the terminal device have both completed link balancing; if the retiming controller itself has completed rate switching, or the root device and the terminal device have both completed link balancing, then it is determined that the root device and the terminal device are both in the receiver locked state.
[0057] That is, in this embodiment of the application, it can be determined whether the root device and the terminal device are both in the receiver-locked state by detecting whether the retiming controller itself has completed the rate switching or whether the root device and the terminal device have both completed link balancing.
[0058] Step S12: If both the root device and the terminal device are in the receiver locked state, then enable the error injection function for the ordered training set so that both the root device and the terminal device remain in the receiver locked state.
[0059] Enabling error injection for the ordered training set involves enabling bidirectional error injection on the link, ensuring that both the root device and the terminal device remain locked at the receiving end. Error injection is the function of injecting erroneous data.
[0060] Before enabling the error injection function for the ordered training set, this embodiment may further: detect whether an ordered training set exists for the upstream pseudo-port and detect whether an ordered training set exists for the downstream pseudo-port; if an ordered training set exists for the upstream pseudo-port, enable the error injection function for the ordered training set in a first direction, wherein the first direction is from the upstream pseudo-port to the downstream pseudo-port; if an ordered training set exists for the downstream pseudo-port, enable the error injection function for the ordered training set in a second direction, wherein the second direction is from the downstream pseudo-port to the upstream pseudo-port.
[0061] Furthermore, it detects whether the data path has been switched to a forwarding mode path. If the data path has been switched to a forwarding mode path, it triggers the step of switching the data path to a low-latency mode path.
[0062] In this embodiment, it can detect whether both the first direction and the second direction are switched to the forwarding mode. If both the first direction and the second direction are switched to the forwarding mode, it is determined that the data path has been switched to the forwarding mode, and the step of switching the data path to the low-latency mode is triggered.
[0063] Although in an optional implementation, the data path can be switched to a low-latency mode path in execution mode, the step of first switching the data path to a forwarding mode path and then triggering the switch to a low-latency mode path ensures serial switching of the path within the retiming chip, resulting in higher reliability.
[0064] Step S13: Switch the data path to a low-latency mode path and disable the error injection function.
[0065] In this application, the low-latency mode path is a path with lower latency than the normal mode path. The low-latency mode path can be preset in the retiming chip. When the switching conditions are met, the path switches to the low-latency mode path. In an optional implementation, the low-latency mode path can be implemented by a low-latency path processing module. Furthermore, low-latency path processing modules can be set in two directions respectively. These modules can perform asynchronous processing of transmitted data to obtain data from the low-latency path. That is, in any direction, there can be two data paths: one transmitted to the retiming controller via the normal mode path, and the other transmitted to the low-latency path processing module via the low-latency mode path. A selector can be used to select whether to transmit data via the normal mode path or the low-latency path. Switching the data path to the low-latency mode path involves outputting a path switching control signal to the selector, allowing the selector to choose between the normal mode path or the low-latency path based on the path switching control signal. If the path switching control signal is 0, the normal mode path is selected; if it is 1, the low-delay path is selected. The error injection function is disabled, that is, the error injection functions for both the first and second directions are disabled.
[0066] See Figure 2 As shown, Figure 2 This is a control plane flowchart of a Retimer controller switching from FORWARDING_PATH / EXE_PATH to BYPASS_PATH, as disclosed in an embodiment of this application. It represents a single Retimer scenario, where BYPASS_PATH is the low-latency mode path. In the case of FORWARDING_PATH / EXE_PATH, it checks whether the rate switching is complete or EQ (Equalization) has ended. If the switching is complete or EQ has ended, it indicates that the link is in a locked state, i.e., the receiver is locked. It determines whether the UP (upstream-facing) pseudo-port and DP (downstream-facing) pseudo-port have detected the bitstream, i.e., the ordered training set. If the UP pseudo-port detects the bitstream, the bitstream error injection function is enabled in the UP to DP direction; if the DP pseudo-port detects the bitstream, the bitstream error injection function is enabled in the DP to UP direction. After switching to forwarding paths in both directions, 1. both directions simultaneously switch to low-latency paths; 2. the bitstream modification function (error injection) in both directions is disabled.
[0067] Furthermore, embodiments of this application may also include: when the data path is a low-latency mode path, detecting whether both the root device and the terminal device are at the switching rate; if both the root device and the terminal device are at the switching rate, and the link between the root device and the terminal device is in an idle state and the retiming controller enters the switching rate state, then switching the data path to a forwarding mode path.
[0068] See Figure 3 As shown, Figure 3 This application provides a control plane flowchart for a Retimer controller switching from BYPASS_PATH to FORWARDING_PATH in a rate-switching scenario, as provided in an embodiment of the present application. This is a single Retimer scenario. First, it detects whether the link is at the switching rate. If the link switching rate is detected, it checks whether the link is in EI (i.e., idle) state and whether the controller has entered the rate-switching state. If both are true, it switches to FORWARDING_PATH simultaneously in both directions.
[0069] Furthermore, embodiments of this application may also include: when the data path is a low-latency mode path, if the root device is detected to enter a link balancing state, the data path is switched to a forwarding mode path.
[0070] This application embodiment can detect when the root device enters a link balancing state by detecting the ordered training set of pseudo-ports facing upstream. The data path is switched to forwarding mode, that is, a path switched to forwarding mode in both the first and second directions.
[0071] See Figure 4 As shown, Figure 4 This application provides a control plane flowchart for switching the Retimer controller from BYPASS_PATH to FORWARDING_PATH in a non-speed-change redo EQ scenario, as provided in an embodiment of this application. This is a single Retimer scenario. The UP pseudo-port detects whether the RC has entered EQ (equilibration) state; if so, both directions simultaneously switch to FORWARDING_PATH.
[0072] In this embodiment, the selection of the low-latency path exit time point is more reasonable, which enhances the stability of the link.
[0073] This provides a novel method for switching between low-latency data paths and forwarding or execution paths in a Retimer controller. The solution provided in this application can be used at GEN4-GEN6 rates to switch the Retimer chip from the normal (i.e., normal mode) path to the low-latency path after the link has completed the rate switching or EQ process. It provides a link error injection mechanism to ensure that all devices remain stable in the rcvrlock state during low-latency path switching; it provides a link switching mechanism to ensure serial switching of paths within the Retimer chip; and it provides multiple low-latency path exit points, which can prevent RC and EP devices from detecting link anomalies in some scenarios, improving robustness.
[0074] As can be seen, in the embodiment of this application, when the data path is in normal mode and both the upstream root device and the downstream terminal device of the retiming controller are detected to be in a receiver-locked state, errors are injected into the ordered training set to keep both the root device and the terminal device in the receiver-locked state. In this state, the low-latency path is switched, reducing the robustness requirements of the devices during the low-latency path switching process, avoiding switching failures, eliminating the need for complex processing, simplifying the circuit, and requiring no coordination between upstream and downstream devices, thus adapting to various types of devices. This ensures reliable low-latency path switching, reduces the complexity of low-latency path switching, and expands the application scenarios. Furthermore, the selection of the low-latency path exit time point is more reasonable, enhancing the stability of the link.
[0075] Furthermore, this application provides a retiming chip, including a retiming controller, which is used to execute the data path switching method disclosed in the foregoing embodiments. See also Figure 5 As shown, Figure 5 This is a schematic diagram of a retiming chip structure provided in an embodiment of this application.
[0076] Furthermore, the retiming chip also includes: a first selector and a second selector connected to the retiming controller; the first selector includes a first control signal input terminal, a first input terminal, and a second input terminal, the first input terminal being used to input data of the normal mode path, the second input terminal being used to input data of the low latency path, the first control signal input terminal being used to input a first path switching control signal output by the retiming controller, and the first selector being used, under the control of the first path switching control signal, to select whether to output the data of the normal mode path input by the first input terminal or the data of the low latency path input by the second input terminal to the root device; the second selector includes a second control signal input terminal, a third input terminal, and a fourth input terminal, the third input terminal being used to input data of the normal mode path, the fourth input terminal being used to input data of the low latency path, the second control signal input terminal being used to input a second path switching control signal output by the retiming controller, and the second selector being used, under the control of the second path switching control signal, to select whether to output the data of the normal mode path input by the third input terminal or the data of the low latency path input by the fourth input terminal to the terminal device.
[0077] That is, when the retiming controller switches the data path to a low-delay mode path, it inputs the corresponding path switching control signals to the first selector and the second selector respectively.
[0078] Furthermore, the retiming chip also includes:
[0079] The first low-latency path processing module, which is connected to the second input terminal, is used to perform cross-asynchronous processing of transmitted data, obtain the data of the low-latency path, and output it to the first selector;
[0080] The second low-latency path processing module, connected to the fourth input terminal, is used to perform cross-asynchronous processing of the transmitted data, obtain the data of the low-latency path, and output it to the second selector.
[0081] Furthermore, the retiming chip also includes:
[0082] A first serial-to-parallel conversion module is connected to the output of the first selector, and the output of the first serial-to-parallel conversion module is connected to the root device;
[0083] A second serial-to-parallel conversion module is connected to the output of the second selector, and the output of the second serial-to-parallel conversion module is connected to the terminal device;
[0084] Accordingly, the first selector is specifically used, under the control of the first path switching control signal, to select and output the data of the low-latency path input at the first input terminal or the data of the low-latency path input at the second input terminal to the first serial converter module for transmission to the root device; the second selector is specifically used, under the control of the second path switching control signal, to select and output the data of the low-latency path input at the third input terminal or the data of the low-latency path input at the fourth input terminal to the second serial converter module for transmission to the terminal device.
[0085] See Figure 6 As shown, Figure 6 This application provides a circuit structure diagram for switching data paths based on a retiming chip. a2b_data: Data output from the RC transmitter, intended for transmission to the EP receiver; a2b_data_normal: Data originating from a2b_data and processed by the controller; a2b_data_bp: Data originating from a2b_data and processed by the low-latency data processing module; b2a_data: Data output from the EP transmitter, intended for transmission to the RC receiver; b2a_data_normal: Data originating from b2a_data and processed by the controller; b2a_data_bp: Data originating from b2a_data and processed by the low-latency data processing module; a_phy: The SERDE module near the RC side, i.e., the first serial-to-parallel conversion module; b_phy: The SERDE module near the EP side, i.e., the second serial-to-parallel conversion module; MUX: Data path selection module, which selects one of the multiple data paths for output based on the control signal. The first selector is connected to the first serial-to-parallel conversion module, and the second selector is connected to the second serial-to-parallel conversion module. ASYNC_FIFO_BP_MODULE: Low-latency data path processing module, mainly responsible for cross-asynchronous data processing. The first low-latency path processing module is connected to the first selector, and the second low-latency path processing module is connected to the second selector. BP_MODULE: Low-latency control module, responsible for generating path switching controller signals, i.e., used to execute the data path switching method disclosed in the aforementioned embodiments. During data path switching, it outputs path switching controller signals to the first and second selectors. Select: Path switching control signal.
[0086] This application expands the application scenarios of low latency, making it applicable not only to specific servers but also to other common servers. The circuitry is significantly simplified; compared to the complex data processing required for switching to low latency during the `recovery.rcvrcfg` stage, this application can directly switch data paths without complex data processing. This application chooses to switch to low latency during the `recovery.rcvrlock` stage, utilizing the fact that the `rcvrlock` stage itself is used to transition each device in the link from an unstable to a stable state to switch low latency paths, which reduces the robustness requirements on devices during low latency path switching. Simultaneously, the low latency path exit point is selected more rationally; switching from a low latency path to a normal path during speed switching is seamless and imperceptible to the link, enhancing link stability.
[0087] Furthermore, embodiments of this application provide a data path switching device applied to a retiming controller, comprising:
[0088] The detection module is used to detect whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in a receiving-end locked state when the data path is a normal mode path. The normal mode path includes a forwarding mode path and an execution mode path.
[0089] The error-injection module is used to enable the error-injection function for the ordered training set if both the root device and the terminal device are in the receiving end locked state, so that both the root device and the terminal device remain in the receiving end locked state.
[0090] The switching module is used to switch the data path to a low-latency mode and disable the error injection function.
[0091] As can be seen, in the embodiment of this application, when the data path is in normal mode and both the upstream root device and the downstream terminal device of the retiming controller are detected to be in a receiver-locked state, errors are injected into the ordered training set to keep both the root device and the terminal device in the receiver-locked state. In this state, the low-latency path is switched, reducing the robustness requirements of the devices during the low-latency path switching process, avoiding switching failures, eliminating the need for complex processing, simplifying the circuit, and requiring no coordination between upstream and downstream devices, thus adapting to various types of devices. This ensures reliable low-latency path switching, reduces the complexity of low-latency path switching, and expands the application scenarios. Furthermore, the selection of the low-latency path exit time point is more reasonable, enhancing the stability of the link.
[0092] Furthermore, embodiments of this application also disclose a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data path switching method disclosed in the foregoing embodiments.
[0093] For details regarding the specific process of the above data path switching method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.
[0094] Furthermore, embodiments of this application provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the data path switching method disclosed in the foregoing embodiments.
[0095] For details regarding the specific process of the above data path switching method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.
[0096] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0097] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0098] The above provides a detailed description of a data path switching method and a retiming chip provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method of data path switching, characterized by, The application is applied to a retiming controller, comprising: In the case that the data path is a normal mode path, detecting whether a root device upstream of the retiming controller and a terminal device downstream of the retiming controller are in a receiving end lock state, wherein the normal mode path comprises a forwarding mode path and an execution mode path; If both the root device and the terminal device are in the receiving end lock state, starting an error injection function for an ordered training set, so that both the root device and the terminal device are maintained in the receiving end lock state; Switching the data path to a low delay mode path and closing the error injection function.
2. The data path switching method of claim 1, wherein, The detection of whether the root device upstream of the retiming controller and the terminal device downstream of the retiming controller are in the receiving end lock state comprises: Detecting whether the retiming controller itself completes rate switching or whether both the root device and the terminal device complete link equalization; If the retiming controller itself completes rate switching or both the root device and the terminal device complete link equalization, it is determined that both the root device and the terminal device are in the receiving end lock state.
3. The data path switching method of claim 1, wherein, Before starting the error injection function for the ordered training set, further comprising: Detecting whether there is an ordered training set in a pseudo port facing upstream and detecting whether there is an ordered training set in a pseudo port facing downstream; In the case that there is an ordered training set in the pseudo port facing upstream, starting the error injection function for the ordered training set in a first direction, wherein the first direction is a direction from the pseudo port facing upstream to the pseudo port facing downstream; In the case that there is an ordered training set in the pseudo port facing downstream, starting the error injection function for the ordered training set in a second direction, wherein the second direction is a direction from the pseudo port facing downstream to the pseudo port facing upstream.
4. The data path switching method of claim 1, wherein, Before switching the data path to the low delay mode path, further comprising: Detecting whether the data path has been switched to the forwarding mode path, and in the case that the data path has been switched to the forwarding mode path, triggering the step of switching the data path to the low delay mode path.
5. The data path switching method of claim 1, wherein, Further comprising: In the case that the data path is the low delay mode path, detecting whether both the root device and the terminal device are switching rates; If both the root device and the terminal device are switching rates, and a link between the root device and the terminal device is in an idle state and the retiming controller enters a switching rate state, switching the data path to the forwarding mode path.
6. The data path switching method of claim 1, wherein, Further comprising: In the case that the data path is the low delay mode path, if it is detected that the root device enters a link equalization state, switching the data path to the forwarding mode path.
7. A retiming chip, characterized by The application further comprises:
8. The retiming chip of claim 7, wherein, A first selector and a second selector connected with the retiming controller. The application further comprises: A first selector and a second selector connected with the retiming controller. The first selector comprises a first control signal input end, a first input end and a second input end, the first input end is used for inputting data of a normal mode path, the second input end is used for inputting data of a low latency path, the first control signal input end is used for inputting a first path switching control signal output by the retiming controller, and the first selector is used for outputting data of the normal mode path input by the first input end or data of the low latency path input by the second input end to the root device under control of the first path switching control signal. The second selector comprises a second control signal input end, a third input end and a fourth input end, the third input end is used for inputting data of a normal mode path, the fourth input end is used for inputting data of a low latency path, the second control signal input end is used for inputting a second path switching control signal output by the retiming controller, and the second selector is used for outputting data of the normal mode path input by the third input end or data of the low latency path input by the fourth input end to the terminal device under control of the second path switching control signal.
9. The retiming chip of claim 8, wherein, Further comprising: a first low latency path processing module connected with the second input end, used for performing cross-asynchronous processing on transmission data, obtaining data of a low latency path and outputting the data to the first selector; a second low latency path processing module connected with the fourth input end, used for performing cross-asynchronous processing on transmission data, obtaining data of a low latency path and outputting the data to the second selector.
10. The retiming chip of claim 9, wherein, Further comprising: a first serial-parallel conversion module connected with an output end of the first selector, and an output end of the first serial-parallel conversion module is connected with the root device; a second serial-parallel conversion module connected with an output end of the second selector, and an output end of the second serial-parallel conversion module is connected with the terminal device; Correspondingly, the first selector is specifically used for outputting data of the low latency path input by the first input end or data of the low latency path input by the second input end to the first serial conversion module under control of the first path switching control signal, so as to be transmitted to the root device; and the second selector is specifically used for outputting data of the low latency path input by the third input end or data of the low latency path input by the fourth input end to the second serial conversion module under control of the second path switching control signal, so as to be transmitted to the terminal device.