RAFT consensus algorithm acceleration system

Abstract

The invention discloses an RAFT consensus algorithm acceleration system, which belongs to the technical field of block chain algorithm acceleration and comprises a CPU (central processing unit), a bus bridging system, a network communication module, an RAFT algorithm acceleration module, a memory and a network interface. The CPU is used for completing control of an acceleration system, scheduling data to the RAFT algorithm acceleration module and converting message data conforming to a message frame format; the bus bridging system is formed by combining a plurality of buses and is used for carrying out protocol conversion on data according to different data frame formats; the network communication module is used for communicating with the RAFT algorithm acceleration module; the RAFT algorithm acceleration module is used for maintaining nodes, performing voting and election initiating operations through the network communication module, and completing RAFT consensus acceleration; the memory is composed of a high-speed memory array. The implementation of the RAFT consensus algorithm in the block chain is completed, the time delay is greatly reduced, and the effect of optimizing the performance is achieved.

Description

Technical Field

[0001] This invention belongs to the field of blockchain algorithm acceleration, and in particular relates to a RAFT consensus algorithm acceleration system. Background Technology

[0002] Blockchain is essentially a distributed database system, and consistency is the most crucial issue in distributed networks. Consensus algorithms were developed to address this problem, ensuring the consistency of distributed systems through algorithmic means. Consistency includes the consistency of transaction data, order, and node states. Commonly used blockchain consensus algorithms include Proof-of-Work (PoW), Proof-of-Stake (PoS), Delegated Proof-of-Stake (DPoS), Resolved Automated Optical Frames (RAFT), and Paxos. PoW, PoS, and DPoS are primarily used in public blockchains, requiring greater computing power and consuming more energy. RAFT and Paxos are more commonly used in consortium blockchains, offering lower energy consumption. RAFT is a consensus algorithm that is easier to implement in engineering.

[0003] Patents CN116248697A and CN114448996A introduce additional storage and backup nodes to the RAFT consensus mechanism. These additional nodes only accept compressed log data to reduce the amount of data transmitted. CN116248693A pre-compresses the logs of each node, and all nodes in the network use compressed log data for data synchronization to improve data transmission efficiency. Existing improvements are based on improving the transmission efficiency of logs in the network. While these improvements reduce the amount of data transmitted and increase the transmission speed, the compressed logs still need to be decompressed on the local node before the data can be submitted to the state machine, introducing new decompression overhead to the entire RAFT consensus process. CN1155567373A introduces circuit breakers to reduce the waiting time during invalid operations. CN116708460A introduces the K-means clustering algorithm to partition nodes into child nodes to optimize the RAFT consensus mechanism.

[0004] Current optimizations all focus on improving the algorithm itself, without specifying the hardware environment or devices for deployment. Furthermore, their acceleration effects are limited to traditional CPU computing systems and are not significant. Summary of the Invention

[0005] The purpose of this invention is to provide an accelerated system for the RAFT consensus algorithm to solve the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides a RAFT consensus algorithm acceleration system, comprising:

[0007] CPU, bus bridging system, network communication module, RAFT algorithm acceleration module, memory and network interface;

[0008] The CPU is used to control the acceleration system, schedule data to the RAFT algorithm acceleration module, convert message data into message frame format, and complete application layer software operations.

[0009] The bus bridging system is composed of multiple buses and is used to convert data according to different data frame formats.

[0010] The network communication module is used to communicate with the RAFT algorithm acceleration module;

[0011] The RAFT algorithm acceleration module is used to maintain nodes and perform voting and election operations through the network communication module to accelerate the RAFT consensus.

[0012] The memory consists of a high-speed memory array.

[0013] Preferably, the CPU is also used to execute a driver program to control the RAFT algorithm acceleration module to create nodes and configure the initial state.

[0014] Preferably, the network communication module is further configured to package and send the messages processed by the RAFT algorithm acceleration module that need to be sent over the network using network protocols.

[0015] Preferably, the RAFT algorithm acceleration module includes a node state machine, an election processing circuit, a decoding circuit, an encoding circuit, a timer circuit, and a function register module;

[0016] The node state machine is responsible for maintaining the node state;

[0017] The election processing circuit is used to process election messages in the RAFT consensus.

[0018] The decoding circuit is used to decode RAFT consensus algorithm messages;

[0019] The encoding circuit is used to encode RAFT consensus algorithm messages;

[0020] The timer circuit is used to configure the initial value, clock division function, and interrupt pulse signal generation function;

[0021] The function register module is used to convert software register read / write instructions into hardware signals.

[0022] Preferably, the node state machine is also used to configure initial registers and create nodes in the idle state.

[0023] Preferably, the election processing circuit starts a countdown for each node in the network with an initial value of its built-in timer, decrementing by 1 in each clock cycle. If no heartbeat signal is received continuously until the countdown reaches 0, the node with the countdown at 0 enters the candidate state and initiates an election. After the election begins, the candidate increments its election term number by 1, then packages its current term number and the log index number, and sends them to the encoding circuit and the decoding circuit to complete the election message sending process.

[0024] Preferably, the decoding circuit is further configured to define a message frame format, wherein the message frame format comprises a message header data frame and a message data frame;

[0025] The message header data frame includes information representing the data type, data source, log ID number, and return type;

[0026] The message data frame includes a term number, an index number, and voting information;

[0027] Both the message header data frame and the message data frame have a data length of 128 bits.

[0028] Preferably, the timer circuit is further configured to decrement according to the clock signal, and emit a pulse signal when the clock signal decrements to 0.

[0029] The technical advantages of this invention are as follows: the core consensus steps and memory image maintenance of RAFT consensus are all completed by hardware circuits. The storage circuit is closely connected to the RAFT algorithm library, forming an integrated storage and computing architecture, so that data scheduling between the RAFT algorithm library module and high-speed storage does not require the use of bus and CPU resources. The network communication module adopts two types of connections: one mounted on the bus and the other mounted on the RAFT consensus algorithm acceleration, supporting network transmission operations without CPU scheduling. This invention's RAFT consensus algorithm system, through the design of a specific circuit structure for the RAFT consensus library and its coordinated operation with the memory module, network communication module, and bus bridging module, completes the implementation of the RAFT consensus algorithm in the blockchain, greatly reducing latency and achieving optimized performance. Attached Figure Description

[0030] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0031] Figure 1 A schematic diagram of a RAFT consensus algorithm acceleration system in an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a specific RAFT consensus algorithm acceleration system in an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a message frame format in an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of the RAFT consensus acceleration module in an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the RAFT consensus acceleration module state transition in an embodiment of the present invention. Detailed Implementation

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0038] Example 1

[0039] This embodiment provides a RAFT consensus algorithm acceleration system, including:

[0040] The system comprises a CPU core, a storage module, a bus bridging system, a RAFT consensus algorithm acceleration module, a network communication module, and defines a consensus message frame format and acceleration method. These circuit modules work in coordination to accelerate the RAFT algorithm.

[0041] Its overall system structure is as follows Figure 1 As shown. The CPU core controls the acceleration system, scheduling data to the RAFT consensus module and converting it into message data conforming to the message frame format, as well as performing application layer software operations. The RAFT consensus algorithm acceleration module processes the message data to be agreed upon and outputs the data to the bus bridging module. The bus bridging system performs protocol conversion on the data according to different data frame formats and sends it to the downlink module, which may include the CPU core, storage module, and network communication module. The storage module consists of a high-speed storage array, characterized by its tight connection with the RAFT algorithm library, rather than just its connection to the bus bridging module. The network communication module is responsible for packaging and sending the messages processed by the RAFT algorithm library module that need to be sent over the network according to the network protocol.

[0042] The core RAFT consensus algorithm acceleration module includes a node state machine, election processing circuit, decoding circuit, encoding circuit, timer circuit, and function register module. Its specific structure is as follows: Figure 4 As shown.

[0043] The node state machine is the core control module of the RAFT consensus algorithm acceleration module, responsible for maintaining the node states. The RAFT algorithm has three node states: leader, candidate, and follower. The node state machine primarily maintains these three states. Depending on the actual operating characteristics of the circuit, there is also an idle state for configuring initial registers and creating a node; this state is active before node creation. The state machine transition diagram is as follows: Figure 5 As shown.

[0044] The primary function of the election processing circuit is to process election messages in the RAFT consensus mechanism. The election mechanism is a crucial component of the RAFT algorithm, and its specific algorithm flow is as follows: Each node in the network begins a countdown with an initial value from its built-in timer, decrementing by 1 each clock cycle. If no heartbeat signal is received until the timer reaches 0, the node with the timer at 0 enters the candidate state and initiates an election. After the election begins, the candidate increments its election term number by 1, then packages its current term number and log index number, and sends them to subsequent modules such as the encoding circuit to complete the election message transmission process.

[0045] The decoding circuit is responsible for decoding RAFT consensus algorithm messages. It defines a message frame format, in which message frames are combined into a message header and a message data frame. A data frame consists of 128 bits of data. This module decodes and processes the data before sending it to the various downlink modules.

[0046] The timer circuit is a built-in circuit designed to assist in the generation of heartbeat messages in the RAFT algorithm. Its function is to configure the initial value, decrease it according to the clock signal, and emit a pulse signal when it decreases to 0. The initial value can be generated by software as a random number and can be controlled by software in real time, so that it can also achieve the function of a circuit breaker.

[0047] The function register module mainly converts software register read and write instructions into hardware signals;

[0048] This invention specifies a RAFT message frame format as follows: Figure 3 As shown, it mainly consists of header data frames and message data frames. These two types of data frames together form the message frame, which is used to cooperate with the consensus operation accelerated by the RAFT consensus algorithm.

[0049] The acceleration method can be roughly divided into the following steps:

[0050] The CPU executes the driver program, which controls the RAFT algorithm acceleration module to create nodes.

[0051] The RAFT algorithm acceleration module begins its own initialization.

[0052] The RAFT algorithm acceleration module performs voting and election initiation operations through the network communication module.

[0053] The RAFT algorithm acceleration module completes self-election and, together with the CPU, storage module, and network communication module, begins to form a consensus.

[0054] Example 2

[0055] This embodiment provides a RAFT consensus algorithm acceleration system, including:

[0056] CPU, bus bridging system, network communication module, RAFT algorithm acceleration module, memory and network interface;

[0057] The CPU is used to control the acceleration system, schedule data to the RAFT algorithm acceleration module, convert message data into message frame format, and complete application layer software operations.

[0058] The bus bridging system is composed of multiple buses and is used to convert data according to different data frame formats.

[0059] The network communication module is used to communicate with the RAFT algorithm acceleration module;

[0060] The RAFT algorithm acceleration module is used to create nodes and perform voting and election operations through the network communication module to accelerate the RAFT consensus.

[0061] The memory consists of a high-speed memory array.

[0062] The solution has been further optimized as follows:

[0063] This embodiment presents an FPGA-based RAFT consensus algorithm acceleration system and method, including a RAFT consensus algorithm acceleration circuit, a memory module, a network communication module, AHB and APB bus modules, an E906 CPU core, and a message frame format. Figure 2 As shown, the CPU core is responsible for processing the software-written RAFT application layer driver, and its output is connected to the AHB bus module. The AHB bus is responsible for processing various bus protocol data, completing arbitration and forwarding, and its output is connected to the AHB interface of the AHB bus module, network communication module, RAFT algorithm library module, and memory module. The RAFT algorithm library is responsible for processing various consensus-related operations specified by the RAFT algorithm, and its output is connected to the network communication module, memory module, and AHB bus module. The network communication module is responsible for handling the unpacking and depacking of various network data packets, and its output is connected to the AHB bus module and network interface.

[0064] In this embodiment, the CPU module uses the E906 with the RISC-V instruction set, which has an AHB-lite bus protocol interface and supports floating-point operations; the memory module uses a BRAM-based memory matrix that can store 36Kb of data; the network communication module is responsible for converting data to be sent over the network into UDP packets and working with the network interface module to complete the sending and receiving of network protocols; the RAFT algorithm acceleration module is composed of a node state machine, election processing circuit, decoding circuit, encoding circuit, timer circuit, and function register module, and is mainly responsible for processing the RAFT consensus algorithm; the AHB and APB bridging modules together constitute the bus conversion system;

[0065] This embodiment specifies a message frame format, which consists of a header data frame and a message data frame. Both the header data frame and the message data frame are 128 bits long; therefore, the message frame is a 256-bit data packet. Its structure is as follows: Figure 3 As shown in Table 1, the functions of each field are defined in this embodiment.

[0066] Table 1

[0067]

[0068] The acceleration method can be roughly divided into the following steps:

[0069] 1. The CPU executes the driver program to control the RAFT algorithm acceleration module to create nodes.

[0070] 2. The RAFT algorithm acceleration module begins its own initialization.

[0071] 3. The RAFT algorithm acceleration module performs voting and election initiation operations through the network communication module.

[0072] 4. The RAFT algorithm acceleration module completes self-election and, together with the CPU, storage module, and network communication module, begins to form a consensus.

[0073] In steps one and two, the CPU executes the driver program, controls the RAFT algorithm acceleration module to create nodes, and begins initialization from the perspective of a single node. First, the initial state, ID number, and random initial timer values ​​for the new node are written. The CPU reads the software-written driver, issues instructions, and forwards them through the bus system to the RAFT consensus library module, completing the relevant register configurations, thereby creating a processing node in the RAFT algorithm library.

[0074] In step three, the RAFT algorithm acceleration module performs voting and election initiation operations through the network communication module. The detailed operation is as follows: After completing steps one and two, there are no election nodes in the network, and no node has received a heartbeat signal from the leader node. Therefore, all nodes' timers begin counting down. Because each node's initial timer value is different, the time it takes for the countdown to reach zero also differs. The node whose countdown reaches zero first enters the candidate state and initiates the election. The RAFT algorithm acceleration module is as follows: Figure 4 As shown, the following example illustrates the election processing flow within the RAFT algorithm library module, using the node initiating the election as an example. The built-in timer module triggers a pulse signal when the timer reaches zero. This pulse signal is output to the RAFT node state machine module, causing the RAFT node state machine to transition from a follower node to a leader node. The election processing module, controlled by the state machine, begins the election process, increments the election period (Term) by one, packages its election-related information, and outputs it to the encoding module. The encoding module packages the information into message frame format and then into a data format that the network protocol module can process. The network protocol module sends the election message frame to the network, waiting for responses from other nodes. The following example illustrates the voting operation processing within the RAFT algorithm library from the perspective of a non-candidate node. The non-candidate node receives data from the network protocol module, which unpacks it and sends the message frame format data to the RAFT consensus algorithm acceleration module. The RAFT consensus algorithm acceleration module receives the data and sends it to the decoding module. The decoding module splits and identifies the data as election request data and processes the header. Because of the inherent requirements of the RAFT algorithm, a follower node can only vote once per term. Therefore, for nodes that have not voted, the information is stored in the corresponding register, while nodes that have already voted discard the data packet. The election processing module reads the node's Term count and the log's Index count, compares them with the Term count and Index count in the data frame format, and determines whether to vote. If the determination is successful, a signal indicating successful voting is sent. The downlink encoding module then begins to package the voting data into message frames and sends them to the network protocol module to complete the network operation. When an elector node receives a sufficient number of voting message data frames, the election is successful, and the node's state machine transitions from a candidate node to a leader node. A diagram illustrating the state transition is shown below. Figure 5 As shown.

[0075] After the election is completed, the RAFT network has a single leader and several follower nodes. In this embodiment, step four, reaching consensus in the network, can then begin. At this point, the application layer client sends a consensus request. The CPU executes the driver code, packages the request into a message frame format, and outputs it to the AHB bus via register read / write operations. The AHB bus arbitrates the request, converts it into an AHB host message, and writes it to the RAFT algorithm library module. If the message is sent to a follower node, that node directly outputs the message to the network protocol module, forwarding it to the leader node. The leader node receives the data frame and sends it to the decoding module. The decoding module identifies and splits the frame, extracting log data, which is stored in the memory module. Then, the control module outputs the node's information to the encoding module. The encoding module packages the information and log data into a message data frame format and sends it to the network. Other nodes in the network applying this scheme read the data frame through the network protocol module. The RAFT algorithm library module receives the message frame and outputs it to the decoding module. The decoding module unpacks and identifies the message frame as a consensus request, then writes the Index and Term information in the header data frame format into the corresponding registers. The message frame data is first buffered. The RAFT control module compares the node's Term count and Index count with the Index and Term counts stored in the registers. If the comparison is successful, the log information in the message frame format is output to the encoder module, which segments and transforms it into an AHB data stream, writing it into the AHB-SRAM memory. Simultaneously, a return message frame is encoded, indicating successful submission, and sent to the network through the network protocol module, ultimately reaching the destination node in the RAFT network.

[0076] The following describes the application and synchronization process of the RAFT consensus log in this embodiment from the perspective of the leader node. Upon receiving the returned message frame, the leader node sends it from the network processing module to the RAFT consensus library module. The decoding module parses the frame; if successful, the control module increments the success count by one; otherwise, it discards the data packet without further action. When the leader node receives a success count that satisfies the success determination formula, it indicates that the client can be notified to perform application operations. The success determination formula is as follows:

[0077] (1-1)f=∑v-∑n / K

[0078] Where v represents the number of voting nodes and n represents the total number of nodes. K is the decision coefficient, which is generally 2, and in this embodiment it is 2. The sum of the number of voting nodes minus the sum of the total number of nodes divided by the decision coefficient is used. If equation (1-1) is greater than 0, the election is considered successful; otherwise, it is unsuccessful. The leader node packages the message frame according to the log ID using the encoding module and notifies the client of the successful submission in the network. After receiving the message, the client executes the code on the CPU to complete the application operation. Specifically, it calculates the address of the log ID in memory, reads it, and then applies it to the RAFT application layer. At this point, a consensus operation is completed.

[0079] When a node in the network encounters a failure, or goes offline due to physical power outages, network latency, or other reasons, the RAFT network may experience a "split-brain" problem. This means that the leader node's failure results in a leaderless network, while the remaining nodes complete the election process normally. However, at some point after the election, when the old leader node recovers from its failure and rejoins the network, the problem occurs: two leader nodes exist simultaneously in the network.

[0080] At this point, the old leader node will send a heartbeat signal according to its internal timer. The heartbeat signal is a synchronization message frame without log data; its log data is empty, and everything else is the same as the synchronization request message frame. When other followers receive this node, after the decoder unpacks and parses it, the control module compares its Term count and finds that its Term count lags behind the current node's Term count, so it will reject the node's message. The old leader node will then receive a message frame from the new leader in the network after a certain period of time. After parsing and unpacking it using its own decoder, the control module will find that its Term and Index are both higher than the old leader node's. At this time, the node's state machine will receive a jump instruction calculated by the control module, and the leader node will fall to the follower node, with its Term count matching that of the new leader. Because the Index difference may be greater than the standard, the determination formula is as follows:

[0081] (2-1)f1=T m -T n

[0082] (2-2)f2=f1-K

[0083] T m T is the index number in the new message. nLet f1 be the index of the current node. When equation (2-1) is greater than 0, the old leader node will reject the current data frame and send the corresponding return message frame to the network through the encoding module. Equation (2-2) represents the value of the index that the leader node resynchronizes after a synchronization failure. Here, f1 is the difference between the index of the message node and the current node, which is equation (2-1), and K represents the difference coefficient. In this embodiment, it is taken as 3. Then, after each synchronization failure, the new leader node can resynchronize by calculating the index through (2-2), which can complete the synchronization more efficiently. The new leader node will schedule log data from multiple memory modules at once through the encoding module and control module, and package multiple commit message frames to help the node reconnecting to the network complete the synchronization operation. There is no need to try by decrementing the index by one, which avoids the bandwidth waste of invalid data.

[0084] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A RAFT consensus algorithm acceleration system, characterized in that, The application relates to a bus bridge system for a RAFT algorithm acceleration module, which comprises a CPU, a bus bridge system, a network communication module, a RAFT algorithm acceleration module, a memory and a network interface. The CPU is connected with the bus bridge system and is used for completing control of the acceleration system, scheduling data into the RAFT algorithm acceleration module, converting out message data conforming to a message frame format and completing software operation of an application layer. The bus bridge system is combined by multiple buses and is connected with the network communication module, the RAFT algorithm acceleration module and the memory respectively, is used for converting data according to different data frame formats. The network communication module is connected with the network interface and is used for communicating with the RAFT algorithm acceleration module. The RAFT algorithm acceleration module is connected with the bus bridge system, the network communication module and the memory respectively and is used for maintaining a node, performing voting and initiating an election operation through the network communication module and completing acceleration of a RAFT consensus. The memory is composed of a high-speed storage array. The CPU is further used for executing a driver, controlling the RAFT algorithm acceleration module to create a node and configure an initial state. 2.The RAFT consensus algorithm acceleration system of claim 1, wherein, The network communication module is further used for packing and sending network protocol of a message needing to be sent on a network and processed by the RAFT algorithm acceleration module. 3.The RAFT consensus algorithm acceleration system of claim 1, wherein, The RAFT algorithm acceleration module comprises a node state machine, an election processing circuit, a decoding circuit, an encoding circuit, a timer circuit and a function register module. 4.The RAFT consensus algorithm acceleration system of claim 1, wherein, The node state machine is used for maintaining a node state. The election processing circuit is used for processing an election message in the RAFT consensus. The decoding circuit is used for decoding a RAFT consensus algorithm message. The encoding circuit is used for encoding a RAFT consensus algorithm message. The timer circuit is used for configuring an initial value, clock frequency division function and interrupt pulse signal generation function. The function register module is used for converting a software register read-write instruction into a hardware signal. The node state machine configures initial registers and creates a node in an idle state. 5.The RAFT consensus algorithm acceleration system of claim 4, wherein, The election processing circuit starts countdown from an initial value of a built-in timer of each node in a network, decreases by 1 in each clock cycle, and if a heartbeat signal is not received continuously, the node with the timer of 0 enters a candidate state and initiates an election. 6.The RAFT consensus algorithm acceleration system of claim 4, wherein, The decoding circuit is further used for defining a message frame format, and the message frame format comprises a message header data frame and a message data frame. 7.The RAFT consensus algorithm acceleration system according to claim 4, wherein, The message header data frame comprises data type, data source, log ID number and return type. The message data frame comprises term number, index number and voting information. The message header data frame and the message data frame are both 128 bits in length. The timer circuit is further used for decreasing according to a clock signal and emitting a pulse signal when decreasing to 0. 8.The RAFT consensus algorithm acceleration system of claim 4, wherein, ​

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