Efficiely transmittable bit sequences with restricted difference and

Abstract

The invention relates to a method for generating an efficiently transmittable bit sequence with a limited degree of discrepancy and a limited run length. The proposed method allows a particularly efficient transmission of data over a transmission channel. Compared with the prior art, one of the advantages of the invention is that the physical behavior on the transmission channel can be certainly controlled all the time although the resource demand is reduced. Thus, according to the proposed method, bit errors are few, and transmit errors can be corrected efficiently (i.e., with little technical effort). Furthermore, the encoder used is designed to have a minimum number of gates, and interlacing is implied in the proposed method, which ensures that so-called burst errors can be particularly advantageously corrected.

Description

[0001] The invention relates to a method for generating efficiently transmittable bit sequences with limited disparity and limited run length. The proposed method allows to transmit data through a transmission channel particularly efficiently. One of the advantages of the invention over the prior art is that although the resource requirements are reduced, the physical behavior on the transmission channel can always be controlled deterministically. Thus, according to the proposed method, bit errors are rare and transmission errors can be corrected efficiently, i.e. with little technical effort. In addition, the encoder used is designed with a minimum number of gates and implicit interleaving is implied in the proposed method, based on the fact that so-called burst errors can be corrected particularly advantageously. This implicit interleaving makes it possible to dispense with the conventional buffer memory required for explicit interleaving. In addition, the invention ensures that user data can be advantageously encoded with correction metadata for transmission. According to the invention, not only the user data, but also the correction data can be ensured to be line encoded or line coded. The optimized disparity is a quality feature of the data transmissibility. An unfavorable disparity can mean that the data cannot be transmitted properly through the data channel, because the recipient cannot interpret the data properly. Another quality feature is the data efficiency in terms of the ratio of the amount of user data transmitted to additional data that is not directly related to the content of the user data. This includes so-called header data. The invention makes it possible to generate data streams that can be read out particularly efficiently and are also very efficient in terms of overhead data. This minimizes the so-called user data overhead, which in turn results in a particularly efficient process. The explicit interpretability on the receiver side also ensures that the data does not have to be transmitted repeatedly, but can be read out on the receiver side with a high degree of fault tolerance. In addition, the proposed method is particularly efficient, because the data segments can be converted to or consist of sub-symbols in parallel, while this parallel design only requires units that are easy to produce technically. The efficiency gain is therefore also related to the hardware or runtime used. The invention further relates to a correspondingly configured system arrangement, as well as a computer program product and a memory readable medium with control commands for carrying out the method.

[0002] EP 3323219 A1 shows a method that makes it possible to read out an analog data stream through a data line in a particularly error-proof manner. Among other things, the amplitude of the signal is monitored and, particularly preferably, the signal is measured at the point at which the amplitude is at its maximum. This converts the analog data stream into a digital data set and the maximum amplitude ensures that it is safely below or above the threshold between 0 and 1 on the line.

[0003] Various encoding methods and data transmission methods are known from the prior art, but all of these methods are related to application scenarios in which the use in a car can only bring about disadvantages. For example, the prior art generally assumes that high computing power is available and that there are no high real-time requirements. In addition, the prior art generally assumes that the weight or reliability of the components to be used plays a minor role. The prior art generally refers to conventional computer networks in which reliability and low technical complexity are less important.

[0004] Furthermore, so-called forward error correction is known from the prior art. Forward error correction (FEC) is an error correction method that adds additional redundant information to the data. This redundancy allows the receiver to detect and correct errors without having to resend the packet. FEC is often used for high-speed Ethernet connections, such as 10 gigabit Ethernet (10 GbE), to ensure data integrity.

[0005] On the basis of this prior art, there is a need to create a method or system arrangement that enables data to be processed as quickly as possible due to the safety requirements in a car, while also requiring little technical effort and minimizing the error rate during transmission, since a resend is not possible in the event of an error. Low technical effort consists of installing components that are as simple as possible, have low weight and can also be produced in large quantities in a cost-effective manner. Here, methods and system arrangements known from computer network technology cannot generally be used, since weight savings and real-time behavior are not decisive for stand-alone PCs or servers. Although the heat to be dissipated generally poses a challenge for computer arrangements, energy efficiency is more important for a car, since, for example, in an electric car, the power consumption can even affect the car's range.

[0006] More advanced technologies relate to data transmission in serial data streams. For example, the prior art allows detailed description data to be transmitted together with the user data, which indicates where the user data is located and how the user data is to be interpreted. In addition, it is known from the prior art to discard individual data packets if they are not transmitted correctly. It is also known from the prior art to resend data packets if they do not arrive at the sender on time or in the unexpected format.

[0007] When data is transmitted serially, there must be as many 1s and 0s as possible in the serial data stream. This is called disparity. In order to avoid baseline drift during transmission, a disparity that averages zero and is also zero over a short period of time is desirable. Baseline drift (DC voltage fluctuations) of the serial signal leads to bit errors. In extreme cases, transmission is not possible.

[0008] In order to be able to reliably recover the serial bits in the serial data stream at the receiving end without having to send a clock, a minimum number of 0->1 or 1->0 transitions is required. This means that the clock for recovering the serial data is generated from the serial data stream locally at the receiver. The so-called run length specifies the number of bits that occur consecutively without changing, either 1 or 0. Short run lengths are always desirable, since long run lengths no longer allow the clock to be reliably recovered from the serial data stream.

[0009] Now, the task of the line code, in this case the block code, is to generate symbols from any data word with any degree of disparity and infinite run length, which have a guaranteed degree of disparity and a guaranteed run length. This causes an overhead in the transmission. This means that more bits (in the form of symbols) have to be transmitted than would occur in the net data word to be transmitted. This means that the required transmission speed (bandwidth) has to be greater than the data rate of the data to be transmitted. This in turn means that the system has to tolerate a higher error rate or needs more effort, power, etc. than would be required to transmit the original data.

[0010] The prior art has a high overhead (8B10B) or the quality of the encoded signal in terms of disparity and run length is very poor, so that additional measures (complexity) such as scramblers usually have to be taken to improve the quality in terms of disparity or run length.

[0011] It is therefore an object of the present application to produce a method which generates a bit sequence that can be transmitted particularly efficiently and which can also be transmitted safely. In this context, "efficiently" can mean hardware efficiency, efficient decryption on the receiver side, no need for redundant data transmission due to uninterpretable signals, and / or a ratio of user data to overhead data. Furthermore, according to the present application, it should be possible to produce or use particularly efficient hardware which achieves runtime optimization through parallel processing. Furthermore, it is an object to provide a correspondingly equipped system arrangement, as well as a computer program product and a memory readable medium with control commands for executing the method or operating the system arrangement.

[0012] The features of claim 1 solve this problem. Further advantageous embodiments are given in the subclaims.

[0013] Thus, a method for generating an efficiently transmittable bit sequence with limited Hamming distance, limited run length and line coding for forward error correction in a car is proposed, the method comprising: providing an arbitrary bit sequence; segmenting the provided bit sequence into a sequence of predefined segments according to a respective predefined bit length; calculating a forward error correction for each segment or a plurality of segments of the same bit length; encoding each segment or a plurality of segments of the same bit position with its forward error correction into one or more sub-symbols, respectively, using the same encoding unit of a plurality of encoding units for the segments of the same bit position and the associated forward error correction, wherein a first subset of encoding units actively controls the sign of the Hamming distance of the generated sub-symbols by inverting the Hamming distance of the sub-symbols to compensate for the Hamming distance of a second subset of encoding units, wherein concatenation of the sub-symbols results in the efficiently transmittable bit sequence together with the calculated forward error correction.

[0014] In the preparation process step, a potentially infinite bit stream comprising an arbitrary bit sequence can be provided. Depending on the application scenario, the data stream already has any length and, in turn, can be divided into words or any bit sequence. This provides that an output data stream can be generated with a bit sequence potentially having any length. However, this arbitrary length can be limited in the preparation process step and preferably can be limited to 112 bits. According to one aspect of the present invention, the length or bit length of the arbitrary bit sequence is fixed as soon as it is limited. In this respect, the arbitrary length of a bit sequence in the sense of the present invention cannot be understood as arbitrary. Rather, the synonym for an arbitrary bit sequence according to the present invention can be a bit sequence whose length can be freely chosen in advance and / or whose content corresponds to data to be transmitted or at least a part of data to be transmitted.

[0015] Thus, in the preparation process step, an output data stream comprising an arbitrary bit sequence can be provided. Then, in the first step method, this arbitrary bit sequence is read from the output data stream and provided.

[0016] Generally, the output data stream or the output bit sequence can have too many bits so that the process is carried out iteratively in a way that several arbitrary bit sequences are generated from the output bit sequence, segmented, converted into sub-symbols, optimized with respect to the Hamming distance and then transmitted. This means that the output bit sequence can also have any length and finally can be transmitted in several complete symbols.

[0017] There are multiple encoding units, whereby an encoding unit is assigned to each segment, which in turn corresponds to a part of an arbitrary bit sequence or a previously freely selectable bit sequence. This converts the segments into partial symbols, whereby the set of concatenated partial symbols corresponds to a symbol or a complete symbol of a bit sequence to be transmitted efficiently. Thus, according to one aspect of the application, the encoding units are located in the logical path of the processing chain or the structural arrangement between the segments and the partial symbols.

[0018] The proposed method is particularly efficient compared to the prior art, since the transmittable bit sequence has a particularly high degree of useful data. For example, 128 bits can be transmitted, of which 112 bits have user data. Thus, the proposed method is already superior to the prior art in this respect. Furthermore, the creation of the transmittable bit sequence is particularly efficient, since this can be carried out in parallel and, for this purpose, the encoding units can be designed particularly simply. In this context, "simple" means, for example, that only very few circuits have to be installed in the encoding units. The encoding units do not necessarily have to have complex logic and can even be optimized for a specific bit number. Thus, according to the application, the input and output of the respective encoding units can be fixed in terms of the bit number.

[0019] Due to the optimized degree of disparity of the bit sequence to be transmitted, errors can be avoided when interpreting on a serial channel. Thus, the efficiency also relates to the fact that the bit sequence has a particularly strong error resistance, so that it can only be transmitted reliably once. Due to the high detectability, which is in turn due to the optimized degree of disparity, redundant transmissions are avoided.

[0020] In serial data transmission, it is advantageous to keep the number of ones and zeros in the serial data stream as equal as possible. This is generally referred to as the degree of disparity. In order to reliably recover the clock at the receiver, a run length limit can be imposed on the generated channel sequence. This limits the maximum number of consecutive ones and zeros. Thus, the proposed method can also be described as a method for efficient encoding of a bit sequence. According to the application, the degree of disparity is optimized by cleverly setting the partial degree of disparity. This can be particularly advantageously used in the case of a limited run length of the bit sequence. The limited degree of disparity and the limited run length can also relate to an arbitrary bit sequence provided. This means that it does not have to be a highly transmittable bit sequence. Overall, an arbitrary bit sequence provided can be transmitted efficiently, or a bit sequence to be transmitted is generated or created from this bit sequence, which can then be transmitted efficiently.

[0021] In a preparation process step, an arbitrary bit sequence is provided which line-encodes user data. Problems can occur in this arbitrary bit sequence, for example, if there is an unfavorable degree of variance. For example, too many 0s can lead to problems during transmission. To avoid this, and thus, in a further process step, the arbitrary bit sequence is optimized so that it can now be transmitted efficiently. The arbitrary bit sequence provided thus represents any user data to be transmitted from a transmitter to a receiver via a serial data channel. The arbitrary bit sequence can be, for example, control data in a car.

[0022] According to the invention, the provided bit sequence is segmented into a predefined sequence of segments according to a predefined bit length. This means that the input data stream, i.e. the arbitrary bit sequence, is divided according to a predefined procedure, thereby creating separate data segments. These segments cumulatively thus result in the arbitrary bit sequence. The predefined bit length has the advantage that the encoding units can be optimized in a corresponding identical bit length manner. This makes it possible to produce a highly specialized, particularly efficient circuit. Defined bit lengths are mentioned below, but these are merely examples.

[0023] Each segment is encoded into a sub-symbol using one of a plurality of encoding units. The encoding itself takes place in an encoding unit, which finds a segment at the input and then converts this segment into a partial symbol. The partial symbol is also a bit sequence. Overall, the arbitrary bit sequence is thus divided into segments, which are each converted into a sub-symbol by an encoding unit, and the sub-symbols overall produce the encoding of the arbitrary bit sequence to be transmitted. Overall, it is advantageous if the number of segments corresponds to the number of encoding units and thus to the number of partial symbols. Each segment can thus have exactly one encoding unit, which in turn generates exactly one partial symbol from the segment. The number of encoding units describes all the encoding units to be used, which corresponds to the number of segments. The number of segments is predefined because the predefined bit length is specified. The method is thus overall deterministic.

[0024] To achieve an overall advantageous variance, there is a first subset of encoding units that actively control the variance of the sub-signals by inverting the variance of the generated sub-signals to compensate for the variance of the second subset of encoding units. This means, therefore, that there are subsets of encoding units that do or do not control the variance. The encoding units in the first subset control this variance, while the encoding units in the second subset do not control this variance. The encoding units in the first subset can therefore be described as active, while the encoding units in the second subset can be described as passive. Due to the different subsets or types of encoding units, the encoding units can be connected in series such that the encoding units in the first subset also advantageously shape the total variance of the partial variances from the encoding units of the second subset.

[0025] According to the application, therefore, the encoding units used are arbitrary with respect to the variance of the partial signals. The encoding units in the first subset can then be connected in parallel, whereby the variance of the previous encoding unit and its own encoding unit or the variance of its sub-signals is controlled by the variance of the encoding units in the second subset. In this way, a certain number of encoding units in the second subset is used first, and then another certain number of encoding units in the first subset is used. In this way, the type or subset of encoding units changes such that the next encoding unit connected in parallel adapts to the variance of the previous sub-signal and / or its own sub-signals. In this way, it is avoided to connect the uncontrolled encoding units one after the other in parallel, which leads to an unfavorable variance. Therefore, each encoding unit in the first subset corrects the sign of the previous encoding unit or its sub-signals. This parallel connection of encoding units is described in more detail below with reference to Figure 4 in more detail.

[0026] From the above, it can therefore be concluded that the encoding units in the first subset optimize the encoding units in the second subset with respect to the variance. Optimizing the variance means that the variance is 0. How the skilled person calculates or sets the variance (for example, by changing the sign) is well known to the skilled person.

[0027] According to the proposed method, sub-signals are therefore generated that are optimized with respect to the variance in their sequence. Since each segment is converted into a sub-signal, the (complete) signal to be transmitted can be generated by concatenating these sub-signals. Since the variance or partial variances are optimized, the signal can be transmitted in a particularly efficient or fault-tolerant manner. This results in a particularly advantageous sequence of bits to be transmitted.

[0028] According to an aspect of the application, the bit sequences are not limited in their difference and run length. This has the advantage that any amount of user data can be transmitted or any amount of user data can be converted into bit sequences which are limited in terms of difference and limited in terms of run length. Thus, any bit sequence is encoded into a bit sequence to be transmitted which is optimized in terms of difference and run length.

[0029] According to a further aspect of the application, the difference of the second subset of encoding units is not controllable. This has the advantage that any sub-symbol can be generated using the encoding units of the second subset, wherein particularly simple encoding units will be used. These encoding units can be designed to be particularly simple because the generated partial symbols are not limited in terms of difference or run length.

[0030] According to a further aspect of the application, the active control of the symbol is carried out by means of a conditional inversion of the partial symbols. This has the advantage that the corresponding sub-symbol of the encoding units of the first subset can be controlled in a simple manner. It is only necessary to invert the difference of the partial symbols or individual bits. The symbol refers to the difference of the partial symbols, which can be positive or negative.

[0031] According to a further aspect of the application, the conditional inversion takes place in dependence on the difference of the complete symbol formed by all partial symbols. This has the advantage that not only the partial symbols are optimized, but also the entire symbol, i.e. the combined partial symbols, i.e. the complete symbol is optimized in terms of difference. This results in particularly advantageous complete symbols.

[0032] According to a further aspect of the application, the dependency is influenced in such a way that the magnitude value of the difference is minimized. This has the advantage that as low a difference as possible, preferably 0, is achieved. Thus, the differences are related to each other in such a way that the amount of difference is as low as possible or as low as possible.

[0033] According to a further aspect of the application, the amount value is minimized in such a way that a positive complete symbol difference is cancelled by a negative parity of the sub-symbols. This has the advantage that the positive complete symbol difference is minimized or eliminated.

[0034] According to a further aspect of the application, the magnitude value is minimized in such a way that a negative complete symbol difference is cancelled by a positive parity of the sub-symbols. This has the advantage that the complete symbol difference is minimized or eliminated in general.

[0035] According to a further aspect of the application, the active control takes place in dependence on the complete symbols that have already been transmitted, such that the difference degree of all complete symbols is minimized. This has the advantage that several complete symbols can be minimized with respect to their difference degree, or the difference degree is eliminated, and thus, the several complete symbol sequences are optimized with respect to their transmissibility.

[0036] According to a further aspect of the application, the encoding unit in the first subset encodes a fragment of 11 bits as a sub-symbol of 13 bits. This has the advantage that a line coding of 11 bits can be carried out particularly efficiently, with only 2 bits of additional effort for this. This is particularly advantageous if a complete symbol of 128 bits is to be created. In general, the specific values mentioned here for the proposed technical teaching are determined empirically and can be justified by the fact that only 128 to 112 bits, i.e. 14%, of additional effort are required. The values listed here are thus justified for the transmission of 112 bits.

[0037] According to a further aspect of the application, the encoding unit in the first subset has a difference degree of between +3 and +9, which is specifically inverted to -3 to -9 by inversion. This has the advantage that a difference degree of +3 is offset, for example, by a difference degree of -3, which is similarly carried out when a difference degree of +9 is adjusted by a difference degree of -9. This in turn is particularly advantageous for any bit sequence of 112 bits that is to be encoded as 128 bits.

[0038] According to a further aspect of the application, the run length in the sub-symbol is at most 7. This has the advantage that at most 7 identical instances of 0 and 1 are generated, which is particularly advantageous in the proposed 112-bit or 128-bit scenario.

[0039] According to a further aspect of the application, the run length of the sub-symbol of the encoding unit in the first subset is at most 5, starting from the most significant bit and / or the least significant bit. This has the advantage that at most 5 identical bits can be present at the end or at the beginning of the sub-symbol. This is also proven to be particularly advantageous in the scenario described.

[0040] According to a further aspect of the application, in the encoding unit in the second subset, a fragment of 11 bits is encoded as a sub-symbol of 12 bits, or a fragment of 7 bits is encoded as a sub-symbol of 8 bits, or a fragment of 6 bits is encoded as a sub-symbol of 8 bits. This has the advantage that in the scenario of transmitting 112 bits in a symbol of 128 bits, this encoding can produce particularly advantageous values, which have a minimized overhead of only 14%.

[0041] According to a further aspect of the application, for the encoding unit in the second subset, a difference degree of between -2 and +2 is generated. This has the advantage that particularly advantageous difference degrees are generated again.

[0042] According to a further aspect of the application, in the coding units of the second subset the run length of the generated sub-symbols is 6. This has the advantage that particularly optimized sub-symbols can be generated again.

[0043] According to a further aspect of the application, the coding units of the second subset generate partial symbols with a maximum run length of 3 at the edges. This has the advantage that the partial symbols created by the second subset of coding units have a maximum run length of 3 at the beginning or end, which is a particularly advantageous value.

[0044] According to a further aspect of the application, the coding units are addressed in parallel and in each case encode one segment as a partial symbol. This has the advantage that a piece of text is converted into one complete partial symbol with only one coding unit. The coding units can therefore be addressed in parallel, since the segments are formed by arbitrary bit sequences and can be converted into partial symbols in parallel.

[0045] According to a further aspect of the application, the coding units are addressed in the sequence 21212221212, wherein 1 represents a coding unit of the first subset and 2 represents a coding unit of the second subset. This has the advantage that a certain number of non-actively controlled coding units is always followed by an actively controllable single coding unit. In this respect, it has been empirically determined that the proposed coding units produce particularly advantageous complete symbols.

[0046] According to a further aspect of the application, when positive and negative data streams are applied, the multiplexer selects the data stream which contributes to minimizing the total difference degree of the complete symbol. This has the advantage that a suitable data stream can be selected, the symbols of which minimize or cancel the difference degree. For example, if the difference degree to be optimized is negative, a data stream with a positive difference degree is selected, which is then minimized or compensated with respect to the difference degree of this data stream.

[0047] According to the invention, the forward error correction is improved by calculating the forward error correction in relation to the user data and for this purpose, the user data is first segmented. Then, a separate forward error correction is calculated for each segment, so that the forward error correction is not for the entire data word, but for different partial words. This keeps the number of gates of the FEC encoder to be used low and avoids exponential growth. In addition, an improvement results from the fact that according to the invention, the line coding is carried out by the user data together with the forward error correction, thus overcoming the disadvantage in the prior art of transmitting the forward error correction in uncoded form. Furthermore, it is advantageous that the error correction can work more efficiently, since the error correction is only for partial words and thus can identify the location where an error has occurred with fine granularity. Conventional error correction methods always work on the entire data word and are therefore inefficient, or errors can occur in the prior art that cannot be corrected. This is avoided by the segmentation according to the invention.

[0048] A further improvement is that all transmitted data is line coded and thus all data can benefit from the line coding. Thus, a deterministic control of the transmission link is possible and the number of bit errors is kept low. In addition, an implicit interleaving results from the fact that smaller packets are transmitted and thus an implicit interleaving occurs, since not all data words are transmitted. This is achieved by using several forward error correction encoders, each of which only works on partial words. Thus, according to the invention, the disadvantage in the prior art that a lot of costs have to be spent to create an explicit interleaving, which would also require additional buffer memory, is overcome.

[0049] Due to the optimized difference of the bit sequence to be transmitted (line coding), errors can be avoided when interpreting on a serial channel. Thus, the efficiency also relates to the fact that the bit sequence has a particularly strong error resistance, so that it can only be transmitted reliably once. Due to the high detectability (which is in turn due to the optimized difference), a redundant transmission is avoided.

[0050] In serial data transmission, it is advantageous to keep the number of ones and zeros in the serial data stream as equal as possible. This is generally referred to as the difference. In order to reliably recover the clock at the receiver, a run length limit can be imposed on the generated channel sequence. This limits the maximum number of consecutive ones and zeros. Thus, the proposed method can also be described as a method for efficient encoding of a bit sequence. According to the invention, the difference is optimized by cleverly setting the partial differences. This can be particularly advantageously used in the case of a limited run length of the bit sequence. The limited difference and the limited run length can also relate to an arbitrary bit sequence provided. This means that it does not have to be an efficiently transmittable bit sequence. Overall, an arbitrary bit sequence provided can be efficiently transmitted, or a bit sequence to be transmitted is generated or created from this bit sequence, which can then be efficiently transmitted.

[0051] The proposed method can be used in particular in vehicles or be specifically tailored to the requirements in vehicles. This is the case because safety-critical functions are provided in vehicles, which must be protected accordingly. According to the application, this takes place in several ways. On the one hand, by forward error correction and by line encoding. In addition, the reduction in the number of gates required is particularly advantageous in electric vehicles.

[0052] According to the application, user data to be transmitted is provided in a preparation process step. The user data to be transmitted is usually a sequence of bits having a fixed length. This can also be referred to as a data word.

[0053] The provided user data is then divided into several sequences of bits having the same length. In a preferred embodiment, these sequences of bits can have a length of 112 bits. Although the user data can be a continuous data stream, the sequences of bits always have a certain length, and the subdivision of the user data is provided in a certain way. In the following, the sequences of bits are also referred to as data words. Furthermore, in the following, in particular in the figures, it is assumed symbolically that the sequences of bits are arranged above one another. This means that each individual sequence of bits is horizontally extended, and the individual sequences of bits are arranged above one another in the vertical direction.

[0054] Since the sequences of bits are now segmented, a read-out subdivision rule is read out, which divides the sequences of bits into a sequence of segments having a predefined length at predefined positions. The subdivision rule can take the form of a data format which defines how long the segments must be. The individual segments must have the same length; the lengths between the segments can vary. However, the subdivision rule provides that the individual sequences of bits each have the same format, so that symbolically the same subdivision result is produced in the vertical direction. For example, the first segment of each sequence of bits can have 11 bits. For example, the first four segments can each also have 11 bits, followed by a segment having 7 bits. This can be followed by another segment having 11 bits, then by a segment having 6 bits. This data format is maintained for all sequences of bits. This means that the segments at the same position can always have the same length, although symbolically the segments can vary in the vertical direction. The segments of each row then form a sequence of bits. The sequences of bits form the user data as a whole in their vertical arrangement.

[0055] This means that the read-out subdivision rule is applied to all of the sequences of bits, until the entire user data is broken down horizontally into sequences of bits and segments are formed in the vertical direction. This means that all sequences of bits are subdivided according to the same subdivision rule. The subdivision rule can be read from a data store and applies to all sequences of bits obtained from the user data.

[0056] Now, partial forward error correction is iteratively created across all bit sequences for all segments at the same bit position. Therefore, symbolically speaking, forward error correction is calculated for all segments at the same bit position or for all vertical segments in the same sequence. Performing this operation for all segments results in partial forward error correction being created for all bit sequences and thus for the complete user data. Therefore, all partial forward error corrections collectively produce a total forward error correction for the complete user data or all bit sequences.

[0057] Generally, there is another possibility: the user data is only divided into a bit sequence, or the user data is already available as a bit sequence in its length. Then, partial forward error correction is generated for each segment.

[0058] Now, a segment encoder is iteratively applied to all segments at the same bit position to generate segment line codes for all segments at each bit position and for each bit sequence. In other words, symbolically speaking, line encoding is performed on all vertical segments. The advantage of doing this is that a line encoder is specifically provided for a predetermined length. This ensures that each vertical segment can be line-coded by a single line encoder. Therefore, iteratively applying the segment encoder ensures (symbolically speaking) line encoding of segments column by column, and iteratively applying the segment encoder across all segments until all bit sequences are line-coded relative to their segments.

[0059] A particular advantage is that the partial forward error correction has the same number as the corresponding segment. This means that the partial forward error correction can be line-encoded using the same line encoder as the corresponding segment.

[0060] The corresponding partial forward error correction is applied using the same segment encoder used relative to the segment in which it was created, to generate a partial forward error correction line code for each partial forward error correction. This means using the same segment encoders that line-encode the corresponding segment and then also line-encode the corresponding partial forward error correction. This implies using the same segment encoder as the partial forward error correction associated with the corresponding column to line-encode these segments column by column.

[0061] Then, send all fragment line codes and all part forward error correction line codes.

[0062] According to one aspect of the application, the subdivision rules are stored in a data memory and are present as coding rules and / or are read out from the hardware architecture. This has the advantage that the subdivision rules can be statically predefined or can also be changed in the data memory. In addition, the subdivision rules can also take the corresponding hardware architecture into account. For example, if different encoders are provided for different bit lengths, the bit sequences can be subdivided such that the corresponding segments correspond to the respective encoders. These segments thus have exactly the length provided by the respective encoder.

[0063] According to another aspect of the application, all bit sequences have the same structure in their data format, have the same segment length, and / or have the same bit position. This has the advantage that individual segments can be fed to the respective encoder. For example, each first segment of each bit sequence is fed to the same encoder. Thus, figuratively speaking, these segments can be line-encoded column by column and there is a dedicated encoder for each column.

[0064] According to another aspect of the application, the partial forward error correction has correction information which describes the target content of the segment for which the partial forward error correction was created. This has the advantage that the transmitted data can be corrected by means of this correction data, wherein not an entire correction is formed for each bit sequence, but rather individual partial forward error corrections are formed for individual segments. All partial forward error corrections describe all segments of all bit sequences and thus all user data as a whole. However, the difference here to the prior art is that not a forward error correction is formed for each bit sequence, but rather a forward error correction is formed for all segments across all bit sequences. Thus, the same line encoder for the corresponding segment can be used for each partial forward error correction.

[0065] According to another aspect of the application, the partial forward error correction has the same bit length as the segment for which the partial forward error correction was generated. This has the advantage that a dedicated line encoder can be provided, which achieves maximum efficiency, since the corresponding columnar line encoders are designed specifically for the bit length which they then have to encode. This results in a highly efficient and technically least complex process.

[0066] According to another aspect of the application, the partial forward error correction describes all user data to be transmitted in a correctable manner as a whole. This has the advantage that all transmitted user data can be corrected with respect to errors of all transmitted user data, but in this case individual segments can be taken into account, so that the proposed method is more fine-grained than that provided by the prior art.

[0067] According to another aspect of the invention, each segment encoder generates at least a portion of the line code. This has the advantage that the outputs of the segment encoders can be combined to provide the line code to be transmitted.

[0068] According to another aspect of the invention, the set of segment encoders encodes a 112-bit bit sequence into a 128-bit word. This has the advantage of creating particularly efficient line codes.

[0069] According to another aspect of the invention, a portion of the forward error correction line code is appended to the segment line code during transmission. This has the advantage that all data to be transmitted is line-coded, thus allowing for deterministic line operation, or that the advantages of line coding can be applied to all data, not just the payload data itself.

[0070] According to another aspect of the invention, the bit position is specified as an offset or as a bit index in the bit sequence. This has the advantage that different addressing types can be used, and the index is based on the order of the corresponding segments, the sequence of which can then be advantageously specified using known methods.

[0071] According to another aspect of the invention, user data can be obtained as a serial data stream. This has the advantage that any amount of user data can theoretically be sent, and then these data can be divided into bit sequences of equal length.

[0072] According to another aspect of the invention, the method steps are performed in the described order and / or iteratively. This has the advantage that the encoding order is reversed. According to the invention, forward error correction is defined first, followed by line encoding. This does not preclude the possibility that individual process steps must be performed multiple times. This may occur, for example, when there are several bit sequences and they must be segmented.

[0073] According to one aspect of the invention, line code segments are generated for each data subblock and / or for each data subblock forward error correction. This has the advantage that, in particular, the forward error correction need not be transmitted in an unencoded form, but can also be line-coded. Therefore, the advantages of line coding apply not only to user data but also to forward error correction.

[0074] According to another aspect of the present application, the forward error correction for a data block consists of several partial forward error corrections of data subword blocks. This has the advantage that not the entire forward error correction is generated initially, but rather many individual partial forward error corrections, which together form the complete forward error correction. In this way, the number of gates of the FEC encoder required is kept to a minimum. Nonetheless, all data can be protected by means of the forward error correction, in addition, the data can also be transmitted in the form of line encoding together with the forward error correction FEC.

[0075] According to another aspect of the present application, the readout data structure and the selection of the forward error correction sub-encoder according to the respective bit length of the data subword. This has the advantage that the FEC encoder is precisely adapted to the fragment length or bit length of the subword. In this way, the number of gates can be minimized, so that the encoder only needs to create an encoding for small subwords and not for entire data words. Thus, each FEC encoder is precisely tailored to the bit length of the data subword to be encoded.

[0076] According to another aspect of the present application, the number of gates of the FEC partial encoders is selected according to the bit length of the data subword. This has the advantage compared to the prior art that the number of gates required in the FEC encoder is reduced, thus creating an efficient system arrangement or an efficient method, which is particularly advantageous in a car or vehicle. In this way, it is not necessary to provide any unnecessary gates. This results in a deterministic and minimal number of gates.

[0077] According to another aspect of the present application, the number of all gates of all encoders is selected such that the iterative execution of the method results in a linear increase of the number of gates with respect to the data word length. This has the advantage that the data format is considered to provide a minimal number of gates, or the data format can be selected such that only a linear increase of the number of gates is required. For example, in one embodiment, the maximum bit length can be 10 bits, 11 bits or 12 bits, which means that the number of gates or circuits required by the FEC encoder only increases linearly. Since the number of gates required increases exponentially for larger values, the present application produces the technical effect of minimizing power consumption or energy consumption, in turn reducing waste heat. In addition, the proposed method is particularly robust, which is particularly advantageous in a car, since safety-critical functions are provided in a car.

[0078] According to another aspect of the present application, each data word has 112 bits. This has the advantage that a word of 128 bits can be created with line encoding, which corresponds to a universal format. According to the present application, it has been shown that 112 bits can be particularly robustly encoded as 128 bits. This ensures that the transmission is subject to lossy or error-prone data channels.

[0079] According to another aspect of the application, the bit length of the data subword block forward error correction is chosen such that it corresponds to the bit length of the data subword. This has the advantage that the same encoder can be used for line encoding of the forward error correction and the data subword or segment, which is a line encoder, i.e. not an FEC encoder. Thus, the present application makes the technical contribution that not only the number of gates has to be provided at a minimum, but also the total number of encoders has to be minimized. Thus, the forward error correction can be line encoded with the same encoder as the actual segment of user data.

[0080] According to another aspect of the application, the data subword block forward error correction and the data subword block on which the data subword block forward error correction is based are line encoded using the same line encoder. This has the advantage that only a minimum number of line encodings has to be provided. Symbolically, almost all columns, i.e. all partial word blocks, are line encoded with the same segment encoder for each column together with the corresponding partial forward error correction.

[0081] According to another aspect of the application, the data structure is chosen depending on the bit length of the data word. This has the advantage that also different bit lengths can be handled dynamically at runtime, so that the same data format can be chosen for further data words as for the first data word provided. If the first data word is available, the corresponding data structure can be used for further serial data streams and the further data words are structured such that they correspond to the data structure of the first received data word.

[0082] According to another aspect of the application, the serial line encoding is performed after the data subword block forward error correction has been calculated. This has the advantage that the order as provided in the prior art is reversed and the forward error correction is calculated first, which means that the forward error correction can also be line encoded without having to be sent unencrypted or unencoded.

[0083] According to another aspect of the application, the method steps are performed in a virtualized manner and information about the underlying encoders and / or gates is generated. This has the advantage that these implementations can be evaluated in the preparation process step and in this respect it can be determined how many gates or how many FEC encoders and / or line encoders are to be provided. Furthermore, the whole process can be simulated. The hardware components can be provided virtually.

[0084] One aspect of the invention is to pack several data streams (video, audio and data) in one transmission frame and to transmit these data streams serially. Different data formats not only have different bandwidth requirements, but also different latency, reassembly sublayer and error rate requirements. In particular, the transmission of today's video data formats not only requires the transmission of pure video data and its frame information, but also the support of encryption methods such as HDCP. All of this requires many different data channels, which have a wide range of requirements in terms of bandwidth, latency, reassembly sublayer, etc. In addition, it is desirable to obtain a network architecture that is much more complex than that provided by a simple transmitter / receiver architecture. An architecture with several repeaters (where the data path can start and end), branches (Y), and the possibility of re-integrating the data path into the link is advantageous.

[0085] According to one aspect of the invention, the technology follows the basic idea of packing services quite uniformly, but offers completely new possibilities with respect to the network architecture and allows new approaches to be taken to implement today's video interfaces. In addition, the technology can also be used as a general data transmission layer, for example, also for the transmission of Ethernet data or camera data or any kind of sensor data.

[0086] With the virtual paths, all packets / cells take the same path, which is different from IP, in which packets can take a different route to their destination than the preceding and subsequent packets. The latency and reassembly sublayer on the virtual path are therefore constant.

[0087] The virtual paths also have the advantage that they can be used as multiplexing branches for different services (video, audio, Ethernet), since the properties of the virtual paths can be configured in different ways so that different virtual paths do not interfere with each other.

[0088] The virtual paths only consume bandwidth when actual data is being transmitted.

[0089] The concept of virtual paths also makes it possible to use dedicated (virtual) data channels at runtime to implement complex and far-reaching diagnostic and network configuration functions.

[0090] According to one aspect of the invention, a virtual path layer is implemented between the physical layer (serializer and framer) and the various application data interfaces.

[0091] According to one aspect of the invention, the virtual path layer is used to multiplex different data paths and to support more complex architectures with repeaters and branches. This is mainly done in the cell layer.

[0092] According to an aspect of the application, another part of the virtual path layer is the application adaptation layer, which performs the conversion of video (stream) or e.g. Ethernet (packet) data into cells. This application adaptation layer also comprises OAM functions for network diagnosis and management.

[0093] According to an aspect of the application, the technology can be the basis for sending various data formats over serial links in cars (and elsewhere). It thus forms the basis for a new generation of devices.

[0094] The high serial bandwidth makes it necessary to define an architecture, cell format and interface that allow flexible internal data bus widths in order to adapt the speed of the internal timing system to the capabilities of the chip technology.

[0095] According to an aspect of the application, the virtual path layer is: a physical layer, which consists of a transmission sublayer and a physical medium sublayer; a cell layer; and an application adaptation layer, which contains a segmentation sublayer and a reassembly sublayer and functions for adapting the data format to the corresponding application.

[0096] The main task is to establish a physical connection with other physical layers. This connection is basically bidirectional. In principle, this connection can be implemented over a wide variety of media. In practice, two serial differential GBps connections are used. In this layer, line coding is performed, null cells are inserted to decouple the cell rate from the connection rate, and the cell stream is integrated into serial frames.

[0097] In the cell layer, the segmented data of the segmentation and reassembly sublayer above (cell payload data) are assembled into complete cells with a header, a VP identifier and a CRC, or the CRC of the cells is checked, and the payload is passed on to the segmentation and reassembly sublayer. This is also where the different cell streams of the application adaptation functions are multiplexed or the cell payloads are distributed to the application adaptation functions according to the VP identifier. (feed-in / feed-out)

[0098] According to an aspect of the application, the multiplexing and demultiplexing (forwarding) of the cell streams in the repeaters and splitters also takes place in the cell layer.

[0099] According to an aspect of the application, the task of the application adaptation functions is to adapt the data of the application interface to the format of the user data field of the cell and to send control information to the opposite side or to send control information from the opposite side to make it suitable for use (time generation, frame formation).

[0100] According to an aspect of the application, all virtual data paths are unidirectional, i.e. they start from an initiator and end at one or more targets. If the virtual data paths logically belong together (e.g. HDCP of a video channel) and thus form a bidirectional data path, these paths should have the same VP identifier.

[0101] The virtual data path starts at the initiator and ends at one or more targets. This is accomplished by

[0102] The cell sublayer implements and performs the following functions on the virtual path:

[0103] - Add / Delete Multiplexing

[0104] - VP Transformation

[0105] Streaming data (continuous data flow)

[0106] The streaming data function combines the time domain crossing with the bit width conversion of the data from the application interface to the N-bit cell rows. The cell row payload is already pre-formatted so that the cell header and trailer fit into the first and last cell row.

[0107] The streaming data is (usually) source synchronous. Here, the clock domain crossing of the data path from the application clock domain to the virtual path layer clock domain is performed.

[0108] In the transmit direction, a data buffer is provided into which the source synchronous data is written together with the source clock. The segmentation layer retrieves the data from this buffer as needed in order to perform the data format conversion to N-bit wide cell rows. Frame data (e.g. Hsync, Vsync, DE) is encoded in the payload information bits so that the frame can be reconstructed on the receiver side.

[0109] In the receive direction, the cell data from the reassembly sublayer is written into a data buffer with the cell row bit width (with cell row bit width). The frame information is reconstructed based on the payload information bits. The source clock is regenerated, for example, using buffer fill level and clock synthesis.

[0110] If data encryption (HDCP) is required, the cell data is encrypted or decrypted in this function.

[0111] Due to the different types of streaming data, such as: audio, video with encryption and video without encryption, this basic function can have different implementations (e.g. VStream In / Out; AStream In / Out; EncVStream In / Out).

[0112] For all functions, the interface of the segmentation and reassembly sublayer is the same.

[0113] Burst data (non-continuous data flow)

[0114] The burst data function combines clock domain crossing and data width conversion from the application interface to N-bit cell rows. The cell rows payload has been pre-formatted so that cell headers and trailers fit into the first and last cell rows.

[0115] The burst data is (usually) externally time synchronized and has different identification signals for direction and data type (address / data / ByteEnable).

[0116] This data is usually accompanied by control lines in order to implement a specific protocol.

[0117] In the transmit direction, a data buffer is provided into which the burst data is written together with the interface clock. The segmentation layer retrieves the data from this buffer as required in order to perform the data format conversion to N-bit wide cell rows.

[0118] In the receive direction, the cell data is written into a data buffer by the reassembly sub-layer, where the cell rows are bit wide. Interface control signals are reconstructed on the basis of the payload information bits.

[0119] The payload information bits are used to generate control signals for the application-specific interface or to synchronize a protocol state machine in the application-specific interface.

[0120] Due to the different interfaces providing burst data (SPI, I2C, MII), this basic function can have different implementations (e.g. SPI Burst, I2C Burst, MII Burst).

[0121] There will therefore also be (slightly) different stream input / output interfaces, but their structure should be identical.

[0122] The problem is also solved by a system arrangement for generating in a vehicle an efficiently transmittable bit sequence with a limited Hamming distance and a limited run length, the system arrangement comprising: an interface unit arranged for providing any bit sequence; a segmentation unit arranged for segmenting the provided bit sequence into a sequence of predefined segments according to a respective predefined bit length; a calculation unit arranged for calculating a forward error correction for each segment or a plurality of segments of the same bit length; an encoding device arranged for encoding each segment or a plurality of segments of the same bit position with its forward error correction into one or more partial symbols, respectively, using the same encoding unit of a plurality of encoding units for the segments of the same bit position and the associated forward error correction, respectively, wherein a first subset of encoding units actively controls the sign of the Hamming distance of the generated partial symbols by inverting the Hamming distance of the partial symbols to compensate the Hamming distance of a second subset of encoding units, wherein a concatenation of the partial symbols results in the efficiently transmittable bit sequence together with the calculated forward error correction.

[0123] The problem is also solved by a computer program product having control instructions for implementing the proposed method or operating the proposed apparatus.

[0124] According to the application, it is particularly advantageous that the method can be used to operate the proposed apparatus and units. Furthermore, the proposed apparatus and units are suitable for implementing the method according to the application. Thus, each apparatus implements structural features that are suitable for carrying out the corresponding method. However, the structural features can also be designed as method steps. The proposed method also provides steps for the functions of the structural features. In addition, physical components can also be provided virtually or virtualized.

[0125] Further advantages, features and details of the application are provided in the following description, in which aspects of the application are described in detail with reference to the drawings. The features mentioned in the claims and the specification are each of individual importance or in any combination. Likewise, the features mentioned above and those described further herein can be used individually or in any combination. Functionally similar or identical parts or components are sometimes provided with the same reference signs. The terms "left", "right", "top" and "bottom" used in the description of the embodiments refer to the orientation of the drawing in which the generally recognizable graphic signs or the generally recognizable reference signs are recognizable. The shown and described embodiments are not to be understood as conclusive, but have the exemplary nature of explaining the application. The detailed description provides information for the skilled person, so that known circuits, structures and methods are not shown or explained in detail in the specification in order not to hinder the understanding of the present specification. The drawings show:

[0126] Figure 1 : Several examples of process flow with serial line coding and calculation of forward error correction according to prior art;

[0127] Figure 2 : Optimized process flow with forward error correction and serial line coding according to one aspect of the invention;

[0128] Figure 3 : Encoding of user data and calculation of forward error correction according to prior art;

[0129] Figure 4 : Method for improving forward error correction in serial line coding in data transmission in vehicles according to the invention;

[0130] Figure 5 : Prior art encoding compared to method for improving forward error correction according to one aspect of the invention;

[0131] Figure 6 : Diagram illustrating the number of gates needed per bit length for forward error correction;

[0132] Figure 7A : Encoding of user data into a row code according to one aspect of the invention;

[0133] Figure 7B : Proposed system arrangement for improving forward error correction in serial line coding in data transmission in vehicles according to one aspect of the invention;

[0134] Figure 8A : Method for improving forward error correction at the transmitter side according to one aspect of the invention;

[0135] Figure 8B : Method for improving forward error correction at the receiver side according to one aspect of the invention;

[0136] Figure 9 : Flow chart of the method for improving forward error correction in serial line coding in data transmission according to one aspect of the invention;

[0137] Figure 10 : Application of the basic frame format and so-called block code according to one aspect of the invention;

[0138] Figure 11 : Schematic illustration of the layout and structure of the so-called block code according to another aspect of the invention;

[0139] Figure 12 : Schematic illustration of the frame format applicable according to the invention; and

[0140] Figure 13, Figure 14 , Figure 15 , Figure 16 : Exemplary encoding of data segments into symbols such that the degree of disparity is optimized according to an aspect of the present invention.

[0141] Some of the present drawings show the following parameters, which are well known to the person skilled in the art in English names, and which are used as parameters and thus cannot be translated.

[0142] Figure 1 Three examples of the way in which forward error correction is performed according to conventional methods are shown. On the left-hand side, an example is shown in which the user data is first line-encoded and then a forward error correction code FEC is generated. The line-encoded data is transmitted, and subsequently the forward error correction is line-encoded and then the encoded forward error correction is appended to the encoded user data. Thus, according to this example from the prior art, the forward error correction is generated by the complete data word, and then has to be line-encoded again and appended. Thus, the encoding is not carried out by separate segments, but by the entire bit sequence.

[0143] In the middle, another prior art example is shown in which the line encoding step of the forward error correction is omitted, and the unencoded parity information is appended. The disadvantage here is that the last data portion, i.e. the parity information, is not line-encoded and is thus very error-prone.

[0144] On the right-hand side, an example is shown which, in contrast to the example in the middle, does not send back the parity information for line encoding. This has the same disadvantage as the example in the middle.

[0145] With ever increasing data rates, the data transmission solutions always impose ever more stringent requirements on the error-free / fault-tolerant capability, which requires a fine adjustment between line encoding and forward error correction (FEC).

[0146] The current prior art (Ethernet / DisplayPort) processes the data stream in the following order:

[0147] 1. In a first step, the input data is line-encoded using line encoding (8b10b, 64b66b, 128b132b, etc.). For the larger encodings 64b66b and above, this is mainly achieved by scrambling using an LFSR.

[0148] 2. Now, the serial line encoded stream is additionally protected against bit errors by means of FEC (Forward Error Correction) encoding. The complete FEC encoding (FEC code word) contains both the input data based on symbols as well as so-called parity symbols. For these applications, the input data passes the FEC unaltered. This means that the input data always corresponds to the original serial code. Now the following additional procedures exist:

[0149] a. Now, the parity symbols are also serial line encoded (e.g. 8b10b) thereafter in order to fulfill the requirements of the serial transmission (run length, DC balance, etc.). This additional subsequent encoding of the parity symbols requires an additional encoder in the form of hardware.

[0150] b. Instead of the above-mentioned subsequent serial line encoding of the parity symbols, there also exists the solution to feedback the parity symbols to step 1.). With the serial line encoder, it is possible to control the DC balance based on the selection of positive or negative symbols. However, this is associated with a corresponding dead time (dead time depends on the size of the serial line encoder and the FEC encoder). This can lead to large deviations in the amount of temporary DC balance, for example.

[0151] c. The parity symbols are transmitted directly to the serial link (e.g. DisplayPort 2.0) without processing. However, this is very inaccurate because the parity symbols are generated based on the input data. Here, the fact that the parity symbols are on average DC balanced is relied upon.

[0152] All of the mentioned methods (a-c) have the following disadvantage: These methods require a large amount of resources (e.g. two serial line encoders) or lead to an inaccurate control of the serial line encoding (e.g. DC balance, run length, spectrum). In combination with the transmission channel, an inaccurate control of the serial line encoding can in particular lead to an incorrect reconstruction of the data stream at the receiver side (CDR sample error). These influences are mitigated in operation by the FEC (because it corrects bit / symbol errors), which unnecessarily deprives the FEC encoding of the correction margin for additional necessary error correction of errors caused by signal integrity or e.g. external influences with each error caused by bad serial line encoding. Reed Solomon FEC can only correct t symbol errors based on the size of the overhead in symbols (2t, see Figure 3 ).

[0153] On the other hand, Figure 2The method according to the application is shown, wherein forward error corrections are generated from the user data and then these forward error corrections are also line coded together with the user data. The advantage here is that both the user data and the forward error corrections are line coded, so that the error is robust. This figure also shows the difference to the prior art in that the forward error corrections are generated directly on the basis of the user data, not on the basis of the line coded user data. This makes it possible to send all data in line coded form, which in turn increases the error robustness.

[0154] The method presented below to improve the above problem applies to all conceivable ECC / FEC codes, not only to Reed Solomon codes.

[0155] The procedure presented changes the order of the line coding and the FEC:

[0156] 1. In a first step, the input data are protected by means of an FEC or a plurality of individual FEC units with a smaller symbol width (6 to 12 bits). This also results in an overall overhead of 2t.

[0157] Here, the use of several FEC sub-codes is particularly preferred, since this has (explained below) further positive properties.

[0158] 2. The respective current FEC output symbol (not to be confused with the entire FEC code word n) is then line coded using a block code, so that all desired properties, such as DC balance, run length, spectrum, etc., are maintained.

[0159] In the case of the multi-FEC coding in step 1), exactly the same number of block coders is used here. On the receiving side, this means that a bit error on the link that destroys a complete data symbol of the serial code only leads to a single FEC symbol error.

[0160] Figure 3A prior art flow chart is shown, in which the input data is line encoded and then a forward error correction is generated. This forward error correction is appended to the present right hand side, as shown at the bottom. This means that first the data words are line encoded at the top and then the non-line encoded forward error correction is appended. This now poses a problem, because the forward error correction does not have the properties required for robust data transmission. This leads to some disadvantages, because the data is not DC (digital current) balanced, i.e. no advantageous parity check is set. In addition, in the case of non-line encoded transmission, errors can occur during clock recovery. In general, the advantage of line encoding is that the average of the measurable analog signal is measured and then it is checked which actual signals are above this average and which are below this average. What is desired here is that the number of analog signals above the average, i.e. the digital "1", is equal to the number of analog signals below the average, i.e. the digital "0". This means that an optimized signal modeling can be carried out. This is not possible in the present Figure 3

[0161] Figure 4 A procedure according to the present application and a transmission over a lossy channel is shown. Here, there is potentially a loss per channel and it is particularly advantageous to first forward error encode the data input and then to carry out a full string line encoding. At the receiver side, the procedure is carried out in reverse and first a serial decoding is carried out, whereby in addition to the user data, the forward error correction is also recovered.

[0162] Figure 5 An upper example of a prior art method is shown, in which in a first method step, the output data words or bit sequence is line encoded from a first line to a second line. This results in a code which is longer than the output bit sequence, which is also referred to here as overhead. In a subsequent process step, a forward error correction code is generated from the second line to a third line and the forward error correction code is added to the line encoding. As can now be seen, the first part on the left of the data to be transmitted is line encoded, while the second part, i.e. the forward error correction, is not line encoded. This poses a problem, because in the appendix on the right hand side, the advantages of line encoding must be abandoned. This is disadvantageous.

[0163] ​In the middle embodiment example of this figure, the source word ABC is again shown at the top. Thus, the bit sequence consists of the segments A, B and C. In the present case, these segments have a length of 11 bits, 6 bits and 7 bits. According to the present application, not the entire data word, i.e. the entire bit sequence, is protected as a whole (i.e. provided with a forward error correction code), but the individual segments are protected. This is shown in the second row by the fact that after each segment A, B and C the corresponding forward error correction code is shown. In a subsequent process step, in the third row, line encoding is applied, or the data from the second row is line encoded in its entirety, so that in the third row a line code is generated. The line code can now be transmitted, and it can be seen that the entire data is line encoded, and the forward error correction code is also line encoded. Thus, the advantages of line encoding apply to all data to be transmitted.

[0164] In Figure 5 The embodiment example at the bottom shows the process steps according to the present application, in which further sub-steps can be carried out. Different bit sequences are shown, in which the user data has now been divided into bit sequences of the same length. Thus, the entire user data is divided into four bit sequences, which all have the same length. The four bit sequences are again subdivided into segments of the same length. Symbolically, the individual bit sequences are arranged horizontally, and these are arranged above and below one another so that each row reflects one bit sequence. As can also be seen, the bit sequences are each divided into three segments of equal length. This gives a matrix-like arrangement of the user data in the form of bit sequences per row and segments per column.

[0165] The line encoding is now no longer carried out as provided in the prior art, but a partial forward error correction is calculated for each column, i.e. for all segments at the same bit position, according to the subdivision rule as specified in the upper process steps. As can be seen in the first row of the second rectangle, the partial forward error correction is shown above, which is referred to as FEC overhead in this figure as a whole. Now, the segmented bit sequences can be obtained according to the subdivision rule, and the partial forward error correction can be obtained for all segments of the same bit position across all bit sequences.

[0166] Now, a segment encoder is applied to all segments of the same bit position to generate a segment line code for each bit position and all segments of each bit sequence. In a further process step or the same process step, the segment encoder used equally for the segments is applied to the corresponding partial forward error correction, resulting in a single line code comprising the segment line code and the partial forward error correction line code. As can be seen below in the present Figure 5 As can be seen in the present

[0167] Figure 6 The number of gates required for creating a forward error correction code is shown in the diagram on the y-axis as a function of the bit length on the x-axis to be encoded. As can be seen here, this is an exponential growth, and from a bit length of 10 bits to 12 bits, the growth of gates, i.e. the number of gates required for forward error correction, grows at a higher than average rate. Therefore, it is particularly advantageous according to the present application to carry out forward error correction for each segment, because this avoids having to consider the entire data word, i.e. the entire bit length. If forward error correction has to consider the entire bit length, the bit length will usually exceed the critical 12 bits. The number of gates required in the forward error correction encoder will increase in an unfavorable manner. This therefore illustrates the advantageous technical effect of the present application, i.e. first forming segments by bit sequences and then calculating forward error correction for the segments.

[0168] At this point, reference is again made to the subdivision rule according to Figure 5 which provides that a segment can have 11 bits, 6 bits or 7 bits.

[0169] By using several FEC encoders / decoders with smaller FEC symbol sizes, both the number of gates required is reduced and the maximum operating frequency F max of a given process node F is increased (the shorter the carry chain, the greater the parallelism).

[0170] Figure 6 The relationship between the FEC symbol size in bits and the required implementation is shown. This refers to a hardware implementation of Reed Solomon FEC. The number of gates is normalized (to a 12-bit symbol size), so a direct comparison is possible. In the graph, the exponentially significant relationship between the symbol size in bits and the implementation in gates can be seen.

[0171] For the respective small FEC sub-encoders, it is not necessary to always use the same symbol width. Large serial line encodings can also be composed of several different sub-encoders (the simplest example is 8b10b, which can be composed of 3b4b and 5b6b, as suggested for use with FEC). In the case of the present application or ADXpress (registered trademark), this is achieved by a total of 11 encoders, which have four basic types: 6b8b, 7b8b, 11b12b and 11b13b. The FEC symbol width used for the respective sub-encoding is determined by the data word width of the respective serial line encoder. For example, for 6b8b, an FEC with a symbol width of 6 bits is used.

[0172] Figure 8AThe complete structure of the transmitter data path according to one aspect of the present invention or ADXpress (registered trademark) is shown in Fig. 1. The data path in the receiver has the corresponding inverse structure (see also Figure 8B ).

[0173] Figure 7A The line encoding or the line encoding device is shown with several line encoding units, e.g. mapping 11 bits to 12 bits, mapping 11 bits to 13 bits, or mapping 11 bits to 12 bits. This corresponds to the sequence from right to left in Fig. 7 and illustrates that the input data word, i.e. the sequence of bits above, is divided into separate segments and then the separate segments are line encoded. The current Figure 7A The calculation of the forward error correction is not considered in the prior art, so that the system arrangement according to Figure 7A can act as an output system arrangement of the present invention.

[0174] Figure 7A In Fig. 1 an arbitrary sequence of 112 bits is shown, which is divided into segments of 11 bits, 6 bits or 7 bits. Then, in parallel, the encoding units are addressed, which convert the bits into sub-symbols, so that the sub-symbols are optimized in terms of the degree of difference. For example, 11 bits are encoded after 12 bits, or 11 bits are encoded after 13 bits.

[0175] In this Figure 7A , the encoding units from the second subset are shown in the left-hand middle (labeled 11B12B). This provides partial symbols with any symbol, i.e. with any degree of difference. To compensate for this degree of difference, the encoding units 11B13B are connected in parallel downstream with respect to the sequence of bits. This means that the following data stream is formed, which converts the 11-bit most significant bits twice into two sub-symbols, i.e. once the 11-bit data segment is converted by 11B12B into a 12-bit sub-symbol with any symbol, i.e. degree of difference, and once the data segment is encoded from 11 bits to 13 bits by means of the encoding unit 11B13B. In the encoding units in the lower part of the figure, the left-hand second encoding unit 11B13B is an encoding unit from the first subset. It has an inverter and a multiplexer. Thus, the first 13 bits are available as a data stream, which is divided so that it is inverted once with respect to the symbol, i.e. the degree of difference, and remains unchanged once. Below it is shown that, with feedback of the degree of difference, the data stream is used which compensates for the positive or negative, i.e. original or inverted, symbol from the left-hand encoding unit. Thus, there are two data streams at the left-hand first multiplexer, each of which represents a partial symbol, one with the regular symbol, i.e. as output from the 11-bit 13-bit encoding unit, and the other with the inverted symbol or inverted degree of difference.

[0176] Based on the feedback from the cells at the top, the disparity generated by the leftmost encoder 1 IB 12B can be determined and, thus, the multiplexer at the lower left corner compensates or minimizes the disparity of the partial symbol of the leftmost encoder 1 IB 12B. This is done in parallel, such that the encoding cells from the second subset are followed by the encoding cells from the first subset, thereby minimizing or eliminating the disparity. Finally, the complete symbol is output at the lower right corner. This complete symbol has 128 bits and is composed of sub-symbols, as these sub-symbols are inserted into the underlying thick line by the slanted arrows. Thus, the sub-symbols, which are optimized or minimized in terms of disparity, are present on this output line and these sub-symbols form the entire symbol, which can then be output and transmitted.

[0177] According to one aspect of the present application, the present application encodes a 112-bit wide data word, which has any disparity (disparity maximum: 112) and any run length (run length maximum: 112), onto a 128-bit wide symbol. Thus, the overhead caused by the encoding is 14.2%.

[0178] The maximum run length occurring in a symbol and any sequence of symbols is 8 equal bits.

[0179] The long-term average maximum disparity is 0. The disparity in a symbol is less than 9.

[0180] The complexity of the logic is very low, equivalent to 10 8B / 10B encoders (but with the known drawback of a large overhead).

[0181] This is achieved by using or using in parallel several "small" encoders, which optimally match each other in terms of their disparity and run length characteristics.

[0182] The 1 IB 12B, 7B 8B and 6B 8B encoders all generate symbols with a guaranteed maximum run length of 6, even if the (partial) symbols are ordered in any order.

[0183] According to one aspect of the present application, the encoder (1 IB 13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the ordering of the (1 IB 13B) with the other encoders ( Figure 2 ), a maximum run length of 8 can be generated in a symbol.

[0184] The characteristics of the encoders are as follows:

[0185] - 1 IB 13B: maps 11 bits of data onto 2048 13-bit symbols. These symbols can be transmitted in inverted or non-inverted form.

[0186] Disparity:

[0187] +3...+9 or controllable -3...-9

[0188] Run length in word: 7

[0189] Run length at edge: 5.

[0190] -11B 13B: 11-bit data mapped to 2048 13-bit symbols. These symbols can be sent in inverted or non-inverted form.

[0191] Differential: +3...+9 or controllable -3...-9

[0192] Run length in word: 7

[0193] Run length at edge: 5

[0194] -11B 12B: 11-bit data mapped to 2048 12-bit symbols. These symbols are sent only in non-inverted form.

[0195] Differential: -2, -1, 0, 1, 2

[0196] Run length in word: 6

[0197] Run length at edge: 3

[0198] -7B 8B: 7-bit data mapped to 128 8-bit symbols. These symbols are sent only in non-inverted form.

[0199] Differential: -2, -1, 0, 1, 2

[0200] Run length in word: 6

[0201] Run length at edge: 3

[0202] -6B 8B: 6-bit data mapped to 64 8-bit symbols. These symbols are sent only in non-inverted form.

[0203] Differential: 0

[0204] Run length in word: 6

[0205] Run length at edge: 3

[0206] With four 11B 13B encoders, a controllable differential of at least +-12 can be generated in order to compensate for the uncontrollable differential of the maximum values of +-12 (6 x +-2) of the 11B 12B and 7B 8B encoders, so that a balanced differential can be reliably achieved regardless of the data to be transmitted.

[0207] To further reduce the complexity of the hardware, four small encoders (11B 13B) are used according to an aspect of the application, the sign of which can be controlled with respect to the sign (+-).

[0208] According to an aspect of the application, the sign of the difference is controlled in such a way that each encoder calculates "its" sub-sign. This is achieved without any effort, since the sub-signs only have a few bits.

[0209] By means of four of the eleven encoders, the sign of the difference of the sub-signs can be actively controlled by inverting the generated sub-signs. For this purpose, the encoders (11B 13B) have the special feature that their signs generate a positive difference (+3...+9) for all input data. By inverting the partial signs, a sign with a negative difference (-3...-9) is obtained.

[0210] In this way, the difference of the partial signs of the other encoders (11B 12B and 7B 8B) (-2, -1, 0, 1, 2) can be compensated. The encoder 6B 8B generates a sign with a difference of always 0. Then, all (partial) parity checks of the encoders (11B 12B and 7B 8B) are added together and the result controls the decision with respect to the number of inverted and non-inverted signs of the encoders (11B 13B) used.

[0211] The lowest (smallest) difference of the encoders 11B 13B is +-3. Thus, a total of four of these encoders can be used to safely compensate for a difference of +-12 (4*+-3) per sign.

[0212] In addition, five (11B 12B) encoders and one (7B 8B) encoder are used, the maximum difference of which is +-2. Thus, in the extreme case, these six encoders generate a difference of exactly +-12 (2*+-6). This can be safely compensated by the 11B 13B encoders.

[0213] According to an aspect of the application, the method can achieve the same quality as the 8B 10B code, but only half the overhead (loss due to encoding).

[0214] Due to the use of multiple small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires only minimal resources (logic).

[0215] The encoding can usually be completely completed within one cycle of the parallel data path (without pipelining).

[0216] The control of the disparity of 128-bit symbols can be implemented with (very) little logic and can be (fully) implemented within one clock cycle of the data path, instead of counting the 1's and 0's in a serial data stream by using a very fast serial clock to calculate the disparity.

[0217] Due to the deterministic disparity and run length, no further scrambling is needed and thus fast synchronization to the data stream (without scrambler synchronization) is possible at the receiver side.

[0218] In addition, this is very useful for power save mode, where the link can be switched off to save energy and switched on again when needed. For this, fast synchronization between transmitter and receiver is necessary.

[0219] According to an aspect of the invention, a 112-bit wide data word with any disparity (disparity maximum: 112) and any run length (run length maximum: 112) is encoded onto a 128-bit wide symbol. The overhead caused by the encoding is thus 14.2%.

[0220] The maximum run length occurring in a symbol and any sequence of symbols is 8 equal bits.

[0221] The long term average maximum disparity is 0. The disparity in a symbol is less than 9.

[0222] The complexity of the logic is very low, comparable to 10 8B / 10B encoders (but with the known disadvantage of a large overhead).

[0223] This is achieved by using or using in parallel several "small" encoders that best match each other in their disparity and run length characteristics.

[0224] The 11B12B, 7B8B and 6B8B encoders all generate symbols with a guaranteed maximum run length of 6, even if the (partial) symbols are ordered in any order.

[0225] According to an aspect of the invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7 or 5 at the beginning or end of the symbol. Due to the ordering of the (11B13B) with the other encoders ( Figure 2 ), a maximum run length of 8 can be generated in a symbol.

[0226] The characteristics of the encoders are as follows:

[0227] To further reduce the complexity of the hardware, four small encoders (11B13B) are used whose disparity can be controlled in terms of the symbol (+-).

[0228] According to an aspect of the application, the symbol disparity is controlled in such a way that each encoder calculates the "its" sub-symbol disparity. This is done without any effort, because the sub-symbols have only a few bits.

[0229] By four of the eleven encoders, the sign of the sub-symbol disparity can be actively controlled by inverting the generated sub-symbols. For this purpose, the encoders (1 IB 13B) have the special feature that their symbols generate a sign with positive disparity (+3...+9) for all input data. By inverting the partial symbols, a sign with negative disparity (-3...-9) is obtained.

[0230] In this way, the disparity of the partial symbols of the other encoders (1 IB 12B and 7B 8B) can be compensated (-2, -1, 0, 1, 2). The encoder 6B 8B generates symbols with a disparity of always 0. Then, all (partial) parity checks of the encoders (1 IB 12B and 7B 8B) are added together and the result controls the decision about the number of inverted and non-inverted symbols with respect to the used encoders (1 IB 13B).

[0231] The lowest (smallest) disparity of the encoders 1 IB 13B is +-3. Therefore, these four encoders can be used in total to safely compensate a disparity of +-12 (4*+-3) per symbol.

[0232] Furthermore, five (1 IB 12B) encoders and one (7B 8B) encoder are used, which have a maximum disparity of +-2. Therefore, in the extreme case, these six encoders generate a disparity of exactly +-12 (2*+-6). This can be safely compensated by the 1 IB 13B encoders.

[0233] The method achieves the same quality as the 8B 10B code, but only half the overhead (loss due to encoding).

[0234] Due to the use of several small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires only minimal resources (logic).

[0235] The encoding can usually be completely done within one cycle of the parallel data path (without pipelining).

[0236] The control of the disparity of 128-bit symbols can be implemented with (very) little logic and can be completely implemented (slow) within one clock cycle of the data path, instead of calculating the disparity by counting the 1-bits and 0-bits in a serial data stream using a very fast serial clock.

[0237] Due to the deterministic difference and run length, no further scrambling is needed and thus a fast synchronization to the data stream at the receiver side is possible (no scrambler synchronization is needed).

[0238] In addition to this, this is very useful for power save mode, where the link can be switched off to save energy and switched on again when needed. For this, a fast synchronization between transmitter and receiver is necessary.

[0239] Now, Figure 7B shows the formation of segments from Figure 7A a modified system arrangement, where now corresponding partial forward error correction encoders are drawn. These encoders are here called FEC modules. Thus, this figure shows that first segments are formed from the bit sequence, which corresponds to the upper arrow pointing down from the user data. Here partial forward error correction is generated, which is then fed into the encoding unit, as Figure 7A has been shown. Here the line encoding unit is called line encoder and both the segments of the bit sequence and the partial forward error correction are line encoded. Also parity check can be adjusted in an optional process step. Then the line encoded data is output at the bottom and sent to the right to the receiver (not shown here) over a potentially error prone communication channel.

[0240] Figure 8A shows a method for improving forward error correction according to the invention and in particular shows the process steps carried out at the transmitter side. Here the Figure 8A arrow at the bottom corresponds to the arrow at the top of Figure 8B . Thus, as shown in Figure 8A the input data is shown, then the partial forward error correction is calculated. As can be seen above, all segments have the same bit length. This means that the first column comprises 11 bits, the second column comprises 11 bits and the last column comprises 6 bits.

[0241] Now, the partial forward error correction is generated for all segments of the same bit sequence, which has the same bit length as the corresponding segment. This results in data with parity check symbols. In a final process step, a serial line encoding is carried out, which for example maps 11 bits to 12 bits, or 11 bits to 13 bits, or 6 bits to 8 bits. Now this data can be sent over a potentially interference prone channel. This results in a transmission as shown in Figure 8A the lower part or Figure 8B the upper part.

[0242] Figure 8B shows the procedure at the receiver side and it corresponds inversely to the procedure in Figure 8A . As the current Figure 8BAs also shown in Fig. 1, it is recognized that bit errors can occur, but these bit errors can be particularly advantageously handled at the segment level. Thus, bit errors do not occur in the entire bit sequence, but only on individual segments, which can thus be advantageously handled. This results in the corrected data as shown in the lower part, whereby the 112-bit data are recovered, as they were used as output in Fig. 1. Figure 8B Figure 8A

[0243] Figure 9 A method for generating efficiently transmittable bit sequences with limited Hamming distance, limited run length and line coding for forward error correction in a vehicle is shown in the form of a flow chart, the method comprising: providing 100 any bit sequence; segmenting 101 the provided bit sequence into a sequence of predefined segments according to a respective predefined bit length; calculating 101 A a forward error correction for each segment or a plurality of segments of the same bit length; encoding 102 each segment or a plurality of segments of the same bit position into one or more sub-symbols together with its forward error correction, respectively, using the same encoding unit of a plurality of encoding units for the segments of the same bit position and the associated forward error correction, respectively, wherein a first subset of encoding units actively controls the sign of the Hamming distance of the generated sub-symbols by inverting the Hamming distance of the sub-symbols to compensate for the Hamming distance of a second subset of encoding units, wherein the juxtaposition of the sub-symbols results in the efficiently transmittable bit sequence together with the calculated forward error correction.

[0244] All segment line codes and all partial forward error correction line codes are also transmitted: In this last step, all generated segment guide codes and partial forward error correction guide codes are sent. These transmitted codes include error detection and correction information for the corresponding segments as well as partial forward error correction. The described method enables an improved forward error correction during line coding and data transmission in a vehicle. By dividing the user data into segments and applying a specific encoding procedure to these segments, an efficient error detection and correction can be achieved at the segment level.

[0245] By iteratively creating partial forward error correction for all segments of the same bit position and applying a segment encoder to each segment, it is possible to make targeted error corrections to the transmitted data. The partial forward error correction line codes contain the necessary information for detecting and correcting errors, while the segment line codes represent the structure and content of the segments and likewise contribute to error detection and correction.

[0246] By transmitting all generated segment line codes and partial forward error correction line codes, the receiver can accordingly analyze the received data and detect and correct errors to ensure a reliable and accurate transmission of user data in a vehicle.

[0247] ​​The described method thus provides improved forward error correction, which is particularly important in challenging environments with disturbances and signal losses such as vehicles. It helps to ensure reliable and high-quality data transmission, which is very important for various applications in the automotive field, such as autonomous driving, vehicle safety systems and infotainment applications.

[0248] The invention makes it possible to maintain all the desired properties and requirements of the serial line coding at all times while operating the FEC efficiently. By positioning the serial line encoder carefully behind the FEC unit, the physical behavior on the link is always deterministically controlled (this is not the case with the use of a scrambler as serial line coding).

[0249] In addition, the selection of the FEC symbol size based on the data word size of the respective serial sub-encoder always ensures that the degree of propagation of bit errors is always minimal (here, a defective row code symbol only generates a defective FEC symbol).

[0250] Furthermore, the use of several FEC sub-encoders results in a very efficient type of so-called interleaving. This can be done without the need for time-consuming manual interleaving, which always requires data to be reserved (more latency and buffer). This also makes it possible to correct burst errors, for example 112 / 128 bit errors.

[0251] This is only the case with the schematic structure of Figure 7A , Figure 7B and Figure 8A , Figure 8B : In this case, a 128-bit error only leads to one symbol error of the respective FEC sub-encoder. With classic single FEC encoding, a burst error of the same length (consecutive 128 error bits) would continuously generate several symbol errors. Depending on the chosen encoding, this can result in the fact that the FEC word (all symbols of the FEC cycle) can no longer be decoded (this also makes correction impossible). This is usually achieved by interleaving the symbols of one FEC cycle with the symbols of one or more other FEC cycles. However, this is only possible by using buffers on the transmitter side and on the receiver side in order to be able to interleave the data in the case of the transmitter and, in the receiver, to restore the data to the original continuous FEC symbol data stream of the individual FEC cycles by means of an inverse operation. By using several small FEC encoders, the interleaving and thus also the provision of the required buffers for the interleaving becomes superfluous (but only to a certain extent; a burst error of more than 128 bits of the row mentioned in the example results in several symbols being damaged per individual FEC).

[0252] The number of symbols (t) that the respective FEC sub-encoder can repair depends on the overhead 2t, see Figure 2This has to be chosen accordingly to the required application. Figure 8A The case of one symbol error per FEC sub-encoder is shown to be achieved already at t = 1 (i.e. two parity symbol overhead). It should also be noted that burst errors can also occur without any limitation in the area of the parity symbols.

[0253] Figure 10 A data format is shown which displays an arbitrary bit sequence on the left hand side and partial symbols on the right hand side. The data to be encoded has 112 bits and the sub-symbols have 128 bits. In this way an arbitrary bit sequence of 112 bits is encoded into a complete symbol of 128 bits. The encoded 128 bit data is optimized in terms of disparity. The arrow in the middle indicates that the encoding unit transforms the data piece on the left hand side into the sub-symbol on the right hand side. The figure also shows that the method can be used multiple times so that any number of bit sequences can be transformed into any number of complete symbols. In addition, the data can be divided into different data cells or data frames.

[0254] Even if the data on the left hand side has the same semantic content as the data on the right hand side, the data on the right hand side is encoded in such a way that it is optimized in terms of disparity. In general, the method of the present invention can be applied to any data, thus to arbitrary bit sequences and both user data and header data can be transmitted.

[0255] The data fields shown are only examples and form an application example of the present invention.

[0256] Figure 11 An encoding unit in the middle is shown as well as the input and output. The output data consists of 112 bits, which are indexed from 0 to 111. These output data are split into pieces of 11 bits, 6 bits, 7 bits or other bit lengths. In this example, these pieces are transformed into sub-symbols of 12, 13, 8 or other data lengths. The example presented is particularly advantageous because it encodes 112 bits into 128 bits, thus achieving a particularly high efficiency. These 128 bits have the same content as the bit sequence to be encoded and are only 16 bits longer.

[0257] The figure shows on the left hand side that an arbitrary bit sequence of 112 bits is segmented into data pieces of 11 bits which are then encoded into 12 bits using the encoding unit 11B12B.

[0258] Figure 12 A data format is shown which can be used, for example, in Figure 10 or Figure 11 The figure shows again a total symbol of 128 bits and an arbitrary data sequence of 112 bits. In general, the arbitrary bit sequence and the total symbol can have different header data or frame data.

[0259] In the following, some specific possibilities are established as to how a fragment of an arbitrary bit sequence can be transformed into a sub-symbol such that the disparity is minimized or eliminated. A first table shows the transformation from 6 bits to 8 bits, a second table shows the transformation from 7 bits to 8 bits, a third table shows the transformation from 11 bits to 12 bits, and a fourth table shows the transformation from 11 bits to 13 bits. Thus, fragments of 6 bits, 7 bits or 11 bits are converted into sub-symbols of 8 bits, 12 bits or 13 bits. The shown encoding is exemplary and illustrates the technical effect achieved in the present case. The invention has been evaluated empirically and, based on the proposed encoding, it is achieved that it can be optimized in terms of bit disparity of 112, so that only 128 bits are required. This corresponds to a so-called overhead of only 14%.

[0260] In the present case, "cell" is used as a synonym for "frame". These can also be packets.

[0261] Cell format / frame format

[0262] According to one aspect of the invention, the cell comprises a header with a fixed bit length, a payload area with 4 selectable bit lengths, and a trailer also with a fixed bit length.

[0263] The cell structure is a bit sequence as follows:

[0264] • 7-bit virtual path identifier (VP), which is a unique address of the virtual path.

[0265] • 3-bit sequence number (SN), which consecutively numbers the cells in order.

[0266] • 2-bit wide cell type (CT) identifier, which specifies the length of the user data.

[0267] • 3-bit wide payload information (PI), which contains additional information about the payload. This can also be used for synchronization of the payload data and frame data or control data.

[0268] • 10-bit wide CRC polynomial (HCRC), which is used for error protection of the header information. The Hamming distance of the polynomial is 5 bits (P=0x2B9) for bit sequences of up to 21 bits.

[0269] • The payload (PL) range has the following lengths: 187 bits, 411 bits, 635 bits or 859 bits, depending on the CT value. The shortest payload is chosen such that it is still greater than the maximum (video) stream bus width supported. (The mapping of the stream data to the cell payload should be simplified).

[0270] • Finally, a 12-bit wide CRC polynomial (PCRC) which is used to error protect the user data. The Hamming distance of the polynomial is 4 bits (P=0x8F3) for bit sequences of up to 2035 bits.

[0271] Format of the transmitted frame

[0272] According to an aspect of the application, the transmitted frame comprises a sequence of M-bit wide words. The frame starts with a M-bit wide "comma" word in a defined comma word sequence for frame alignment. Next come K cells. These cells consist of 2, 4, 6 or 8 N-bit wide words carrying a header, a payload and a trailer. These N-bit wide words are encoded into M-bit wide symbols (line coding).

[0273] This format is chosen to enable processing of the cell data at an appropriate time frequency, provided that the serializer / deserializer always processes blocks of M bits.

[0274] Figure 13 An exemplary part of the encoding of a data fragment into symbols is shown, according to an aspect of the application, where 6 bits are encoded into 8 bits, such that the degree of disparity is optimized. For example, the fragment 000000 is encoded into the partial symbol 00101011, i.e. a 6B8B encoder. Furthermore, Figure 14 A 7B8B encoder is shown, Figure 15 An 11B12B encoder is shown, and Figure 16 An 11B13B encoder is shown.

Claims

1. A method for generating in a car an efficiently transmittable bit sequence with limited Hamming distance, limited run length and line coding of forward error correction, comprising: - providing (100) an arbitrary bit sequence; - segmenting (101) the provided bit sequence into a sequence of predefined segments according to a respective predefined bit length; - calculating (101A) a forward error correction for each of the segments or a plurality of segments of the same bit length; - encoding (102) each segment or a plurality of segments of the same bit position together with its forward error correction into one or more sub-symbols, using the same encoding unit of a plurality of encoding units for the segments of the same bit position and the associated forward error correction, wherein a first subset of encoding units actively controls the sign of the Hamming distance of the generated partial sub-symbols by inverting the Hamming distance of the partial sub-symbols to compensate the Hamming distance of a second subset of encoding units, wherein the juxtaposition of the partial sub-symbols results in the efficiently transmittable bit sequence together with the calculated forward error correction.

2. The method of claim 1, wherein, The calculating (101A) of a forward error correction for each of the segments is carried out in such a way that segments at the same position in a plurality of segmented bit sequences are combined and in this way form the forward error correction.

3. The method according to claim 1 or 2, characterized in that, The Hamming distance of the second subset of encoding units is uncontrollable.

4. The method according to one of the preceding claims, characterized in that, The partial forward error corrections as a whole describe the provided bit sequence in a correctable manner.

5. The method according to one of the preceding claims, characterized in that, The encoding units have a minimum number of gates with respect to the predefined bit length.

6. The method according to one of the preceding claims, characterized in that, Upstream of each encoding unit is connected a calculation unit for calculating the forward error correction.

7. The method according to one of the preceding claims, characterized in that, The encoding units of the first subset encode segments of 11 bits into sub-symbols of 13 bits.

8. The method according to one of the preceding claims, characterized in that, The encoding units of the first subset have a Hamming distance between +3 and +9, which is specifically inverted to -3 to -9 by inverting the partial sub-symbols bit by bit.

9. The method according to one of the preceding claims, characterized in that, The run length in the partial sub-symbols is at most 7.

10. The method according to one of the preceding claims, characterized in that, The run length of the partial sub-symbols in the encoding units of the first subset is at most 5 starting from the most significant bit and / or the least significant bit.

11. The method according to one of the preceding claims, characterized in that, In the case of the encoding units of the second subset, 11-bit segments are encoded into 12-bit sub-symbols or 7-bit segments are encoded into 8-bit sub-symbols or 6-bit segments are encoded into 8-bit sub-symbols.

12. The method according to one of the preceding claims, characterized in that, When there are positive and negative data streams with respect to the total Hamming distance of the complete symbol, a multiplexer selects the data stream that helps to minimize the Hamming distance.

13. A system arrangement for generating in a car an efficiently transmittable bit sequence with limited Hamming distance and limited run length, comprising: - an interface unit, which is arranged to provide (100) an arbitrary bit sequence; - a segmentation unit, which is adapted to segment (101) the provided bit sequence into a sequence of predefined segments according to a respective predefined bit length; - a calculation unit, which is arranged to calculate (101A) a forward error correction for each of the segments or a plurality of segments of the same bit length; - an encoding unit, which is arranged to encode (102) each segment or a plurality of segments of the same bit position together with its forward error correction into one or more sub-symbols, using the same encoding unit of a plurality of encoding units for the segments of the same bit position and the associated forward error correction, wherein a first subset of encoding units actively controls the sign of the Hamming distance of the generated partial sub-symbols by inverting the Hamming distance of the partial sub-symbols to compensate the Hamming distance of a second subset of encoding units, wherein the juxtaposition of the partial sub-symbols results in the efficiently transmittable bit sequence together with the calculated forward error correction. - an encoding device arranged for encoding (102) each segment or a plurality of segments of identical bit positions with their forward error correction separately into one or more partial symbols using the same encoding unit of a plurality of encoding units separately for the segments of identical bit positions and the associated forward error correction, wherein a first subset of encoding units actively controls the sign of the diversity of the generated sub-symbols by inverting the diversity of the sub-symbols to compensate the diversity of a second subset of encoding units, wherein a concatenation of the sub-symbols results in the efficiently transmittable sequence of bits together with the computed forward error correction.

14. A computer program product comprising instructions which, when the program is executed by at least one computer, cause the computer to carry out the steps of the method according to any one of claims 1 to 12.

15. A computer-readable storage medium comprising instructions which, when executed by at least one computer, cause the computer to carry out the steps of the method according to any one of claims 1 to 13.

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