Soft information acquisition method, controller, electronic equipment and storage equipment

Abstract

The invention discloses a soft information acquisition method, a controller, electronic equipment and storage equipment, and relates to the technical field of flash memories. The soft information acquisition method can be applied to cloud computing software. The method comprises the following steps: performing data reading generation processing on a to-be-tested flash memory for a preset number of times based on a reference interpretation voltage and voltage offset information to obtain a plurality of soft bit data, and storing each soft bit data in different second cache units in sequence; third reading processing is carried out on the flash memory to be tested, and hard bit data obtained through reading is stored in the first cache unit; soft information is generated according to the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, and LDPC soft decoding operation is carried out according to the soft information. The demand quantity of the cache unit can be greatly reduced, cache resources are saved, and meanwhile, the soft information acquisition efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of flash memory technology, and in particular to a method for acquiring soft information, a controller, an electronic device, and a storage device. Background Technology

[0002] Low-density parity check code (Low Density Parity LDPC (Low-Level Check Code) decoding is divided into hardware decoding and software decoding. Hardware decoding has the advantages of simplicity and speed, but its decoding capability is relatively weak; software decoding has stronger decoding capability. When using software decoding for LDPC decoding, it is necessary to obtain the soft information of the read data, and then perform LDPC software decoding based on this soft information. Currently, the process of obtaining soft information requires a large number of buffer units to cache the data, resulting in a large demand for buffer units; moreover, it requires CPU participation in logical operations, and the CPU's read / write operations and logical operations consume a lot of time, leading to low efficiency in obtaining soft information. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a soft information acquisition method, controller, electronic device, and storage device, which can significantly reduce the demand for cache units, save cache resources, and improve the efficiency of soft information acquisition.

[0004] In a first aspect, embodiments of this application provide a method for acquiring soft information, applied to a controller, the controller being electrically connected to a cache region; the cache region includes a first cache unit and multiple second cache units; wherein the first cache unit can be reused. The method includes: Based on the reference reading voltage and voltage offset information, the flash memory under test is processed by reading data a preset number of times to generate multiple soft bit data, and each soft bit data is stored sequentially in a different second cache unit. Each data reading and generation process is as follows: a first reading process is performed on the flash memory under test according to the reference reading voltage and the voltage offset information to obtain left offset data, and the left offset data is stored in the first cache unit; a second reading process is performed on the flash memory under test according to the reference reading voltage and the voltage offset information to obtain right offset data; simultaneously, logical operations are performed on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data. The third read process is performed on the flash memory under test, and the hard bit data obtained from the read process is stored in the first cache unit; The soft information is generated according to the hard bit data read from the first cache unit and soft bit data read from all the second cache units, and an LDPC soft decoding operation is performed according to the soft information.

[0005] In a second aspect, an embodiment of the present application provides a controller, comprising at least one processor and a memory connected with the at least one processor for communication; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the soft information acquisition method according to any one of the embodiments of the first aspect.

[0006] In a third aspect, an embodiment of the present application provides an electronic device comprising the controller according to the embodiments of the second aspect.

[0007] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing computer executable instructions for causing a computer to perform the soft information acquisition method according to any one of the embodiments of the first aspect.

[0008] Embodiments of the present application include: The controller is electrically connected with the cache area; the cache area includes a first cache unit and a plurality of second cache units; wherein the first cache unit can be reused; in the process of LDPC decoding operation of the controller, firstly, a preset number of data reading generation processes are performed on the to-be-tested flash memory based on the reference judgment voltage and the voltage offset information, a plurality of soft bit data are obtained, and each soft bit data is sequentially stored in a different second cache unit; wherein, each data reading generation process is used for: performing first reading processing on the to-be-tested flash memory according to the reference judgment voltage and the voltage offset information to obtain left offset data, and storing the left offset data in the first cache unit; performing second reading processing on the to-be-tested flash memory according to the reference judgment voltage and the voltage offset information to obtain right offset data; at the same time, performing logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data; by reusing the same first cache unit to store the left offset data generated in each data reading generation process, the demand for cache units is reduced, and cache resources are saved; and at the same time of generating the right offset data, the left offset data is read to perform logical operation to obtain the soft bit data, the data processing efficiency of the intermediate process is improved, thereby being beneficial to improving the overall soft information acquisition efficiency; then, third reading processing is performed on the to-be-tested flash memory, and the hard bit data read is stored to the first cache unit; finally, the soft information is generated according to the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, so as to perform LDPC soft decoding operation according to the soft information; the efficiency of the whole process of obtaining soft information is improved. That is to say, the embodiment of the application can greatly reduce the demand for cache units, save cache resources, and at the same time improve the soft information acquisition efficiency.

[0009] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic diagram of a system architecture for performing a soft information acquisition method provided by an embodiment of the present application; Figure 2 is a flowchart of a soft information acquisition method provided by an embodiment of the present application; Figure 3 is a schematic diagram of a threshold voltage distribution curve of a NAND flash memory device provided by an embodiment of the present application; Figure 4 is a schematic diagram of a threshold voltage distribution curve overlap of a NAND flash memory device provided by an embodiment of the present application; Figure 5 This is a schematic diagram of the threshold voltage distribution of the LSB page of a typical TLC NAND provided in one embodiment of this application; Figure 6 This is a schematic diagram of a soft information acquisition method provided in one embodiment of this application; Figure 7 This is a schematic diagram of a prior art soft information acquisition method provided in an embodiment of this application; Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0012] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0014] This application provides a method for acquiring soft information, a controller, an electronic device, and a computer-readable storage medium, relating to the field of flash memory technology. The method includes: performing a preset number of data reads on the flash memory under test based on a reference reading voltage and voltage offset information to generate multiple soft bit data, and storing each soft bit data sequentially in a different second cache unit; performing a third read process on the flash memory under test to store the read hard bit data in a first cache unit; generating soft information based on the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, and performing LDPC soft decoding operation based on the soft information. This significantly reduces the demand for cache units, saves cache resources, and improves the efficiency of soft information acquisition.

[0015] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0016] like Figure 1 As shown,Figure 1 is a schematic diagram of a system architecture for performing a soft information acquisition method provided by an embodiment of the present application; the system architecture for performing the soft information acquisition method comprises an LDPC decoder 400, a controller 100, a cache area 300, and a flash memory to be tested 200. The controller 100 is electrically connected with the LDPC decoder 400, the cache area 300, and the flash memory to be tested 200. The cache area 300 comprises a first cache unit and a plurality of second cache units; wherein the first cache unit can be reused. It should be noted that, Figure 1 BUF_0 is the first cache unit, and BUF_1, BUF_2, BUF_3, …, BUF_n are the second cache units.

[0017] Specifically, the controller 100 is configured to: based on a reference read voltage and voltage offset information, perform a preset number of data read generation processes on the flash memory to be tested 200, to obtain a plurality of soft bit data, and sequentially store each soft bit data in a different second cache unit; wherein each data read generation process is configured to: based on the reference read voltage and the voltage offset information, perform a first read process on the flash memory to be tested to obtain left offset data, and store the left offset data in the first cache unit; perform a second read process on the flash memory to be tested based on the reference read voltage and the voltage offset information to obtain right offset data; simultaneously, perform a logical operation process on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data; perform a third read process on the flash memory to be tested, and store the hard bit data obtained by the read process in the first cache unit; generate soft information based on the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, to perform an LDPC soft decoding operation based on the soft information.

[0018] Specifically, the LDPC decoder 400 is configured to perform an LDPC soft decoding operation on the to-be-decoded data read from the flash memory to be tested based on the soft information output by the controller.

[0019] The controller 100, the LDPC decoder 400, the cache area 300, and the flash memory to be tested 200 cooperate with each other to implement the soft information acquisition method provided by the embodiment of the present application, which can greatly reduce the demand for cache units, save cache resources, and improve the soft information acquisition efficiency.

[0020] Those skilled in the art can understand that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and can include more or fewer components than the figure, or combine certain components, or different component arrangements.

[0021] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0022] It will be understood by those skilled in the art that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. It is known by those skilled in the art that with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0023] Based on the above system structure, various embodiments of the soft information acquisition method of this application are proposed below.

[0024] like Figure 2 As shown, this soft information acquisition method can be applied to, for example... Figure 1 The controller shown is electrically connected to the cache area; the cache area includes a first cache unit and multiple second cache units; wherein the first cache unit can be reused; the soft information acquisition method may include, but is not limited to, steps S100 to S300.

[0025] Step S100: Based on the reference reading voltage and voltage offset information, perform a preset number of data read generation processes on the flash memory under test to obtain multiple soft bit data, and store each soft bit data in a different second cache unit in sequence; wherein, each data read generation process is used to: perform a first read process on the flash memory under test according to the reference reading voltage and voltage offset information to obtain left offset data, and store the left offset data in the first cache unit; perform a second read process on the flash memory under test according to the reference reading voltage and voltage offset information to obtain right offset data; at the same time, perform logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain soft bit data.

[0026] Step S200: Perform a third read process on the flash memory under test, and store the read hard bit data into the first cache unit.

[0027] Step S300: Generate soft information based on the hard bit data read from the first buffer unit and the soft bit data read from all the second buffer units, so as to perform LDPC soft decoding operation based on the soft information.

[0028] Understandably, this method of acquiring soft information can be applied to cloud computing software.

[0029] Specifically, the soft information, hard bit data, and soft bit data involved in this application are further explained as follows.

[0030] It's important to note that NAND Flash is a non-volatile memory technology. NAND Flash (i.e., NAND flash memory devices) uses floating-gate transistors as data storage units. The storage state (0 or 1) is distinguished by the amount of charge on the floating gate. The reference value of NAND Flash refers to the critical threshold (Vth) of charge in its storage cell. When the charge in the floating gate transistor exceeds the reference value, the storage state is 0; below the reference value, it is 1. Figure 3 As shown, with the increase in the number of erase and write cycles of NAND flash memory devices, read / write interference can cause accidental injection or loss of electrons in the floating-gate transistor. This affects the number of charges stored in the floating-gate transistor, causing the threshold voltage distribution curve, which was originally independently distributed on both sides of the reference value, to change (see...). Figure 3 There is overlap. Information in the overlapping areas can be misinterpreted, as shown below. Figure 4 As shown, in the overlapping part of the two threshold voltage distribution curves, 1 falling to the right of the reference value is misjudged as 0, and 0 falling to the left of the reference value is misjudged as 1.

[0031] Understandably, a large amount of misjudgment information will affect the error correction capability of LDPC, and may even fail to meet the read error correction requirements. In this case, it is necessary to use several bits of soft information for soft decoding. Generally, soft information consists of one hard bit (HB) and one or more soft bits (SB). The data read from flash memory with the read voltage set as the reference value is called HB. SB is obtained by shifting the read voltage to the left by -ΔV based on the reference value, reading SB_L, then shifting it to the right by +ΔV based on the reference value, reading SB_R, and finally performing a logical operation (XNOR / XOR) on SB_L and SB_R to obtain SB. The soft bit represents the reliability of the hard bit; the more soft bit information, the stronger the LDPC error correction capability. By setting different ΔV values, one or more soft bits can be obtained for a single hard bit.

[0032] like Figure 5 As shown, the data is 0 between the read voltages A and E, and 1 elsewhere. When the read voltages are set to A and E, the data read from the FLASH is HB; when the read voltages are set to A-ΔA and E-ΔE, the data read from the FLASH is SB_L; when the read voltages are set to A+ΔA and E+ΔE, the data read from the FLASH is SB_R. The XOR operation between SB_L and SB_R yields SB. It can be seen that SB is 0 in the overlapping regions V2 and V3, and V14 and V15, indicating that the reliability of HB in these two regions is low. This can help the LDPC decoder make decoding decisions and improve error correction capabilities.

[0033] Further, the step S100, the step S200 and the step S300 provided by the embodiments of the present application are sequentially described.

[0034] According to some embodiments of the present application, the step S100 is further described. The soft information acquisition method further includes but is not limited to the following steps: before each data read generation process based on the reference interpretation voltage and the voltage offset information on the to-be-tested flash memory, determining the current execution order of the data read generation process; when the current execution order determines the voltage offset amount corresponding to the voltage offset information.

[0035] Specifically, when the current execution order of the data read generation process is the first time, the updated offset information adopts the first voltage offset amount delt0; when the current execution order is the second time, the updated offset information adopts the second voltage offset amount delt1; when the current execution order is the third time, the updated offset information adopts the third voltage offset amount delt2; and so on. It should be noted that the first voltage offset amount delt0, the second voltage offset amount delt1, the third voltage offset amount delt2 and other offset information are preset, and the present application does not make specific limitations on the values of the voltage offset amounts in the offset information.

[0036] The first read process, the second read process and the logical operation process included in the data read generation process of the present application are further sequentially described.

[0037] According to some embodiments of the present application, the step S100 is further described. The first read process on the to-be-tested flash memory according to the reference interpretation voltage and the voltage offset information includes but is not limited to the following steps: the reference interpretation voltage is respectively left shifted by the voltage offset amount to obtain the left offset interpretation voltage; and the bit data in the to-be-tested flash memory is read according to the left offset interpretation voltage to obtain the left offset data.

[0038] Specifically, a first read process is described by taking an example. Assuming that the reference interpretation voltage is U0, in the case that the current execution order of the data read generation process is the first time, the updated offset information adopts the first voltage offset amount delt0, and then the left offset interpretation voltage is UL_1=U0-delt0. In the case that the current execution order of the data read generation process is the second time, the updated offset information adopts the second voltage offset amount delt1, and then the left offset interpretation voltage is UL_2=U0-delt1.

[0039] It can be seen that the left offset data obtained by the first read process lays a data foundation for subsequent logical operation process.

[0040] Specifically, for different types of flash memory to be tested, the number of required interpretation voltages is different. For example: for SLC flash memory, each memory cell has 2 states, only 1 interpretation voltage is needed to distinguish; for MLC flash memory, each memory cell has 4 states, 3 interpretation voltages are needed to distinguish; for TLC flash memory, each memory cell has 8 states, 7 interpretation voltages are needed to distinguish; for QLC flash memory, each memory cell has 16 states, 15 interpretation voltages are needed to distinguish; shifting the reference interpretation voltage left by the voltage offset in the first reading process means that all interpretation voltages are shifted left by the voltage offset; similarly, in the second reading process, all interpretation voltages are shifted right by the voltage offset.

[0041] According to some embodiments of the present application, step S100 is further illustrated, wherein the second reading process on the flash memory to be tested according to the reference interpretation voltage and the voltage offset information to obtain right offset data includes but is not limited to the following steps: shifting the reference interpretation voltage right by the voltage offset to obtain right offset interpretation voltage; reading the bit data in the flash memory to be tested according to the right offset interpretation voltage to obtain right offset data.

[0042] Specifically, taking an example to illustrate the second reading process: assuming that the reference interpretation voltage is U0, in the case of the current execution order of the data reading generation process being the first time, the updated offset information adopts the first voltage offset delt0, and the right offset interpretation voltage is UR_1=U0+delt0. In the case of the current execution order of the data reading generation process being the second time, the updated offset information adopts the second voltage offset delt1, and the left offset interpretation voltage is UR_2=U0+delt1.

[0043] It can be seen that the right offset data obtained through the second reading process lays a data foundation for subsequent logical operation processing.

[0044] Specifically, the logical operation processing is an exclusive OR operation or an exclusive OR operation.

[0045] According to some embodiments of the present application, embodiment one: performing logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain soft bit data, including: generating the right offset data while reading the left offset data from the first cache unit; performing an exclusive OR operation on the left offset data and the right offset data to obtain soft bit data.

[0046] It should be noted that the operation logic of the exclusive OR operation is: when the two inputs are the same, the output is true (1); when the two inputs are different, the output is false (0).

[0047] According to some embodiments of the present application, embodiment two: the soft bit data is obtained by performing logical operation processing on the right offset data and the left offset data read from the first cache unit, comprising: reading the left offset data from the first cache unit while generating the right offset data; performing exclusive or operation on the left offset data and the right offset data to obtain the soft bit data.

[0048] It should be noted that the operation logic of the exclusive or operation is: when the two inputs are the same, the output is false (0); when the two inputs are different, the output is true (1).

[0049] The present application embodiment generates soft bit data through step S100, which lays a data foundation for subsequent generation of soft information.

[0050] According to some embodiments of the present application, step S200 is further described, step S200: performing third reading processing on the to-be-tested flash memory, and storing the read hard bit data to the first cache unit includes but is not limited to the following steps: in the case that the execution number of the data reading generation processing is equal to the preset number, it is judged that the data reading generation processing is completed, and the hard bit data is read from the to-be-tested flash memory based on the reference judgment voltage; store the hard bit data to the first cache unit. It can be seen that the hard bit data is obtained through step S200 and stored in the first cache unit which is reused, reducing the demand for storage units; and laying a data foundation for subsequent generation of soft information.

[0051] Specifically, in step S300, after reading the hard bit data from the first cache unit and the soft bit data read from all the second cache units, the soft information is generated based on the hard bit data and all the soft bit data; the controller sends the soft information to the LDPC decoder, so that the LDPC decoder performs LDPC soft decoding operation on the to-be-decoded data obtained from the to-be-tested flash memory according to the soft information.

[0052] The application generates a plurality of soft bit data through the step S100 to the step S300 in the process of the controller performing the LDPC decoding operation, and stores each soft bit data in different second cache units in sequence. Each data reading generation process is used to: perform a first reading process on the to-be-tested flash memory according to the reference judgment voltage and the voltage offset information to obtain left offset data, and store the left offset data in a first cache unit; perform a second reading process on the to-be-tested flash memory according to the reference judgment voltage and the voltage offset information to obtain right offset data; at the same time, perform a logical operation process on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data; by multiplexing the same first cache unit to store the left offset data generated in each data reading generation process, the demand for cache units is reduced, and the cache resources are saved; and the left offset data is read at the same time of generating the right offset data to obtain the soft bit data through the logical operation, the data processing efficiency of the intermediate process is improved, thereby being beneficial to improving the overall soft information acquisition efficiency; then, a third reading process is performed on the to-be-tested flash memory, and the hard bit data obtained by reading is stored in the first cache unit; finally, the soft information is generated according to the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, so as to perform the LDPC soft decoding operation according to the soft information; the efficiency of the whole process of obtaining the soft information is improved. That is to say, the embodiment of the application can greatly reduce the demand for cache units, save cache resources, and at the same time improve the soft information acquisition efficiency.

[0053] It can be seen that the application moves the judgment voltage from the reference value left by delt_n respectively, reads SBn_L from the NAND FLASH, and stores it into BUF_0; then moves the judgment voltage from the reference value right by delt_n respectively, reads SBn_R from the NAND FLASH, and takes out SBn_L from BUF_0 at the same time, and obtains SBn after logical operation (XOR / AND) of the two, and stores it into BUF_n+1 respectively; in this way, according to the above two steps, the n times (n>=0) of recirculation are repeated, and all SBn data are obtained; finally, the judgment voltage is set as the reference value, HB is obtained from the FLASH and stored into BUF_0; HB, SB0…SBn are taken out from BUF_0~BUF_n+1 and sent to the LDPC decoder for soft decoding. It can be understood that n in SB_n (n>=0) determines the preset number of times of data reading generation processing, the value of n is determined by the LDPC Decoder Spec, the larger the n is, the more hardware resources and cache BUF are needed, and the more time is needed to obtain soft information, but the soft decoding performance is also stronger, so the value of n is finally determined, which is a compromise choice. In practical use, 1HB+4SB can meet the use requirement, SB0~SB3, so n is 3 (that is, the preset number of times is four, and four times of data reading generation processing are needed).

[0054] Further, in combination with Figure 6 , an example is used to illustrate the overall flow of the soft information acquisition method of the embodiment of the application. The overall flow of the soft information acquisition method of the embodiment of the application is as follows: Step S1: first, set the judgment voltage as the reference value, denoted as judgment reference voltage; move the judgment reference voltage left by delt0 respectively, obtain SB0_L from the FLASH (that is, the to-be-tested flash memory in the application), and store it into BUF_0 (that is, the first cache unit in the application); Step S2: then, move the judgment reference voltage right by delt0 respectively, obtain SB0_R from the FLASH, and take out SB0_L from BUF0 at the same time, obtain SB0 after logical operation (XOR / AND) of SB0_R and SB0_L, and store it into BUF_1 (the first second cache unit).

[0055] Step S3: continue to move the judgment reference voltage left by delt1 respectively, obtain SB1_L from the FLASH, and store it into BUF_0.

[0056] Step S4: then, move the judgment reference voltage right by delt1 respectively, obtain SB1_R from the FLASH, and take out SB1_L from BUF_0 at the same time, obtain SB1 after logical operation (XOR / AND) of SB0_R and SB0_L, and store it into BUF_2.

[0057] Step S5: Continue to move the judgment reference voltage left by delt2, respectively, obtain SB2_L from the FLASH, and store it into BUF_0.

[0058] Step S6: Then move the judgment reference voltage right by delt2, respectively, obtain SB2_R from the FLASH, and SB2_L from BUF_0, and perform logical operation (XOR / AND) on SB0_R and SB0_L to obtain SB2, and store it into BUF_3.

[0059] Step S7: Continue to move the judgment reference voltage left by delt3, respectively, obtain SB3_L from the FLASH, and store it into BUF_0.

[0060] Step S8: Then move the judgment reference voltage right by delt3, respectively, obtain SB3_R from the FLASH, and SB3_L from BUF_0, and perform logical operation (XOR / AND) on SB0_R and SB0_L to obtain SB_3, and store it into BUF_4.

[0061] Step S9: Finally, based on the judgment reference voltage, obtain HB from the FLASH, and store it into BUF_0.

[0062] Step S10: Take HB, SB0, SB1, SB2, and SB3 from BUF0 to BUF4, and send them to the LDPC decoder for soft decoding operation.

[0063] It can be seen that, in the embodiment of the application, the related data is read from the NAND FLASH, and then the logical operation is performed by hardware and stored into the BUF, when all the related data is read from the NAND FLASH, all the soft information can be obtained, the reading and writing time of the CPU, the logical operation time, and more than half of the BUF demand can be saved, the cache resources are saved, and the efficiency of obtaining the soft information is greatly improved.

[0064] In combination with Figure 7 , the specific process of obtaining 1HB+4SB LDPC soft information of the NAND FLASH in the prior art is described, and the process includes: Step S1: First, set the judgment voltage as a reference value, denoted as a judgment reference voltage, and based on the judgment reference voltage, obtain HB from the FLASH, and store it into BUF_0.

[0065] Step S2: Move the judgment reference voltage left by delt0, respectively, obtain SB0_L from the FLASH, and store it into BUF_1.

[0066] Step S3: Then shift the decision reference voltage right by deltO, get SB0_R from FLASH, and store it in BUF_2.

[0067] Step S4: Continue to shift the decision reference voltage left by delt1, get SB1_L from FLASH, and store it in BUF_3.

[0068] Step S5: Then shift the decision reference voltage right by delt1, get SB1_R from FLASH, and store it in BUF_4.

[0069] Step S6: Continue to shift the decision reference voltage left by delt2, get SB2_L from FLASH, and store it in BUF_5.

[0070] Step S7: Then shift the decision reference voltage right by delt2, get SB2_R from FLASH, and store it in BUF_6.

[0071] Step S8: Continue to shift the decision reference voltage left by delt3, get SB3_L from FLASH, and store it in BUF_7.

[0072] Step S9: Then shift the decision reference voltage right by delt3, get SB3_R from FLASH, and store it in BUF_8.

[0073] Steps S10 to S12. CPU takes SB0_L and SB0_R from BUF_1 and BUF_2, and performs logical operation to get SB0, and then stores it in BUF_9.

[0074] Steps S13 to S15. CPU takes SB1_L and SB1_R from BUF_3 and BUF_4, and performs logical operation to get SB1, and then stores it in BUF_10.

[0075] Steps S16 to S18. CPU takes SB2_L and SB2_R from BUF_5 and BUF_6, and performs logical operation to get SB2, and then stores it in BUF_11.

[0076] Steps S19 to S21. CPU takes SB3_L and SB3_R from BUF_7 and BUF_8, and performs logical operation to get SB3, and then stores it in BUF_12.

[0077] Step S22: Take HB, SB0, SB1, SB2, SB3 from BUF_0 and BUF_9 to BUF_12, and send them to the LDPC decoder for soft decoding.

[0078] It can be seen that the prior art process of obtaining soft information needs to use a large number of BUFs to cache data, and needs CPU to participate in logical operation, and CPU reading and writing BUF and logical operation need to spend a lot of time. Compared with this, the application stores the left offset data generated in each data reading generation process in the same first cache unit to reduce the demand for cache units and save cache resources; and the left offset data is read at the same time as the right offset data is generated to obtain soft bit data through logical operation, improving the data processing efficiency of the intermediate process, thereby facilitating the improvement of the overall soft information acquisition efficiency.

[0079] As shown in Figure 8 The application further provides a controller, comprising: The processor 801 can be implemented in a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute related programs to implement the technical solutions provided by the embodiments of the application. The memory 802 can be implemented in a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 802 and are called and executed by the processor 801 to implement the soft information acquisition method of the embodiments of the application. The input / output interface 803 is used to realize information input and output. The communication interface 804 is used to realize the communication interaction between the device and other devices. The communication can be realized by wired means (such as USB, network cable, etc.), or by wireless means (such as mobile network, WIFI, Bluetooth, etc.). The bus 805 transmits information between various components (such as the processor 801, the memory 802, the input / output interface 803, and the communication interface 804) of the device. The processor 801, the memory 802, the input / output interface 803, and the communication interface 804 are connected to each other through the bus 805 for internal communication.

[0080] The embodiments of the application further provide an electronic device comprising the above controller.

[0081] The embodiment of the present application further provides a storage medium, which is a computer readable storage medium, and stores a computer program. The computer program is executed by a processor to implement the soft information acquisition method.

[0082] The memory, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged relative to the processor, and the remote memory can be connected to the processor through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The above-described device embodiments are only schematic, and units described as separate components can or can not be physically separated, and can be implemented in one location, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0083] Those skilled in the art can understand that all or some of the steps in the above disclosed method and system can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those skilled in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0084] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the present application.

Claims

1. A soft information acquisition method characterized by comprising: The application is applied to a controller which is electrically connected with a cache area; the cache area comprises a first cache unit and a plurality of second cache units; The first cache unit can be reused; The method comprises: Based on the reference reading voltage and the voltage offset information, a preset number of data reading generation processes are performed on the to-be-tested flash memory to obtain a plurality of soft bit data, and each soft bit data is sequentially stored in a different second cache unit; wherein each data reading generation process is used to: according to the reference reading voltage and the voltage offset information, perform a first reading process on the to-be-tested flash memory to obtain left offset data, and store the left offset data in the first cache unit; according to the reference reading voltage and the voltage offset information, perform a second reading process on the to-be-tested flash memory to obtain right offset data; at the same time, perform logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data; Perform a third reading process on the to-be-tested flash memory, and store the hard bit data obtained by reading into the first cache unit; According to the hard bit data read from the first cache unit and the soft bit data read from all the second cache units, soft information is generated to perform an LDPC soft decoding operation according to the soft information.

2. The soft information acquisition method according to claim 1, characterized by, The method further comprises: Before each data reading generation process based on the reference reading voltage and the voltage offset information is performed on the to-be-tested flash memory, the current execution order of the data reading generation process is determined; When the current execution order determines the voltage offset amount corresponding to the voltage offset information.

3. The soft information acquisition method according to claim 2, wherein The first reading process on the to-be-tested flash memory according to the reference reading voltage and the voltage offset information comprises: The reference reading voltage is respectively left shifted by the voltage offset amount to obtain a left offset reading voltage; According to the left offset reading voltage, the bit data in the to-be-tested flash memory is read to obtain left offset data.

4. The soft information acquisition method according to claim 2, wherein The second reading process on the to-be-tested flash memory according to the reference reading voltage and the voltage offset information comprises: The reference reading voltage is respectively right shifted by the voltage offset amount to obtain a right offset reading voltage; According to the right offset reading voltage, the bit data in the to-be-tested flash memory is read to obtain right offset data.

5. The soft information acquisition method according to claim 1, characterized by, The logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data comprises: The left offset data is read from the first cache unit while the right offset data is generated; The left offset data and the right offset data are subjected to exclusive or operation to obtain the soft bit data.

6. The soft information acquisition method according to claim 1, wherein The logical operation processing on the right offset data and the left offset data read from the first cache unit to obtain the soft bit data comprises: The left offset data is read from the first cache unit while the right offset data is generated; The left offset data and the right offset data are subjected to exclusive or operation to obtain the soft bit data.

7. The soft information acquisition method according to claim 1, wherein The third reading process is performed on the to-be-tested flash memory, and hard bit data obtained by reading is stored in the first cache unit, which includes: In a case where the number of times of execution of the data reading generation process is equal to the preset number of times, it is determined that the data reading generation process is completed, and hard bit data is read from the to-be-tested flash memory based on the reference judgment voltage; The hard bit data is stored in the first cache unit.

8. A controller characterized by comprising: The memory is connected to the at least one processor in communication and stores instructions executable by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the soft information acquisition method according to any one of claims 1 to 7.

9. An electronic device, comprising: The controller according to claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to execute the soft information acquisition method according to any one of claims 1 to 7.

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