Satellite-borne SRAM type FPGA program on-orbit reconstruction system

Abstract

The invention discloses a satellite-borne SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) program on-orbit reconstruction system, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, and is characterized in that the data processing unit comprises a satellite-ground data processing module used for receiving an intermediate frequency signal from a satellite and carrying out demodulation, AOS (Advanced Orthogonal System) data frame recovery, data descrambling and LDPC (Low Density Parity Check) decoding; the on-satellite data processing module is used for carrying out AOS data frame analysis, uploading data packet recombination, verification and secondary packaging; the JFMRS01RH unit is used for receiving the uploading data packet which is secondarily packaged by the data processing unit, performing state monitoring and feeding back to the data processing unit, and is also used for task scheduling management; the external storage unit is used for caching the recombined uploading data packet and is also used for storing an uploading file to be loaded to the target FPGA; and the target FPGA is used for providing logic control and algorithm implementation for the load of the on-orbit satellite.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of satellite integrated electronics and on-orbit software / FPGA reconfiguration, and particularly relates to an on-orbit reconfiguration system for a satellite-borne SRAM type FPGA program. BACKGROUND

[0002] In recent years, with the rapid development of space technology, the functions of satellite payloads are becoming increasingly complex, and higher requirements are placed on the real-time performance, flexibility and reliability of data processing and logic control. SRAM type FPGAs, with their advantages of repeatable programming, flexible configuration and high performance, are gradually becoming the core control chips in the design of satellite payloads. They play an irreplaceable role in on-board data processing, logic control management and other aspects.

[0003] The advantages of SRAM type FPGAs mainly lie in the following aspects: first, their repeatable programming feature allows them to be flexibly configured according to different application requirements, meeting the diverse task requirements of satellite payloads; second, SRAM type FPGAs have parallel processing capabilities, enabling efficient processing of massive data and meeting the real-time requirements of on-board data processing; in addition, SRAM type FPGAs also have the advantages of short design cycle and low development cost, which can effectively shorten the development cycle of satellite payloads.

[0004] However, SRAM type FPGAs also face severe challenges in space environments. First, there are a large number of high-energy radiation particles in space environments, which can cause the state of the storage unit of the SRAM type FPGA to flip, i.e., the Single Event Upset (SEU) effect. The SEU effect can cause internal logic errors in the FPGA, and even cause the satellite payload to fail, seriously threatening the safety and reliability of the satellite in orbit. Second, during the on-orbit operation of the satellite, errors or vulnerabilities may be found in the FPGA logic design, which can cause the satellite to malfunction or even cause mission failure. In addition, the adaptability requirements of spacecraft during on-orbit operation also place higher requirements on the reconfigurability of FPGAs, and some on-orbit satellite products also face the problem of needing to adapt to different task requirements while the hardware remains unchanged.

[0005] Therefore, for satellites in on-orbit operation, it is of great practical significance to reconfigure the FPGA program through ground commands or autonomous decision-making to repair logic errors, update functions or adapt to new task requirements. At the same time, FPGA on-orbit reconfiguration technology can effectively improve the reliability and flexibility of satellites, prolong the service life of satellites and reduce the maintenance cost of satellites. FPGA on-orbit reconfiguration technology will provide stronger support for the design and application of satellite payloads, and will greatly improve the reliability of on-orbit satellites and the success rate of missions. SUMMARY

[0006] The present application aims at overcoming the defects of the prior art and provides a satellite-borne SRAM type FPGA program on-orbit reconfiguration system.

[0007] Therefore, the present application provides a satellite-borne SRAM type FPGA program on-orbit reconfiguration system, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, wherein, The data processing unit comprises a satellite-ground data processing module and an on-satellite data processing module, the satellite-ground data processing module is configured to receive intermediate frequency signals from a satellite, perform demodulation, AOS data frame recovery, data descrambling and LDPC decoding, and the on-satellite data processing module is configured to sequentially perform AOS data frame analysis, uplink data packet reconfiguration, checksum secondary packaging and transmission to the JFMRS01RH unit; The JFMRS01RH unit is configured to receive the uplink data packet after secondary packaging by the data processing unit, perform state monitoring and feedback the state to the data processing unit, and perform task scheduling management; The external storage unit is configured to cache the uplink data packet after reconfiguration, and store the uplink file to be loaded to the target FPGA; The target FPGA is configured to provide logical control and algorithm implementation for the load of the on-orbit satellite.

[0008] As an improvement of the above system, the processing process of the satellite-ground data processing module comprises: Receiving intermediate frequency signals from a satellite, sampling, frequency acquisition, carrier synchronization and timing synchronization are performed on the uplink digital signals obtained by sampling, so as to complete the conversion from analog signals to digital signals; According to the transceiver level, the pilot of the air interface non-numbered information frame is removed in the receiving time slot, and the standard AOS frame format is recovered; The data transmission frame of the de-pilot group AOS frame is received, the original scrambling area is descrambled, the effective frame after descrambling is processed for effectiveness, and then LDPC decoding is performed according to the decoding rule of (8160, 7136) low density parity check code, and the decoded data and the instructions from the ground are output to the on-satellite data processing module.

[0009] As an improvement of the above system, the processing process of the on-satellite data processing module comprises: The data packet is subjected to effectiveness detection, and it is judged whether the starting information of the data packet is correct, if yes, it is an effective data packet, otherwise, it is invalid data and is discarded; Extract and latch the virtual channel identifier in the uplink data packet, used to generate the logical address of the SDRAM, and extract the data source packet information of the FPGA program to be reconstructed from the AOS transmission frame according to the link protocol; Extract the length field of the valid data packet, and perform verification and judgment; if the data packet is correct, generate the logical address of the cache according to the virtual channel identifier and the data packet number, and map out the physical address, so as to cache the uplink data packet in the SDRAM; if the data packet is incorrect, feed back the data packet number to the ground, and cache the uplink data packet in the SDRAM according to the logical address generated according to the virtual channel identifier and the data packet number and the physical address mapped out after the ground returns the updated correct data packet; Pack the valid data packet into a data packet conforming to the programming operation of the NOR Flash according to the format required by the JFMRS01RH protocol, and send it to the JFMRS01RH unit through the UART interface according to the agreed format.

[0010] As an improvement of the above system, the data processing unit further comprises a clock management module, a UART control module and an SDRAM control module; wherein, The clock management module is configured to generate the clock of the space-ground data processing module and the on-board data processing module according to the clock frequency of the external crystal oscillator, and provide a clock signal to the JFMRS01RH unit; The UART control module is configured to send instruction information to the JFMRS01RH unit, and receive the state information fed back by the JFMRS01RH unit; The SDRAM control module is configured to schedule and control the external SDRAM chip, which is configured to provide cache for the on-orbit reconstruction file of the target FPGA received by the on-board data processing module.

[0011] As an improvement of the above system, the JFMRS01RH unit comprises a clock module, a UART control module, a configuration control module, an FPGA control module and a NOR Flash control module, wherein, The clock module is configured to receive the clock signal from the clock management module of the data processing unit, and generate clocks of different frequencies for other modules inside the JFMRS01RH unit; The UART control module is configured to receive and analyze the instruction information from the data processing unit, and feed back the state information to the UART control module of the data processing unit; The configuration control module is used for detecting the model, interface mode and interface connection mode of the target FPGA, and is also used for detecting and counting whether the target FPGA appears readback error and / or refresh error due to single particle function interruption event in the refreshing and loading process, and configuring the refreshing and readback mode, refreshing time interval and readback time interval of the target FPGA; The FPGA control module is used for configuring the bit stream of the target FPGA according to the predetermined process according to the program needing to be updated. The NOR Flash control module is used for monitoring the state of the JFMRS01RH unit, updating the program storage area identifier when the data writing condition is met, encapsulating the valid data in the correct injection data packet into a data packet conforming to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and sending the data packet to the JFMRS01RH unit through the UART interface according to the agreed format, and starting the NOR Flash writing operation.

[0012] As an improvement of the above system, the JFMRS01RH unit uses the RS422 serial port communication mode to feed back the state to the data processing unit, the feedback state includes: the refreshing state, the reloading state, the reloading and refreshing bit stream CRC detection result, the UART command CRC state, the FLASH operation result, the UART processing state and the FIFO data state of the FPGA, the baud rate of the communication is 115200bps, the format of the state data packet is: frame header+offset address+1B data+2B CRC check+frame tail, and 21 bytes are sent once.

[0013] As an improvement of the above system, the external storage unit includes: an SDRAM buffer and a NOR Flash buffer. The SDRAM buffer interacts with the data processing unit for data, and is used for buffering the recombined on-board data packet. The NOR Flash buffer interacts with the JFMRS01RH unit for data, and is used for storing the on-board file loaded to the target FPGA.

[0014] As an improvement of the above system, the target FPGA is any one of the JFM4V, JFM7V, JFM7K series of Fudan Micro Company and the VIRTEX2, VIRTEX4~7 and KINTEX7 series of Xilinx Company.

[0015] Compared with the prior art, the application has the following advantages: 1. The application has the receiving and analyzing ability of the uplink intermediate frequency data from the satellite; 2. The application supports the data packet disorder processing and data packet retransmission. 3、The application has multi-level detection and cache ability of data packet completeness; 4、The application realizes the function of SRAM type FPGA on-orbit reconfiguration with modular architecture, provides stronger support for the design and application of satellite load, and greatly improves the reliability of on-orbit satellite and the success rate of task. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is the schematic diagram of the on-orbit reconfiguration system architecture of the satellite-borne SRAM type FPGA program of the application; Figure 2 is the schematic diagram of standard AOS frame format; Figure 3 is the schematic diagram of SRAM type FPGA program loading; Figure 4 is the schematic diagram of uplink satellite-ground link. DETAILED DESCRIPTION

[0017] The application provides an on-orbit reconfiguration system of satellite-borne SRAM type FPGA program, which comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, wherein, The data processing unit comprises a clock management module, a UART control module, a satellite-ground data processing module, an on-satellite data processing module and an SDRAM control module. On one hand, the data processing unit is used for processing satellite-ground data, including intermediate frequency data receiving and demodulation, AOS data frame recovery, data descrambling and LDPC decoding; on the other hand, the data processing unit is used for processing on-satellite data, including AOS frame analysis, uplink data packet recombination and checking, and secondary packaging of uplink data packet; The JFMRS01RH unit, whose core is a JFMRS01RH chip, comprises a clock module, a UART control module, a configuration control module, an FPGA control module and a NOR Flash control module. The JFMRS01RH unit is used for completing JFMRS01RH communication, state monitoring, initialization, data writing and data reading, and task scheduling management; The external cache unit comprises an SDRAM cache and a NOR Flash cache, wherein the SDRAM cache interacts with the data processing unit for caching the recombined uplink data packet on the satellite; and the NOR Flash cache interacts with the JFMRS01RH unit for storing the uplink file loaded to the target FPGA. The target FPGA is a specified model of SRAM type FPGA of Fudan Micro and Xilinx Company.

[0018] The technical solutions of the application will be described in detail below with reference to the drawings and embodiments.

[0019] Embodiment The embodiment of the application provides a satellite-borne SRAM type FPGA program on-orbit reconstruction system, comprising a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA. The target FPGA is any one of JFM4V, JFM7V, JFM7K series of Fudan Micro Company and VIRTEX2, VIRTEX4-7 and KINTEX7 series of Xilinx Company. As shown in the figure. Figure 1 .

[0020] The data processing unit comprises a space-ground data processing module and an on-board data processing module.

[0021] The processing process of the space-ground data processing module comprises: Intermediate frequency signal analysis: receiving an intermediate frequency signal from a satellite, and inputting the intermediate frequency signal into an AD9361 data acquisition chip, frequency capture, carrier synchronization and timing synchronization are performed on the obtained uplink digital signal, so that analog signal to digital signal conversion is completed; AOS frame format recovery: according to the transceiving level, the pilot of the Unnumbered Information Frame (UW) is removed in the receiving time slot, and the standard AOS (Advanced Orbiting Systems) frame format is recovered; descrambling and decoding: the descrambling module receives the data transmission frame of the pilot-removed group AOS frame, and descrambles the original scrambling area; after validity processing of the descrambled effective frame, decoding is performed according to the (8160, 7136) Low-Density Parity-Check Code (LDPC) decoding rule, and the decoded data is output.

[0022] The processing process of the on-board data processing module comprises: Data packet validity detection: if the data packet start information is 0x1ACFFCD, the data packet is regarded as a valid data packet, otherwise, the data packet is regarded as invalid data and discarded; Uploading data packet analysis: the virtual channel identifier in the uploading data packet is extracted and latched, which is used to generate the logical address of the SDRAM, and the data source packet information of the to-be-reconstructed FPGA program is extracted from the AOS transmission frame according to the link protocol; Data packet verification: the uplink data packet is a fixed-length data packet (packet length) except the last packet, and the last packet data length depends on the actual size of the uploading file, so the extracted length field is used to verify and judge the validity of the data, so as to ensure the correctness of the link. The system supports two modes of accumulation and CRC-CCITT, and the selection is performed through instruction configuration. The default is CRC-CCITT; Data packet secondary encapsulation: encapsulate the valid data in the correct upper bet packet into a data packet that meets the programming operation of NOR Flash according to the format required by JFMRS01RH protocol, and send it to JFMRS01RH through UART interface according to the agreed format.

[0023] The system supports data packet reordering. According to the virtual channel identifier and the data packet number, the logical address of the cache is generated, and the physical address is mapped out. The data packet after completion of the check is cached in SDRAM. For the error data packet, on the one hand, the error data packet number is fed back to the ground, and on the other hand, the updated correct data packet is inserted into the original data packet corresponding position in SDRAM. The JFMRS01RH unit uses RS422 serial communication mode to feedback state to the data processing unit, and has the ability of task self-management. The feedback state includes: the refresh state of FPGA, the reload state, the reload and refresh bit stream CRC detection result, the UART command CRC state, the FLASH operation result, the UART processing state and the FIFO data state. The baud rate of communication is 115200bps. The state data packet is composed of the format of "frame header + offset address + 1B data + 2B CRC check + frame tail", and 21 bytes are sent at a time.

[0024] The JFMRS01RH chip needs to be initialized after power on, including FPGA loading mode selection, FLASH peripheral type selection, automatic telemetry control, refresh control, etc. The task scheduling of JFMRS01RH includes FLASH programming task, FLASH erase task, Flash ID monitoring task, Flash bit stream CRC detection task and Flash data read-back task.

[0025] After entering the territory and completing the establishment of satellite-ground link, the satellite first receives the modulated carrier signal transmitted by the ground station. The satellite-ground data processing module in the data processing unit receives the intermediate frequency signal from the satellite and inputs it into the AD9361 data acquisition chip. The uplink digital signal obtained by sampling is subjected to frequency capture, carrier synchronization and timing synchronization, thereby completing the conversion from analog signal to digital signal. Then, according to the transmit-receive level, the pilot of the air interface UW frame is removed in the receiving time slot, and the standard AOS frame format is restored, as shown in Figure 2 The descrambling module receives the data transmission frame sent by the de-pilot AOS frame module and descrambles the original scrambled area. After the valid frame after descrambling is processed for validity, it is decoded according to the decoding rule of (8160, 7136) LDPC code, and the decoded data is output to the on-board data processing module.

[0026] The on-board data processing module first detects the validity of the data packet. If the data packet start information is 0x1ACFFCD, it is considered as a valid data packet, otherwise, it is considered as invalid data and discarded. Then, by analyzing the bet data packet, the virtual channel identifier in the bet data packet is extracted and latched, which is used to generate the logical address of the SDRAM. In the analysis process, the data packet valid information of the FPGA program to be reconstructed is extracted from the AOS transmission frame according to the link protocol, and after the reception is completed, the valid data is checked through the checksum mechanism of the data packet, so as to judge the correctness of the link and the integrity of the data. For the data packet that passes the check, the logical address of the cache is generated according to the virtual channel identifier and the data packet number, and the physical address is mapped, and the bet data packet is cached in the SDRAM. For the error data packet, on the one hand, the error data packet number is fed back to the ground, and on the other hand, the correct data packet updated from the ground is inserted into the corresponding position of the meta data packet in the SDRAM. Finally, the system monitors the state of the JFMRS01RH through the UART control module of the data processing unit. When it has the data writing condition, the program storage area identifier is updated, the valid data in the correct bet packet is packaged into a data packet conforming to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and is sent to the JFMRS01RH unit through the UART interface according to the agreed format. At the same time, the NOR Flash write operation is started, the data packet is cached to the external NOR Flash through the internal independent task management, and the storage area identifier is restored after the data packet caching is completed, so as to complete the caching of the target FPGA bet data packet.

[0027] The on-board data processing module first detects the validity of the data packet. If the data packet start information is 0x1ACFFCD, it is considered as a valid data packet, otherwise, it is considered as invalid data and discarded. Then, by analyzing the bet data packet, the virtual channel identifier in the bet data packet is extracted and latched, which is used to generate the logical address of the SDRAM. In the analysis process, the data packet valid information of the FPGA program to be reconstructed is extracted from the AOS transmission frame according to the link protocol, and after the reception is completed, the valid data is checked through the checksum mechanism of the data packet, so as to judge the correctness of the link and the integrity of the data. For the data packet that passes the check, the logical address of the cache is generated according to the virtual channel identifier and the data packet number, and the physical address is mapped, and the bet data packet is cached in the SDRAM. For the error data packet, on the one hand, the error data packet number is fed back to the ground, and on the other hand, the correct data packet updated from the ground is inserted into the corresponding position of the meta data packet in the SDRAM. Finally, the system monitors the state of the JFMRS01RH through the UART control module of the data processing unit. When it has the data writing condition, the program storage area identifier is updated, the valid data in the correct bet packet is packaged into a data packet conforming to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and is sent to the JFMRS01RH unit through the UART interface according to the agreed format. At the same time, the NOR Flash write operation is started, the data packet is cached to the external NOR Flash through the internal independent task management, and the storage area identifier is restored after the data packet caching is completed, so as to complete the caching of the target FPGA bet data packet. Figure 3 Figure 4 The on-board data processing module first detects the validity of the data packet. If the data packet start information is 0x1ACFFCD, it is considered as a valid data packet, otherwise, it is considered as invalid data and discarded. Then, by analyzing the bet data packet, the virtual channel identifier in the bet data packet is extracted and latched, which is used to generate the logical address of the SDRAM. In the analysis process, the data packet valid information of the FPGA program to be reconstructed is extracted from the AOS transmission frame according to the link protocol, and after the reception is completed, the valid data is checked through the checksum mechanism of the data packet, so as to judge the correctness of the link and the integrity of the data. For the data packet that passes the check, the logical address of the cache is generated according to the virtual channel identifier and the data packet number, and the physical address is mapped, and the bet data packet is cached in the SDRAM. For the error data packet, on the one hand, the error data packet number is fed back to the ground, and on the other hand, the correct data packet updated from the ground is inserted into the corresponding position of the meta data packet in the SDRAM. Finally, the system monitors the state of the JFMRS01RH through the UART control module of the data processing unit. When it has the data writing condition, the program storage area identifier is updated, the valid data in the correct bet packet is packaged into a data packet conforming to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and is sent to the JFMRS01RH unit through the UART interface according to the agreed format. At the same time, the NOR Flash write operation is started, the data packet is cached to the external NOR Flash through the internal independent task management, and the storage area identifier is restored after the data packet caching is completed, so as to complete the caching of the target FPGA bet data packet.

[0028] ​The JFMRS01RH unit adopts RS422 serial port communication mode to feed back states to the data processing unit, the states include: refresh state, reloading state, reloading and refresh bit stream CRC detection result, UART command CRC state, FLASH operation result, UART processing state and FIFO data state, the baud rate of communication is 115200bps, the state data packet is composed of the format of "frame header+offset address+1B data+2B CRC check+frame tail", 21 bytes are sent once.

[0029] It is worth noting that the embodiments of the above system include various modules only according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of each functional module are only for easy differentiation, and are not used to limit the protection scope of the present application.

[0030] Finally, it should be explained that the above embodiments are only used to illustrate the technical solutions of the present application and are not limited. Although the present application has been described in detail with reference to the embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A system for on-orbit reconfiguration of a space-borne SRAM-based FPGA program, characterized in that, The system comprises a data processing unit, a JFMRS01RH unit, an external storage unit and a target FPGA, wherein, The data processing unit comprises a satellite-ground data processing module and an on-satellite data processing module, the satellite-ground data processing module is configured to receive intermediate frequency signals from the satellite, perform demodulation, AOS data frame recovery, data descrambling and LDPC decoding; the on-satellite data processing module is configured to sequentially perform AOS data frame analysis, uplink data packet reorganization, checksum secondary packaging and transmission to the JFMRS01RH unit; The JFMRS01RH unit is configured to receive the uplink data packet after secondary packaging by the data processing unit, perform state monitoring and feedback the state to the data processing unit, and perform task scheduling management; The external storage unit is configured to cache the uplink data packet after reorganization, and store the uplink file to be loaded to the target FPGA; The target FPGA is configured to provide logical control and algorithm implementation for the load of the on-orbit satellite.

2. The on-orbit reconfiguration system of a space-borne SRAM-type FPGA program according to claim 1, characterized in that, The processing process of the satellite-ground data processing module comprises: Receiving intermediate frequency signals from the satellite, sampling, frequency acquisition, carrier synchronization and timing synchronization of the uplink digital signals obtained by sampling, thereby completing the conversion from analog signals to digital signals; According to the transceiver level, removing the pilot of the air interface non-numbered information frame in the receiving time slot, and restoring to the standard AOS frame format; Receiving the data transmission frame of the de-pilot group AOS frame, descrambling the original scrambled area, performing validity processing on the descrambled effective frame, performing LDPC decoding according to the decoding rule of (8160, 7136) low density parity check code, and outputting the decoded data and the instructions from the ground to the on-satellite data processing module.

3. The on-orbit reconfiguration system of a space-borne SRAM-type FPGA program according to claim 1, characterized in that, The processing process of the on-satellite data processing module comprises: Performing validity detection on the data packet, judging whether the starting information of the data packet is correct, and if yes, the data packet is valid, otherwise, the data packet is invalid and is discarded; Extracting and latching the virtual channel identifier in the uplink data packet, for generating the logical address of SDRAM, and extracting the data source packet information of the FPGA program to be reconstructed from the AOS transmission frame according to the link protocol; Extracting the length field of the valid data packet, performing check judgment; if the data packet is correct, generating the logical address of the cache according to the virtual channel identifier and the data packet number, and mapping out the physical address, caching the uplink data packet in the SDRAM; if the data packet is incorrect, feeding back the data packet number to the ground, waiting for the ground to return the updated correct data packet, generating the logical address of the cache according to the virtual channel identifier and the data packet number, and mapping out the physical address, thereby caching to the corresponding position of the SDRAM; Packaging the valid data packet into a data packet conforming to the programming operation of NOR Flash according to the format required by the JFMRS01RH protocol, and sending to the JFMRS01RH unit through the UART interface according to the agreed format.

4. The on-board SRAM-type FPGA program in-orbit reconfiguration system according to claim 3, characterized in that, The data processing unit further comprises a clock management module, a UART control module and an SDRAM control module; wherein, The clock management module is configured to generate clock signals for the satellite-ground data processing module and the on-board data processing module according to the clock frequency of the external crystal oscillator, and provide the clock signals to the JFMRS01RH unit; The UART control module is configured to send instruction information to the JFMRS01RH unit and receive state information fed back by the JFMRS01RH unit; The SDRAM control module is configured to schedule and control the external SDRAM chip, which is configured to provide cache for the on-orbit reconfiguration file of the target FPGA received by the on-board data processing module.

5. The on-board SRAM-type FPGA program in-orbit reconfiguration system according to claim 4, characterized in that, The JFMRS01RH unit comprises a clock module, a UART control module, a configuration control module, an FPGA control module and a NOR Flash control module, wherein, The clock module is configured to receive clock signals from the clock management module of the data processing unit and generate clock signals of different frequencies for other modules in the JFMRS01RH unit; The UART control module is configured to receive and analyze instruction information from the data processing unit and feed back state information to the UART control module of the data processing unit; The configuration control module is configured to detect the model, interface mode and interface connection mode of the target FPGA, detect and count whether the target FPGA appears readback error and / or refresh error due to single particle function interruption event in the refreshing and loading process, and configure the refreshing and readback mode, refreshing and readback time interval of the target FPGA; The FPGA control module is configured to configure the bit stream of the target FPGA according to the predetermined process. The NOR Flash control module is configured to monitor the state of the JFMRS01RH unit, update the program storage area identifier when the data writing condition is met, encapsulate the valid data in the correct injection data packet into a data packet conforming to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and send the data packet to the JFMRS01RH unit through the UART interface according to the agreed format, and start the NOR Flash writing operation.

6. The on-board SRAM-type FPGA program in-orbit reconfiguration system according to claim 1, characterized in that, The JFMRS01RH unit feeds back the state to the data processing unit in the RS422 serial communication mode, the feedback state comprises the refreshing state, reloading state, reloading and refreshing bit stream CRC detection result, UART command CRC state, FLASH operation result, UART processing state and FIFO data state of the FPGA, the baud rate of the communication is 115200bps, the format of the state data packet is frame header+offset address+1B data+2B CRC check+frame tail, and 21 bytes are sent at a time.

7. The on-board SRAM-type FPGA program in-orbit reconfiguration system according to claim 1, characterized in that, The external storage unit comprises an SDRAM buffer and a NOR Flash buffer, wherein, The SDRAM buffer interacts with the data processing unit for data, and is configured to cache the recombined injection data packet on board. The NOR Flash cache interacts with a JFMRS01RH unit for storing the loading files of the target FPGA.

8. The on-board SRAM-type FPGA program in-orbit reconfiguration system according to claim 1, characterized in that, The target FPGA is any one of JFM4V, JFM7V, JFM7K series of Fudan Micro Company and VIRTEX2, VIRTEX4-7 and KINTEX7 series of Xilinx Company.

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