Control circuit, control system and wiring method

Abstract

The invention relates to the technical field of communication, and particularly discloses a control circuit, a control system and a wiring method, which adopt a mode of controlling a plurality of slave equipment units by one main control unit, reduce the number of pins of the main control unit and the number of independent control lines required to be led out from the main control unit, simplify the wiring complexity of an area close to the main control unit, and improve the wiring efficiency. And the development cost is reduced. In addition, by selectively installing resistors on the parallel slave lines or the serial connection points, two control modes can be flexibly selected, one mode is to carry out data transmission by utilizing a serial cascade path, and the other mode is to control the slave equipment by adopting a fly-by mode. The dual-mode compatibility can effectively manage and control a plurality of slave equipment units and improve the compatibility, and is particularly suitable for a one-drive-multiple large-scale array control scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a control circuit, a control system and a wiring method. BACKGROUND

[0002] With the continuous development of large-scale phased array, large-scale device array and other application scenarios, it is often necessary to integrate and manage a large number of slave device units, such as beam control chips, on a single control board. One of the commonly used control interfaces is the serial peripheral interface (SPI), but the existing control method exposes some problems when facing large-scale applications.

[0003] Firstly, a large number of slave device units mean a large total number of SPI interface pins, which requires the master control unit to have enough control pins. This not only increases the selection limitation of the master control unit, but also leads to an increase in the layout area of the master control unit and consumes more PCB (printed circuit board) space, which increases the design complexity and cost for design scenarios with limited single board area or pursuit of miniaturization.

[0004] Secondly, in order to connect the SPI signal lines of the master control unit and the numerous slave device units, the PCB wiring becomes complex, and therefore, more wiring layers may be needed.

[0005] Thirdly, different manufacturers' slave device chips may have compatible pins but different required SPI communication modes, which leads to a lack of compatibility in the existing hardware connection scheme and reduces the flexibility of the design.

[0006] To solve the above problems, some solutions are disclosed in the prior art. Please refer to Figure 1 Chinese patent application with publication number CN112000610A uses broadcast address matching to achieve one-to-many (one group of master control interface driving multiple groups of slave devices, slave devices >= 2 groups of scenarios), but its design lacks compatibility for different SPI communication modes and is aimed at three-wire SPI (serial peripheral interface) with less pin requirement. Please refer to Figure 2 Chinese patent application with publication number CN116566441A uses

[0007] LVDS (low voltage differential signal) bus control beam, but it must additionally increase the LVDS serial-parallel conversion circuit, introducing additional system complexity. Please refer to Figure 3 Chinese patent application with publication number CN110932748A proposes an improved SPI interface, which aims to reduce the number of interfaces, but requires the slave device to support a specific ID tag protocol rather than a general SPI protocol, which limits the range of chip selection. It can be seen that the prior art still has deficiencies in compatibility, system simplicity or protocol universality. SUMMARY

[0008] The application aims to provide a control circuit, a control system and a wiring method, which are compatible with two SPI communication modes, improve hardware compatibility and reduce wiring complexity.

[0009] A control circuit comprises a master control unit, n slave device units, n first serial interface slave lines and n second serial interface slave lines.

[0010] The serial data output end of the master control unit is connected to the serial data input ends of the first to nth slave device units through the first serial interface slave lines.

[0011] The serial data input end of the master control unit is connected in parallel to the serial data output ends of the first to nth slave device units through the second serial interface slave lines.

[0012] A first resistor is arranged on the first serial interface slave line, and the first resistor is located between the serial data output end of the current slave device unit and the serial data input end of the next slave device unit.

[0013] The second resistor is also arranged on the second serial interface slave line and located between the serial data output end of the current slave device unit and the serial data input end of the next slave device unit.

[0014] The n is an integer, and n≥2.

[0015] Further, the control circuit further comprises a second resistor.

[0016] The second resistor is arranged between the serial data output end of the current slave device unit and the serial data input end of the next slave device unit.

[0017] Further, a first serial interface bus is further included.

[0018] The first serial interface bus is connected to the first serial interface slave lines and input to the serial data input ends of the n slave device units through the first serial interface slave lines.

[0019] The first resistor is also arranged on the first serial interface slave line and located between the serial data output end of the master control unit and the serial data input end of the first slave device unit.

[0020] Further, a second serial interface bus is further included.

[0021] The first serial interface bus is connected to the second serial interface slave lines and input to the serial data output ends of the n slave device units through the second serial interface slave lines.

[0022] The first resistor is also arranged on the second serial interface slave line between the serial data output end of the nth slave device unit and the serial data input end of the master control unit.

[0023] Further, the clock signal output line and the chip select signal output line are further included.

[0024] Further, the n clock signal output slave lines and the n chip select signal output slave lines are further included.

[0025] The clock signal output end of the master control unit is connected in parallel to the clock signal input end of the n slave device units through the n clock signal output slave lines.

[0026] The chip select signal output end of the master control unit is connected in parallel to the chip select signal input end of the n slave device units through the n chip select signal output slave lines.

[0027] Further, the third resistor is arranged on the serial data input end, the serial data output end, the clock signal output end and the chip select signal output end of the master control unit.

[0028] The third resistor is also arranged on the clock signal output slave line and the chip select signal output slave line.

[0029] Further, the master control unit is an FPGA or an MCU.

[0030] Further, the plurality of slave device units in the control circuit are arranged in sequence in the horizontal or vertical direction, or the plurality of slave device units are arranged in an array.

[0031] Further, the signal lines in the control circuit are respectively arranged in the same two physical layers in the substrate.

[0032] On the other hand, the application also discloses a control system, including the above-mentioned control circuit, and a plurality of groups of the control circuit are arranged in sequence in the horizontal or vertical direction.

[0033] On the other hand, the application also discloses a control system wiring method, the method comprising:

[0034] A main path line is arranged on one of the physical layers and is led out from each control end of the master control unit, wherein the main path lines are arranged in parallel.

[0035] When the slave device unit and the nearest master control unit have a wiring obstacle, the via is switched to another physical layer to connect with the master control unit.

[0036] Compared with the prior art, the application has at least the following technical effects:

[0037] The application discloses a control circuit, which reduces the number of independent control lines needed to be drawn from a master control unit to control multiple slave device units, reduces the wiring complexity in the area close to the antenna, i.e. the slave device area. In addition, when the fly-by mode is not used, the signal quality in serial connection can be improved by cutting off the empty network between the first resistors, so as to improve the communication rate of SPI (serial peripheral interface) mode communication.

[0038] Further, by selectively installing resistors on the parallel slave lines or serial connection points, two control modes can be flexibly selected: one is to use the serial cascade path for data transmission, and the other is to use the fly-by mode for control. This dual-mode compatibility can effectively control multiple slave device units and improve compatibility, and is particularly suitable for one-drive-multiple large-scale array control scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 It is a structural schematic diagram of a control circuit in the prior art;

[0040] Figure 2 It is a structural schematic diagram of another control circuit in the prior art;

[0041] Figure 3 It is a structural schematic diagram of still another control circuit in the prior art;

[0042] Figure 4 It is a structural schematic diagram of a control circuit in the embodiment one of the application;

[0043] Figure 5 It is another structural schematic diagram of a control circuit in the embodiment one of the application;

[0044] Figure 6 It is a wiring schematic diagram of a control circuit in the embodiment one of the application;

[0045] Figure 7 It is another wiring schematic diagram of a control circuit in the embodiment one of the application;

[0046] Figure 8 It is a wiring schematic diagram of a control system in the embodiment two of the application;

[0047] Figure 9 It is another wiring schematic diagram of a control system in the embodiment two of the application;

[0048] Figure 10 It is another wiring schematic diagram of a control system in the embodiment two of the application;

[0049] Figure 11 It is another wiring schematic diagram of a control system in the embodiment two of the application. Detailed Implementation

[0050] The following description, with reference to schematic diagrams, illustrates a control circuit, control system, and wiring method of the present invention, which represent preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0051] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0052] Example 1

[0053] Please refer to Figure 4 The present invention provides a control circuit, the control circuit comprising: a master control unit, n slave device units, n first serial interface slave lines, n second serial interface slave lines, and a first resistor R1.

[0054] The serial data output terminal SDO of the master control unit is connected in parallel to the serial data input terminals SDI of the first to nth slave device units via the first serial interface.

[0055] The serial data input terminal SDI of the master control unit is connected in parallel to the serial data output terminals SDO of the first to nth slave device units via the second serial interface.

[0056] The first resistor R1 is also provided on the first serial interface slave line, located between the serial data output terminal SDO of the current slave device unit and the serial data input terminal SDI of the next slave device unit.

[0057] Additionally, it is located on the second serial interface slave line, between the serial data output terminal SDO of the current slave device unit and the serial data input terminal SDI of the next slave device unit.

[0058] Wherein, n is an integer, n≥2.

[0059] In the embodiment, the control circuit reduces the number of independent control lines to be drawn from the master unit, and reduces the wiring complexity in the area close to the antenna, i.e., the slave device area, by controlling a plurality of slave device units with a master unit. In addition, when the fly-by mode is not used, the signal quality in serial connection can be improved by cutting off the empty network between the first resistors, thereby improving the communication rate of the SPI mode communication.

[0060] Further, the embodiment also includes a first serial interface bus.

[0061] The first serial interface bus is connected to the first serial interface slave line, and serial data input ends SDI of n slave device units are input to the first serial interface slave line.

[0062] The first resistor R1 is also provided on the first serial interface slave line, between the serial data output end SDO of the master unit and the serial data input end SDI of the first slave device unit.

[0063] Further, in the embodiment, please refer to Figure 4 , a second serial interface bus is also included.

[0064] The second serial interface bus is drawn from the serial data input end SDI of the master unit, and input to the serial data output end SDO of the first slave device unit.

[0065] A plurality of second serial interface slave lines are provided on the second serial interface bus.

[0066] The first resistor R1 is also provided on the second serial interface bus, between the serial data output end SDO of the nth slave device unit and the serial data input end SDI of the master unit.

[0067] In the embodiment, the resistance value of the first resistor R1 can be 0 ohm. In the case of good signal quality, a 0 ohm resistor (equivalent to a short circuit) can be used to minimize the attenuation of the signal; and in the case of optimizing the signal edge and suppressing overshoot, a suitable resistance value can be used according to the actual test situation. In addition, in the control circuit provided in the embodiment, the resistance values of the first resistors R1 do not need to be consistent, and can also be independently configured.

[0068] Further, please refer to Figure 5 , the circuit also includes a second resistor R2.

[0069] The second resistor R2 is provided between the serial data output end SDO of the current slave device unit and the serial data input end SDI of the next slave device unit.

[0070] In this embodiment, when a first resistor R1 is set on the first serial interface slave line and the second serial interface slave line, a parallel fly-by communication mode can be realized. When a second resistor R2 is set between the serial data output terminal SDO and the serial data input terminal SDI of adjacent slave device units, a serial daisy-chain communication mode can be realized.

[0071] Those skilled in the art will understand that, in fly-by communication mode, the serial data output terminal SDO of the master control unit is simultaneously connected to the serial data input terminals SDI of all n slave device units via the first serial interface slave line, allowing the master control unit to broadcast data to all slave devices. Simultaneously, the serial data output terminals SDO of all n slave device units are also connected in parallel back to the serial data input terminal SDI of the master control unit via the second serial interface slave line, providing a physical path for parallel data reading. In serial daisy-chain communication mode, the data sent by the master control unit first enters the first slave device, then sequentially passes through the serial data path of each slave device to the next slave device, and finally returns to the master control unit from the serial data output terminal of the nth slave device, forming a long shift register containing all devices.

[0072] As can be seen, the above control circuit can flexibly select two control modes by selectively installing resistors on the parallel slave line or the serial connection point: one is to use a serial cascaded path for data transmission, and the other is to use a serial interface slave line for control. This dual-mode compatibility can effectively manage multiple slave device units, and is particularly suitable for large-scale array control scenarios where one device drives multiple others.

[0073] In one specific example, the number of slave device units is 8 ( Figure 4 and Figure 5 As shown in IC1-IC8), the number of the first serial interface slave line and the second serial interface slave line is also 8. Those skilled in the art can choose the number of slave device units according to the actual situation; no specific limitation is made here. For example, 2, 3, 4, 6, 10, 12 or more slave device units can be selected, and thus the number of the first serial interface slave line and the second serial interface slave line will also be 2, 3, 4, 6, 10, 12, etc., respectively.

[0074] In another specific example, the slave device unit is a microchip.

[0075] Furthermore, in this embodiment, it also includes: n clock signal output slave lines and n chip select signal output slave lines.

[0076] Specifically, the clock signal output end CLK of the master control unit is connected in parallel to the clock signal input ends CLK of the n slave device units through n clock signal output slave lines.

[0077] In the embodiment, the timing consistency of data transmission is achieved by synchronously distributing the clock signal of the master control unit to all slave devices; meanwhile, the unified enablement or selection of all slave devices is achieved by the parallel chip select signal, thereby providing basic control for the communication mode requiring the collaborative work of all devices.

[0078] In one specific example, a clock signal output bus and a chip select signal output bus are further included; the clock signal output bus is led out from the clock signal output end CLK_OUT of the master control unit and connected to the clock signal input ends CLK_IN of the n slave device units through clock signal output slave lines. The chip select signal output bus is led out from the chip select signal output end CS_OUT of the master control unit and connected to the chip select signal input ends CS_IN of the n slave device units through chip select signal output slave lines.

[0079] In the embodiment, the clock signal output slave lines and the chip select signal output slave lines are connected to all slave device units in parallel. This means that no signal line needs to be separately led out from each slave device, thereby reducing the number of backbone lines and saving the wiring space.

[0080] It can be understood that the specific number of the clock signal output slave lines and the chip select signal output slave lines also depends on the number of slave device units, such as 2, 3, 4, 6 or 8, etc.

[0081] Further, in the embodiment, a third resistor R3 is further included.

[0082] Specifically, the third resistor R3 is arranged at the serial data input end SDI, the serial data output end SDO, the clock signal output end CLK_OUT and the chip select signal output end CS_OUT of the master control unit.

[0083] In addition, the third resistor R3 is also arranged on the clock signal input branch line and the chip select signal input branch line.

[0084] In the embodiment, the main role of the third resistor R3 is to improve the quality and integrity of high-speed signals. By matching the output impedance of the driving end of the master control unit with the characteristic impedance of the transmission line, the reflection, ringing or overshoot phenomena that may occur in the transmission process of signals can be effectively suppressed, thereby improving the signal quality.

[0085] On the basis of setting the third resistor R3, the control circuit disclosed in the embodiment can work at a clock frequency greater than 50 MHz, for example. When the control circuit works at a frequency greater than 50 MHz, it means that the circuit can update the settings or read the state of the microchip faster, thereby realizing faster beam scanning, target tracking or system configuration, and improving the performance and efficiency of the entire array system.

[0086] Further, in the embodiment, the master control unit is an FPGA (field programmable gate array) or an MCU (microcontroller).

[0087] Further, in the embodiment, the plurality of slave device units in the control circuit are arranged in sequence in the horizontal or vertical direction; or, the plurality of slave device units are arranged in an array.

[0088] In the embodiment, all the signal wires (including the first serial interface wire, the second serial interface wire, the clock signal output wire and the chip select signal output wire, etc.) in the control circuit can be laid on the same physical layer of the same substrate.

[0089] In addition, please refer to Figure 6 , Figure 6 The wiring diagram of the control circuit compatible with the fly-by communication mode and the serial communication mode, wherein the wire 100 (black thin line shown in the figure) is a wire located on one physical layer of the PCB, the wire 200 (black thick line shown in the figure) is a wire located on another physical layer of the PCB, and the via 300 is used to connect the wire 100 and the wire 200. The first resistor R1, the second resistor R2 and the third resistor R3 are located on the surface layer of the PCB, and the wire 100 and the wire 200 are connected by vias (not shown in the figure).

[0090] Figure 7 The SPI daisy chain communication topology diagram in the embodiment, used to control an array composed of 16 ICs; the signal bus from the FPGA is connected in series in the form of a "daisy chain" to access the entire column of electronic elements. Among them, the wire 100 (black thin line shown in the figure) is a wire located on one physical layer of the PCB, the wire 200 (black thick line shown in the figure) is a wire located on another physical layer of the PCB, and the via 300 is used to connect the wire 100 and the wire 200.

[0091] It can be understood that those skilled in the art can select the distribution mode of the wire according to the actual application demand, space layout, signal isolation, cost or other design considerations.

[0092] In a specific embodiment, the substrate is a PCB (printed circuit board).

[0093] Embodiment two

[0094] The embodiment discloses a control system, including multiple groups of control circuits disclosed in the embodiment one, specifically, please refer to Figure 8-9 , multiple groups of the control circuit are arranged in sequence along the horizontal or vertical direction, thereby forming an array arrangement.

[0095] Please refer to the wiring diagram of the control system shown in Figure 8 , it directly connects each element in the array with its adjacent unit above, below, left and right by distributing horizontal and vertical lines on different PCB layers and connecting them with vias.

[0096] Please refer to another wiring diagram of the control system shown in Figure 9 , compared with Figure 8 , the intra-row connection in the horizontal direction in this design is basically unchanged, but the communication bus (line 200) in the vertical direction is no longer served for a single column, but is shared by adjacent two columns of elements.

[0097] Please refer to another wiring diagram of the control system shown in Figure 10 , the signal bus from the FPGA is connected in series in the form of "daisy chain" to access a whole column of electronic elements.

[0098] Please refer to another wiring diagram of the control system shown in Figure 11 , the whole element array is divided into two parts, and the signal bus is routed from the middle position to "fly" up and down.

[0099] In Figure 8-11 , the line 100 (black thin line shown in the figure) is a line on one of the physical layers of the PCB, the line 200 (black thick line shown in the figure) is a line on another physical layer of the PCB, and the via 300 is used to connect the line 100 and the line 200.

[0100] In the embodiment, multiple slave device units in the control circuit can be arranged in sequence along the horizontal or vertical direction; or, multiple slave device units are arranged in an array. Thus, the overall control system is arranged in an array, thereby optimizing the space utilization and simplifying the wiring difficulty. At the same time, the regular column / row arrangement helps to simplify the wiring path, so that the power line, ground line and various signal lines can be connected in a more orderly and shorter way, reducing the wiring complexity.

[0101] In this embodiment, the control system is suitable for scenarios that require processing large amounts of repetitive or parallel data. Typical applications include high-density memory modules (such as DRAM / NAND arrays in servers, solid-state hard drives), large LED display screen driving systems, image sensing or processing arrays (such as digital cameras, industrial vision sensors), and multi-point data acquisition and control systems in industrial automation that require dense deployment of sensors or actuators to achieve compact, efficient, and scalable solutions.

[0102] Embodiment Three

[0103] The embodiment discloses a control circuit board wiring method for wiring the control circuit disclosed in Embodiment One, characterized in that the method comprises:

[0104] A main path line is arranged on one of the physical layers and led out from each control end of the master unit, wherein the main path lines are arranged in parallel. The slave device unit is connected to the master unit through the main path line on the same physical layer. When the slave device unit is obstructed from being connected to the master unit, the slave device unit is switched to another physical layer through a via hole to be connected to the master unit.

[0105] In this embodiment, the PCB wiring method is suitable for chips or modules arranged in an array. Parallel main path lines are arranged on the main physical layer as the backbone, and the slave device is preferentially connected to the master unit on the same layer to improve efficiency. When the wiring is obstructed by a wire or an element, the slave device is switched to another physical layer through a via hole to complete the connection. This strategy optimizes high-density wiring and improves signal quality and manufacturability.

[0106] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A control circuit, characterized by The control circuit comprises: a master unit, n slave units, n first serial interface slave lines, n second serial interface slave lines and a first resistor R1; a serial data output end of the master unit is connected to serial data input ends of the first to nth slave units through the first serial interface slave lines; serial data input ends of the master unit are connected to serial data output ends of the first to nth slave units through the second serial interface slave lines in parallel; a first resistor is arranged on the first serial interface slave line between a serial data output end of a current slave unit and a serial data input end of a next slave unit; a second resistor is also arranged on the second serial interface slave line between the serial data output end of the current slave unit and the serial data input end of the next slave unit; wherein n is an integer, n≥2.

2. The control circuit of claim 1, wherein, The control circuit further comprises a second resistor; the second resistor is arranged between the serial data output end of the current slave unit and the serial data input end of the next slave unit.

3. The control circuit of claim 2, further comprising: a first serial interface bus; the first serial interface bus is connected to the first serial interface slave lines and is input to serial data input ends of the n slave units through the first serial interface slave lines; the first resistor is also arranged on the first serial interface slave line between a serial data output end of the master unit and a serial data input end of the first slave unit.

4. The control circuit of claim 3, wherein, Further comprising: a second serial interface bus; the first serial interface bus is connected to the second serial interface slave lines and is input to serial data output ends of the n slave units through the second serial interface slave lines; the first resistor is also arranged on the second serial interface slave line between a serial data output end of the nth slave unit and a serial data input end of the master unit.

5. The control circuit of claim 3, wherein, Further comprising: n clock signal output slave lines and n chip select signal output slave lines; a clock signal output end of the master unit is connected to clock signal input ends of the n slave units through the n clock signal output slave lines in parallel; a chip select signal output end of the master unit is connected to chip select signal input ends of the n slave units through the n chip select signal output slave lines in parallel.

6. The control circuit of claim 5, wherein, Further comprising: a third resistor; the third resistor is arranged at serial data input ends, serial data output ends, clock signal output ends and chip select signal output ends of the master unit; the third resistor is also arranged on the clock signal output slave lines and the chip select signal output slave lines.

7. The control circuit of claim 1, wherein, The master unit is an FPGA or an MCU.

8. The control circuit of claim 1, wherein, The n slave units in the control circuit are arranged in sequence in a horizontal or vertical direction; or, the n slave units are arranged in an array.

9. The control circuit of claim 7, wherein, Signal wires in the control circuit are arranged in the same two physical layers in the substrate respectively.

10. A control system characterized by, The wiring method comprises:

11. A control system wiring method for wiring the control system of claim 10, characterized by, ​ The main path lines are arranged in parallel between the control terminals of the master unit on one physical layer; The slave units are connected to the master unit through the main path lines on the same physical layer; When there is a wiring obstacle between the slave unit and the nearest master unit, the slave unit is connected to the master unit through a via hole on another physical layer.

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