Capacitor structure and capacitance value adjusting method of capacitor structure

Abstract

The embodiment of the invention provides a capacitor structure and a capacitance value adjusting method of the capacitor structure. The capacitor structure comprises n conductive structures, the n conductive structures are stacked along a first direction, each conductive structure comprises a first conductive pattern and a second conductive pattern which are arranged along a second direction, and the first conductive pattern and the second conductive pattern in each conductive structure form an interdigital structure; wherein the two first conductive patterns in the two conductive structures which are adjacently arranged in the first direction are at least partially overlapped, and the two second conductive patterns in the two conductive structures which are adjacently arranged in the first direction are at least partially overlapped; the first direction is perpendicular to the second direction, and n is an integer larger than 1.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and include but are not limited to a capacitor structure and a method for adjusting capacitance of a capacitor structure. BACKGROUND

[0002] Capacitor structures are basic components in the field of semiconductor technology. Metal-oxide-metal (MOM) capacitor structures and metal-insulator-metal (MIM) capacitor structures are widely used in various chips. MOM capacitor structures include metal layers in the same layer, and two electrodes are formed at the same time. Therefore, the capacitance of the MOM capacitor structure is the capacitance between the metal layers in the same layer. MIM capacitor structures include metal layers in different layers, and two electrodes are formed respectively. Therefore, the capacitance of the MIM capacitor structure is the capacitance between the metal layers in different layers. SUMMARY

[0003] Therefore, embodiments of the present disclosure provide a capacitor structure and a method for adjusting capacitance of a capacitor structure.

[0004] In a first aspect, embodiments of the present disclosure provide a capacitor structure, which includes: n conductive structures, the n conductive structures are arranged in a stack along a first direction, each of the conductive structures includes a first conductive pattern and a second conductive pattern arranged along a second direction, the first conductive pattern and the second conductive pattern in each of the conductive structures form an interdigital structure; wherein two first conductive patterns in two conductive structures arranged adjacent along the first direction at least partially overlap, two second conductive patterns in two conductive structures arranged adjacent along the first direction at least partially overlap; the first direction and the second direction are perpendicular to each other, and n is an integer greater than 1.

[0005] In some embodiments, the capacitor structure includes n first sub-capacitor structures, (n-1) second sub-capacitor structures, and (n-1) third sub-capacitor structures; wherein the first sub-capacitor structure is formed between the first conductive pattern and the second conductive pattern in each of the conductive structures; the second sub-capacitor structure is formed between two first conductive patterns in two conductive structures arranged adjacent along the first direction; and the third sub-capacitor structure is formed between two second conductive patterns in two conductive structures arranged adjacent along the first direction.

[0006] In some embodiments, the n conductive structures include a first conductive structure and a second conductive structure arranged opposite along the first direction; the capacitance structure further includes: (n-1) first adjustable resistance sets, each of the first adjustable resistance sets including a first adjustable resistance and a second adjustable resistance, two ends of each of the first adjustable resistances being respectively used for connecting two of the first conductive patterns in two of the conductive structures arranged adjacent along the first direction, two ends of each of the second adjustable resistances being respectively used for connecting two of the second conductive patterns in the two of the conductive structures arranged adjacent along the first direction; a second adjustable resistance set, the second adjustable resistance set including a third adjustable resistance and a fourth adjustable resistance, two ends of the third adjustable resistance being respectively used for connecting the first conductive pattern in the first conductive structure and a ground voltage, two ends of the fourth adjustable resistance being respectively used for connecting the second conductive pattern in the first conductive structure and the ground voltage; a third adjustable resistance set, the third adjustable resistance set including a fifth adjustable resistance and a sixth adjustable resistance, two ends of the fifth adjustable resistance being respectively used for connecting the first conductive pattern in the second conductive structure and a first voltage node, two ends of the sixth adjustable resistance being respectively used for connecting the second conductive pattern in the second conductive structure and a second voltage node.

[0007] In some embodiments, the first conductive pattern includes: a first connecting portion extending along a third direction; a plurality of first tooth portions extending along a second direction, the first tooth portions including first end portions and second end portions arranged opposite along the second direction, the first end portions of the plurality of first tooth portions being connected with the first connecting portion; the second conductive pattern includes: a second connecting portion extending along the third direction; a plurality of second tooth portions extending along the second direction, the second tooth portions including third end portions and fourth end portions arranged opposite along the second direction, the third end portions of the plurality of second tooth portions being connected with the second connecting portion; wherein the second end portions of the plurality of first tooth portions are towards the second connecting portion, and the fourth end portions of the plurality of second tooth portions are towards the first connecting portion.

[0008] In some embodiments, projections of two of the first conductive patterns in two of the conductive structures arranged adjacent along the first direction on a plane perpendicular to the first direction coincide; projections of two of the second conductive patterns in the two of the conductive structures arranged adjacent along the first direction on the plane perpendicular to the first direction coincide.

[0009] In some embodiments, the method is used to adjust the total capacitance of a capacitor structure as described in the first aspect of this disclosure, the method comprising: providing n voltage groups, each voltage group including a first voltage and a second voltage; wherein the n conductive structures and the n voltage groups correspond one-to-one; applying n first voltages to the n first conductive patterns respectively, and applying n second voltages to the n second conductive patterns respectively.

[0010] In some embodiments, the first voltage and the second voltage in each voltage group are different; the two first voltages applied to two first conductive patterns arranged adjacent to each other along the first direction are different, and the two second voltages applied to two second conductive patterns arranged adjacent to each other along the first direction are different; wherein, the total capacitance of the capacitor structure includes the capacitance of n first sub-capacitor structures, the capacitance of (n-1) second sub-capacitor structures, and the capacitance of (n-1) third sub-capacitor structures; a first sub-capacitor structure is formed between the first conductive pattern and the second conductive pattern in each conductive structure; a second sub-capacitor structure is formed between two first conductive patterns in two conductive structures arranged adjacent to each other along the first direction; and a third sub-capacitor structure is formed between two second conductive patterns in two conductive structures arranged adjacent to each other along the first direction.

[0011] In some embodiments, the first voltage and the second voltage in each voltage group are different; the two first voltages applied to two first conductive patterns arranged adjacent to each other along the first direction are different, and the two second voltages applied to two second conductive patterns arranged adjacent to each other along the first direction are the same; wherein, the total capacitance of the capacitor structure includes the capacitance of n first sub-capacitor structures and the capacitance of (n-1) second sub-capacitor structures; a first sub-capacitor structure is formed between the first conductive pattern and the second conductive pattern in each conductive structure; a second sub-capacitor structure is formed between two first conductive patterns in two conductive structures arranged adjacent to each other along the first direction.

[0012] In some embodiments, the first voltage and the second voltage in each voltage group are different; the two first voltages applied to two first conductive patterns arranged adjacent to each other along the first direction are the same, and the two second voltages applied to two second conductive patterns arranged adjacent to each other along the first direction are the same; wherein, the total capacitance of the capacitor structure includes the capacitance of n first sub-capacitor structures; the first sub-capacitor structure is formed between the first conductive pattern and the second conductive pattern in each conductive structure.

[0013] In some embodiments, the first voltage and the second voltage in each of the voltage groups are the same; two first voltages applied to two first conductive patterns arranged adjacent along the first direction are different, and two second voltages applied to two second conductive patterns arranged adjacent along the first direction are different; wherein the total capacitance of the capacitor structure includes capacitances of (n-1) second sub-capacitor structures and (n-1) third sub-capacitor structures; the second sub-capacitor structure is formed between two first conductive patterns in two conductive structures arranged adjacent along the first direction; the third sub-capacitor structure is formed between two second conductive patterns in two conductive structures arranged adjacent along the first direction.

[0014] The embodiments of the present disclosure provide a capacitor structure and a method for adjusting the capacitance of the capacitor structure. In the embodiments of the present disclosure, in a first aspect, the capacitor structure includes a MOM capacitor and a MIM capacitor, and the MOM capacitor is formed between a first conductive pattern and a second conductive pattern in the same conductive structure; the MIM capacitor is formed between two conductive structures arranged adjacent along a first direction; thus, the density of the capacitor structure can be increased. In a second aspect, n first voltages can be applied to n first conductive patterns respectively, and n second voltages can be applied to n second conductive patterns respectively, and the total capacitance of the capacitor structure can be dynamically adjusted by adjusting the n first voltages and the n second voltages, thereby increasing the flexibility of circuit design and use. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A three-dimensional structural schematic diagram of the capacitor structure provided by the embodiments of the present disclosure is shown in the figure; Figure 2 A top view structural schematic diagram of the conductive structure provided by the embodiments of the present disclosure is shown in the figure; Figure 3 A cross-sectional structural schematic diagram of the capacitor structure along A1-A2 in the figure; Figure 1 Figure 4 A flowchart of the method for adjusting the capacitance of the capacitor structure provided by the embodiments of the present disclosure is shown in the figure; Figure 5 A schematic diagram of each sub-capacitor in the capacitor structure provided by the first embodiment is shown in the figure; Figure 6 A schematic diagram of each sub-capacitor in the capacitor structure provided by the second embodiment is shown in the figure; Figure 7 A schematic diagram of each sub-capacitor in the capacitor structure provided by the third embodiment is shown in the figure. DETAILED DESCRIPTION

[0016] ​The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0017] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure. In the interest of clarity, not all features of the actual implementation are described in detail (exemplary implementations are shown in excessive detail, not to be construed as limiting).

[0018] In the drawings, the size of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference numbers represent the same elements throughout the drawings.

[0019] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one intervening element or layer can exist. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0020] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] For a thorough understanding of the present disclosure, reference will be made to the following detailed description taken in conjunction with the accompanying drawings. The preferred embodiments of the present disclosure will be described below in detail with reference made to the figures. However, the present disclosure can have other embodiments in addition to those described in detail below.

[0023] At present, the capacitance adjustment of the capacitor structure usually uses a fuse or one-time programmable (OTP). In a first aspect, the above-mentioned method for adjusting the capacitance of the capacitor structure increases the processing complexity and the size and manufacturing cost of the chip. In a second aspect, the fuse or one-time programmable is a one-time permanent adjustment and cannot realize dynamic adjustment of the capacitance of the capacitor structure.

[0024] According to the capacitance calculation formula of the capacitor structure, the capacitance of the capacitor structure is affected by the facing area between the first electrode and the second electrode, the spacing between the first electrode and the second electrode, and the dielectric constant of the dielectric layer between the first electrode and the second electrode. The greater the facing area between the first electrode and the second electrode, the smaller the spacing between the first electrode and the second electrode, and the smaller the dielectric constant of the dielectric layer between the first electrode and the second electrode, the greater the capacitance of the capacitor structure. That is, after the physical structure of the capacitor structure is determined, the capacitance of the capacitor structure can be determined.

[0025] In view of this, in order to solve at least one of the above-mentioned technical problems, this disclosure provides a capacitor structure and a method for adjusting the capacitance value of the capacitor structure.

[0026] Here, we first define the various directions that may be involved in the following text. The stacking direction of the conductive structures is defined as the first direction (i.e., direction D1), the arrangement direction of the first and second conductive patterns in the same conductive structure is defined as the second direction (i.e., direction D2), and the extension direction of the first connecting part (or, the second connecting part) is defined as the third direction (i.e., direction D3); wherein, direction D2 and direction D1 are perpendicular to each other, direction D3 and direction D1 are perpendicular to each other, and direction D3 and direction D2 intersect. In some embodiments, direction D2 and direction D3 are perpendicular to each other, and this will be used as an example in the following explanation.

[0027] refer to Figure 1 , Figure 1 This is a three-dimensional structural diagram of the capacitor structure provided in an embodiment of this disclosure. Figure 1 As shown, this embodiment of the present disclosure provides a capacitor structure 100, which includes n conductive structures 102 stacked along the D1 direction. Each conductive structure 102 includes a first conductive pattern 108 and a second conductive pattern 120 arranged along the D2 direction. The first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102 form an interdigitated structure. The two first conductive patterns 108 in two adjacent conductive structures 102 arranged along the D1 direction at least partially overlap, and the two second conductive patterns 120 in two adjacent conductive structures 102 arranged along the D1 direction at least partially overlap. n is an integer greater than 1.

[0028] Here, n conductive structures 102 are stacked along the D1 direction, and from top to bottom they are: conductive structure M1, conductive structure M2, conductive structure M3, ... and conductive structure Mn. Figure 1 The capacitor structure 100 described herein includes five conductive structures 102 stacked along the D1 direction, which is exemplified but does not constitute a limitation on the scope of protection of this disclosure. The capacitor structure 100 provided in the embodiments of this disclosure may include, for example, three, six, seven, or other numbers of conductive structures 102.

[0029] Here, in the same conductive structure 102, the MOM capacitor can be formed between the first conductive pattern 108 and the second conductive pattern 120. The orthographic projection of any two first conductive patterns 108 arranged adjacent to each other in the D1 direction on the D2D3 plane at least partially overlaps, and any two first conductive patterns 108 arranged adjacent to each other in the D1 direction have a certain facing area. That is, the MIM capacitor can be formed between any two first conductive patterns 108 arranged adjacent to each other in the D1 direction. The orthographic projection of any two second conductive patterns 120 arranged adjacent to each other in the D1 direction on the D2D3 plane at least partially overlaps, and any two second conductive patterns 120 arranged adjacent to each other in the D1 direction have a certain facing area. That is, the MIM capacitor can also be formed between any two second conductive patterns 120 arranged adjacent to each other in the D1 direction.

[0030] In the embodiments of the present disclosure, in a first aspect, the capacitor structure 100 includes a MOM capacitor and a MIM capacitor. In the same conductive structure 102, the MOM capacitor is formed between the first conductive pattern 108 and the second conductive pattern 120. The MIM capacitor is formed between any two conductive structures 102 arranged adjacent to each other in the D1 direction. In this way, the density of the capacitor structure 100 can be increased. In a second aspect, n first voltages can be applied to the n first conductive patterns 108 respectively, and n second voltages can be applied to the n second conductive patterns 120 respectively. By adjusting the n first voltages and the n second voltages, the total capacitance of the capacitor structure 100 can be dynamically adjusted, and the flexibility of circuit design and use can be increased.

[0031] In some embodiments, the n conductive structures 102 include a first conductive structure 104 and a second conductive structure 106 arranged opposite to each other in the D1 direction. Here, the first conductive structure 104 and the second conductive structure 106 are respectively located at two ends of the capacitor structure 100 arranged opposite to each other in the D1 direction.

[0032] Here, the first conductive structure 104 can be the conductive structure at the bottom of the capacitor structure 100, and the second conductive structure 106 can be the conductive structure at the top of the capacitor structure 100. For example, the first conductive structure 104 can be the conductive structure Mn, and the second conductive structure 106 can be the conductive structure M1, Figure 1 The above is described taking this case as an example.

[0033] Here, the first conductive structure can be the conductive structure at the top of the capacitor structure, and the second conductive structure can be the conductive structure at the bottom of the capacitor structure. For example, the first conductive structure can be the conductive structure M1, and the second conductive structure can be the conductive structure Mn.

[0034] Here, the first conductive pattern 108 and the second conductive pattern 120 in the same conductive structure 102 have the same height position along the D1 direction. For example, the first conductive pattern 108 and the second conductive pattern 120 in the conductive structure M3 have the same height position along the D1 direction.

[0035] In some embodiments, the first conductive pattern 108 and the second conductive pattern 120 can include a conductive material, including but not limited to at least one of tungsten (W), copper (Cu), aluminum (Al), and polysilicon (Poly).

[0036] In some embodiments, the capacitance structure 100 further includes a first dielectric layer, the first dielectric layer being located between the first conductive pattern 108 and the second conductive pattern 120 in the same conductive structure 102.

[0037] In some embodiments, the capacitance structure 100 further includes a second dielectric layer, the second dielectric layer being located between any two conductive structures 102 arranged adjacently along the D1 direction.

[0038] In some embodiments, the first dielectric layer and the second dielectric layer can include a dielectric material, including but not limited to silicon oxide.

[0039] In some embodiments, the process of forming the first conductive pattern 108, the second conductive pattern 120, the first dielectric layer, and the second dielectric layer can include but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0040] Exemplarily, forming the conductive structure 102 can include the following steps: etching the first layer of the first dielectric layer by using a mask plate to form a first recess and a second recess; filling the conductive material in the first recess and the second recess to form the first conductive pattern 108 and the second conductive pattern 120 respectively; forming the first layer of the second dielectric layer covering the first layer of the first dielectric layer, the first conductive pattern 108 and the second conductive pattern 120; at this time, the first layer of the conductive structure 102, for example, the conductive structure M1, can be formed. Forming the second layer of the first dielectric layer covering the first layer of the second dielectric layer; etching the second layer of the first dielectric layer by using a mask plate to form a third recess and a fourth recess; filling the conductive material in the third recess and the fourth recess to form the first conductive pattern 108 and the second conductive pattern 120 respectively; forming the second layer of the second dielectric layer covering the second layer of the first dielectric layer, the first conductive pattern 108 and the second conductive pattern 120; at this time, the second layer of the conductive structure 102, for example, the conductive structure M2, can be formed. The third layer of the first dielectric layer can be continuously formed, and the conductive structure 102 can be formed in the third layer of the first dielectric layer until n conductive structures 102 stacked along the D1 direction are formed.

[0041] Here, the first layer of the first dielectric layer and the second layer of the first dielectric layer are the first dielectric layer between the first conductive pattern 108 and the second conductive pattern 120 in the same conductive structure 102, and the first layer of the second dielectric layer and the second layer of the second dielectric layer are the second dielectric layer between two conductive structures 102 arranged adjacent along the D1 direction.

[0042] In some embodiments, there is no direct electrical connection between the n first conductive patterns 108 stacked along the D1 direction, and n first voltages can be applied to the n first conductive patterns 108 respectively, which can be the same or different; there is no direct electrical connection between the n second conductive patterns 120 stacked along the D1 direction, and n second voltages can be applied to the n second conductive patterns 120 respectively, which can be the same or different.

[0043] That is, the capacitance structure 100 is controlled by n voltage groups, each of which includes a first voltage and a second voltage. Each voltage group and each conductive structure 102 correspond one-to-one, a first voltage in each voltage group is applied to the first conductive pattern 108, and a second voltage in each voltage group is applied to the second conductive pattern 120. The first voltage applied to the first conductive pattern 108 in the same conductive structure 102 and the second voltage applied to the second conductive pattern 120 can be the same or different, the n first voltages applied to the n first conductive patterns 108 respectively can be the same or different, and the n second voltages applied to the n second conductive patterns 120 respectively can be the same or different.

[0044] In some embodiments, the capacitor structure 100 further includes: n first contact structures, each of which is electrically connected to n first conductive patterns 108; and n second contact structures, each of which is electrically connected to n second conductive patterns 120.

[0045] Here, the n first conductive patterns 108 stacked along the D1 direction are not directly electrically connected, meaning they are not sequentially connected by conductive wires, and the same voltage is applied to all n first conductive patterns 108. Similarly, the n second conductive patterns 120 stacked along the D1 direction are not directly electrically connected, meaning they are not sequentially connected by conductive wires, and the same voltage is applied to all n second conductive patterns 120. The n first conductive patterns 108 can each be led out with electrical signals through n first contact structures, and the n second conductive patterns 120 can each be led out with electrical signals through n second contact structures. In other words, the n first voltages applied to the n first conductive patterns 108 through the n first contact structures can be the same or different, and the n second voltages applied to the n second conductive patterns 120 through the n second contact structures can be the same or different. This allows for more flexible and adjustable voltage application to the n first conductive patterns 108 and n second conductive patterns 120.

[0046] refer to Figure 2 , Figure 2 This is a top view schematic diagram of the conductive structure provided in an embodiment of this disclosure. Figure 2 As shown, in some embodiments, the first conductive pattern 108 includes: a first comb pattern 110, the first comb pattern 110 including a plurality of first teeth 112 extending along the D2 direction; the second conductive pattern 120 includes: a second comb pattern 122, the second comb pattern 122 including a plurality of second teeth 124 extending along the D2 direction; the first teeth 112 of the first comb pattern 110 and the second teeth 124 of the second comb pattern 122 are staggered along the D3 direction; wherein, in the same conductive structure 102 (e.g., the first conductive structure 104), the number of first teeth 112 included in the first comb pattern 110 and the number of second teeth 124 included in the second comb pattern 122 are the same.

[0047] In other embodiments, in the same conductive structure 102, the number of first teeth 112 included in the first comb pattern 110 and the number of second teeth 124 included in the second comb pattern 122 are different. For example, the difference between the number of first teeth 112 included in the first comb pattern 110 and the number of second teeth 124 included in the second comb pattern 122 is 1.

[0048] here, Figure 2The first comb pattern 110 includes three first teeth 112, and the second comb pattern 122 includes three second teeth 124, which are exemplified but do not constitute a limitation on the scope of protection of this disclosure. The first comb pattern 110 provided in the embodiments of this disclosure may include two, four, five, or other numbers of first teeth 112, and the second comb pattern 122 may include two, four, five, or other numbers of second teeth 124.

[0049] Here, each first tooth 112 extends along the D2 direction, and multiple first teeth 112 are parallel to each other and spaced apart along the D3 direction. Each second tooth 124 extends along the D2 direction, and multiple second teeth 124 are parallel to each other and spaced apart along the D3 direction. Here, the first teeth 112 and the second teeth 124 are parallel to each other, and the first teeth 112 and the second teeth 124 are alternately arranged along the D3 direction.

[0050] Here, the orthographic projections of the first tooth 112 and the second tooth 124 arranged adjacent to each other along the D3 direction on the D1D2 plane at least partially overlap, and the first tooth 112 and the second tooth 124 arranged adjacent to each other along the D3 direction have a certain facing area, which can form a MOM capacitor.

[0051] In some embodiments, the orthographic projections of the first tooth 112 and the second tooth 124, which are arbitrarily adjacent along the D3 direction, coincide on the D1D2 plane.

[0052] like Figure 1 As shown, in some embodiments, the number of first teeth 112 included in the two first comb patterns 110 of two conductive structures 102 arranged arbitrarily adjacent to each other along the D1 direction is the same, and the number of second teeth 124 included in the two second comb patterns 122 of two conductive structures 102 arranged arbitrarily adjacent to each other along the D1 direction is the same.

[0053] Here, the orthographic projections of two first teeth 112 arranged arbitrarily adjacent along the D1 direction on the D2D3 plane at least partially overlap, and there is a certain facing area between the two first teeth 112 arranged arbitrarily adjacent along the D1 direction. A MIM capacitor can be formed between the two first teeth 112 arranged arbitrarily adjacent along the D1 direction. Similarly, the orthographic projections of two second teeth 124 arranged arbitrarily adjacent along the D1 direction on the D2D3 plane at least partially overlap, and there is a certain facing area between the two second teeth 124 arranged arbitrarily adjacent along the D1 direction. A MIM capacitor can be formed between the two second teeth 124 arranged arbitrarily adjacent along the D1 direction.

[0054] like Figure 2As shown, in some embodiments, the first conductive pattern 108 further includes: a first connecting portion 118 extending along the D3 direction; the first tooth 112 includes a first end portion 114 and a second end portion 116 disposed opposite to each other along the D2 direction, and the first end portion 114 of the plurality of first teeth 112 is connected to the first connecting portion 118; the second conductive pattern 120 further includes: a second connecting portion 130 extending along the D3 direction; the second tooth 124 includes a third end portion 126 and a fourth end portion 128 disposed opposite to each other along the D2 direction, and the third end portion 126 of the plurality of second teeth 124 is connected to the second connecting portion 130; wherein, the second end portion 116 of the plurality of first teeth 112 faces the second connecting portion 130, and the fourth end portion 128 of the plurality of second teeth 124 faces the first connecting portion 118. Figure 2 The four dashed circles in the middle represent the first end 114, the second end 116, the third end 126, and the fourth end 128, respectively.

[0055] Here, the first tooth 112 is located between two adjacent second teeth 124 arranged along the D3 direction, and the second tooth 124 is also located between two adjacent first teeth 112 arranged along the D3 direction. The first end 114 of the first tooth 112 is connected to the first connecting portion 118, and there is a certain distance between the second end 116 of the first tooth 112 and the second connecting portion 130; the third end 126 of the second tooth 124 is connected to the second connecting portion 130, and there is a certain distance between the fourth end 128 of the second tooth 124 and the first connecting portion 118.

[0056] like Figure 1 As shown, in some embodiments, the projections of two first conductive patterns 108 in two conductive structures 102 arranged arbitrarily adjacent to each other along the D1 direction on a plane perpendicular to the D1 direction (i.e., the D2D3 plane) coincide; the projections of two second conductive patterns 120 in two conductive structures 102 arranged arbitrarily adjacent to each other along the D1 direction on a plane perpendicular to the D1 direction (i.e., the D2D3 plane) coincide.

[0057] Here, the projections of two first conductive patterns 108 arranged arbitrarily adjacent along the D1 direction coincide, meaning that the area facing each other is larger, which is beneficial for increasing the capacitance value of the capacitor structure. Similarly, the projections of two second conductive patterns 120 arranged arbitrarily adjacent along the D1 direction coincide, meaning that the area facing each other is larger, which is beneficial for increasing the capacitance value of the capacitor structure.

[0058] refer to Figure 3 , Figure 3 For along Figure 1 A schematic cross-sectional view of the capacitor structure at section A1-A2. (See diagram below.) Figure 3As shown, in some embodiments, the capacitance structure 100 includes n first sub-capacitance structures, (n-1) second sub-capacitance structures, and (n-1) third sub-capacitance structures; wherein a first sub-capacitance structure is formed between the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102; a second sub-capacitance structure is formed between two first conductive patterns 108 arranged adjacent along the D1 direction; and a third sub-capacitance structure is formed between two second conductive patterns 120 arranged adjacent along the D1 direction.

[0059] Here, along the D3 direction, a first sub-capacitance structure is formed between the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102, and the capacitance structure 100 includes n conductive structures 102 in total, thus the capacitance structure 100 includes n first sub-capacitance structures in total. In the first sub-capacitance structure, the first conductive pattern 108 serves as a first electrode and the second conductive pattern 120 serves as a second electrode; wherein the first sub-capacitance structure can also be referred to as a lateral capacitance structure, or a horizontal capacitance structure.

[0060] Here, along the D1 direction, a second sub-capacitance structure is formed between two first conductive patterns 108 arranged adjacent, and the capacitance structure 100 includes n first conductive patterns 108 in total, thus the capacitance structure 100 includes (n-1) second sub-capacitance structures in total. In the second sub-capacitance structure, one first conductive pattern 108 serves as a first electrode and the other first conductive pattern 108 serves as a second electrode; wherein the second sub-capacitance structure can also be referred to as a longitudinal capacitance structure, or a vertical capacitance structure.

[0061] Here, along the D1 direction, a third sub-capacitance structure is formed between two second conductive patterns 120 arranged adjacent, and the capacitance structure 100 includes n second conductive patterns 120 in total, thus the capacitance structure 100 includes (n-1) third sub-capacitance structures in total. In the third sub-capacitance structure, one second conductive pattern 120 serves as a first electrode and the other second conductive pattern 120 serves as a second electrode; wherein the third sub-capacitance structure can also be referred to as a longitudinal capacitance structure, or a vertical capacitance structure.

[0062] It should be noted that, according to the capacitance calculation formula for a capacitor structure, the capacitance value of each sub-capacitor structure is fixed after the capacitor structure is manufactured. When the same voltage is applied to the first and second electrodes of a sub-capacitor structure, the capacitance value of the sub-capacitor structure is not included in the total capacitance value of the capacitor structure; when different voltages are applied to the first and second electrodes of a sub-capacitor structure, the capacitance value of the sub-capacitor structure is included in the total capacitance value of the capacitor structure. Therefore, the total capacitance value of the capacitor structure can be adjusted by adjusting the voltage applied to the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102 to determine whether the capacitance value of a certain sub-capacitor structure is included in the total capacitance value of the capacitor structure.

[0063] like Figure 3 As shown, the voltage applied to the conductive structure M1 is defined as the first voltage group V1, and the first voltage group V1 includes the first voltage V1. high Second voltage V1 low The voltage applied to the conductive structure M2 is defined as the second voltage group V2, which includes the first voltage V2. high Second voltage V2 low The voltage applied to the conductive structure M3 is defined as the third voltage group V3, which includes the first voltage V3. high Second voltage V3 low The voltage applied to the conductive structure Mn is defined as the nth voltage group Vn, and the nth voltage group Vn includes the first voltage Vn. high Second voltage Vn low .

[0064] Taking conductive structure M1 as an example, the MOM capacitor will be explained. Along the D3 direction, for conductive structure M1, a first voltage V1 is applied to each first tooth 112 in the first conductive pattern 108. high A second voltage V1 is applied to each of the second teeth 124 in the second conductive pattern 120. low Along the D3 direction, a first sub-capacitor structure C is formed between adjacent first teeth 112 and second teeth 124. H0 The voltage difference between the first tooth 112 and the second tooth 124 is (V1) high -V1 low ).

[0065] It should be noted that if V1 high and V1 low If they are the same, then the first sub-capacitor structure C H0 The capacitance value is not included in the total capacitance value of the capacitor structure; if V1 high and V1 low The first sub-capacitor structure C is different.H0 The capacitance value is included in the total capacitance value of the capacitor structure.

[0066] Taking conductive structures M1 and M2 as examples, the MIM capacitor will be explained. Along the D1 direction, for adjacent conductive structures M1 and M2, a first voltage V1 is applied to the first tooth 112 in conductive structure M1 and the first tooth 112 in conductive structure M2, respectively. high and the first voltage V2 high A second voltage V1 is applied to the second tooth 124 in conductive structure M1 and the second tooth 124 in conductive structure M2, respectively. low Second voltage V2 low Along the D1 direction, a second sub-capacitor structure C is formed between two adjacent first teeth 112. V10 The voltage difference between two adjacent first teeth 112 is (V1) high -V2 high Along the D1 direction, a third sub-capacitor structure C is formed between two adjacent second teeth 124. V20 The voltage difference between two adjacent second teeth 124 is (V1) low -V2 low ).

[0067] It should be noted that if V1 high and V2 high If they are the same, then the second sub-capacitor structure C V10 The capacitance value is not included in the total capacitance value of the capacitor structure; if V1 high and V2 high The second sub-capacitor structure C is different. V10 The capacitance value is included in the total capacitance value of the capacitor structure. If V1 low and V2 low If they are the same, then the third sub-capacitor structure C V20 The capacitance value is not included in the total capacitance value of the capacitor structure; if V1 low and V2 low The third sub-capacitor structure C is different. V20 The capacitance value is included in the total capacitance value of the capacitor structure.

[0068] refer to Figure 4 , Figure 4 This is a schematic flowchart illustrating the capacitance adjustment method for a capacitor structure provided in an embodiment of this disclosure. Figure 4 As shown, this disclosure provides a method for adjusting the capacitance value of a capacitor structure. The method is used to adjust the capacitor structure in the above-described technical solution. The method includes: Step S210: providing n voltage groups, each voltage group including a first voltage and a second voltage; wherein the n conductive structures and the n voltage groups are in one-to-one correspondence; Step S220: applying n first voltages to the n first conductive patterns respectively, and applying n second voltages to the n second conductive patterns respectively.

[0069] Here, the first voltage group V1 includes the first voltage V1 high and the second voltage V1 low , the second voltage group V2 includes the first voltage V2 high and the second voltage V2 low , the third voltage group V3 includes the first voltage V3 high and the second voltage V3 low , …, the n-th voltage group Vn includes the first voltage Vn high and the second voltage Vn low .

[0070] Reference Figures 5 to 7 , Figures 5 to 7 is a schematic diagram of each sub-capacitor in the capacitive structure provided by the embodiments of the present disclosure. The following will be described in combination with Figures 5 to 7 , the capacitance adjustment process of the capacitive structure.

[0071] As Figure 5 shown, the first conductive pattern 108 in the conductive structure M1 applying the first voltage V1 high and the second conductive pattern 120 applying the second voltage V1 low form a first sub-capacitive structure C H1 , the first conductive pattern 108 in the conductive structure M2 applying the first voltage V2 high and the second conductive pattern 120 applying the second voltage V2 low form a first sub-capacitive structure C H2 , the first conductive pattern 108 in the conductive structure M3 applying the first voltage V3 high and the second conductive pattern 120 applying the second voltage V3 low form a first sub-capacitive structure C H3 , …, the first conductive pattern 108 in the conductive structure Mn applying the first voltage Vn high and the second conductive pattern 120 applying the second voltage Vn low form a first sub-capacitive structure C Hn . That is, the capacitive structure 100 includes n first sub-capacitive structures 132, i.e., the first sub-capacitive structures C H1 , C H2 , C H3 , …, and C Hn .

[0072] Combination Figure 1 and Figure 5 As shown, in some embodiments, the capacitor structure further includes: (n-1) sets of first adjustable resistors, each set including a first adjustable resistor 138 and a second adjustable resistor 140, the two ends of each first adjustable resistor 138 being used to connect to two first conductive patterns 108 in two adjacent conductive structures 102 arranged along the D1 direction, and the two ends of each second adjustable resistor 140 being used to connect to two second conductive patterns 120 in two adjacent conductive structures 102 arranged along the D1 direction; and a second adjustable resistor set, the second adjustable resistor set including a third adjustable resistor. The system includes a resistor 142 and a fourth adjustable resistor 144. The two ends of the third adjustable resistor 142 are respectively used to connect the first conductive pattern 108 in the first conductive structure 104 and the ground voltage VSS. The two ends of the fourth adjustable resistor 144 are respectively used to connect the second conductive pattern 120 in the first conductive structure 104 and the ground voltage VSS. The system also includes a third adjustable resistor set, comprising a fifth adjustable resistor 146 and a sixth adjustable resistor 148. The two ends of the fifth adjustable resistor 146 are respectively used to connect the first conductive pattern 108 in the second conductive structure 106 and the first voltage node 150 (i.e.,...). Figure 5 The V shown in the middle high The two ends of the sixth adjustable resistor 148 are respectively used to connect the second conductive pattern 120 and the second voltage node 152 in the second conductive structure 106 (i.e., Figure 5 The V shown in the middle low ).

[0073] By adjusting the resistance values ​​of the first adjustable resistor 138, the third adjustable resistor 142, and the fifth adjustable resistor 146, the voltage applied to each of the first conductive patterns 108 stacked along the D1 direction can be adjusted. For example, by increasing the resistance value of the first adjustable resistor 138, the voltage difference between the two first conductive patterns 108 connected to its two ends can be increased. Conversely, by decreasing the resistance values ​​of the third adjustable resistor 142 and the fifth adjustable resistor 146, the voltage division of the third adjustable resistor 142 and the fifth adjustable resistor 146 can be decreased, respectively. Decreasing the resistance value of the third adjustable resistor 142 increases the first voltage Vn. high Decreasing the resistance of the fifth adjustable resistor 146 increases the first voltage V1. high .

[0074] Here, based on the resistance values ​​of the first adjustable resistor 138, the third adjustable resistor 142, and the fifth adjustable resistor 146, the voltage V at the first voltage node 150 is... high The voltage difference between the adjustable resistor and the ground voltage VSS is distributed. The larger the resistance value of the adjustable resistor, the larger the voltage difference between its two ends.

[0075] Similarly, by adjusting the resistance values of the respective second adjustable resistors 140, fourth adjustable resistors 144 and sixth adjustable resistors 148, the voltage values applied to the respective second conductive patterns 120 stacked along the D1 direction are adjusted. For example, by reducing the resistance value of the second adjustable resistor 140, the voltage difference between the two second conductive patterns 120 connected respectively at the two ends of the second adjustable resistor 140 can be reduced. For another example, by increasing the resistance values of the fourth adjustable resistors 144 and sixth adjustable resistors 148, the voltage division of the fourth adjustable resistors 144 and sixth adjustable resistors 148 respectively can be increased. Among them, increasing the resistance value of the fourth adjustable resistor 144 can reduce the second voltage Vn low ; increasing the resistance value of the sixth adjustable resistor 148 can reduce the second voltage V1 low .

[0076] Here, according to the resistance values of the second adjustable resistors 140, fourth adjustable resistors 144 and sixth adjustable resistors 148, the voltage difference between the voltage V low of the second voltage node 152 and the ground voltage VSS is divided. The greater the resistance value of the adjustable resistor, the greater the voltage difference between the two ends.

[0077] Here, the n first conductive patterns 108 stacked along the D1 direction are sequentially applied with the first voltages V1 high , V2 high , V3 high , …, and Vn high . The first conductive pattern 108 in the conductive structure M1 applied with the first voltage V1 high and the first conductive pattern 108 in the conductive structure M2 applied with the first voltage V2 high form a second sub-capacitance structure C V11 ; the first conductive pattern 108 in the conductive structure M2 applied with the first voltage V2 high and the first conductive pattern 108 in the conductive structure M3 applied with the first voltage V3 high form a second sub-capacitance structure C V12 ; …; the first conductive pattern 108 in the conductive structure M(n-1) applied with the first voltage V(n-1) high and the first conductive pattern 108 in the conductive structure Mn applied with the first voltage Vn high form a second sub-capacitance structure C V1(n－1) . That is, the capacitance structure 100 includes (n-1) second sub-capacitance structures 134, i.e., the second sub-capacitance structures C V11 , C V12 , C V13 , …, and C V1（n－1） .

[0078] Here, the n second conductive patterns 120 stacked in the D1 direction are sequentially applied with the second voltages V1 low , V2 low , V3 low , …, and Vn low . The second conductive pattern 120 in the conductive structure M1 to which the second voltage V1 low is applied and the second conductive pattern 120 in the conductive structure M2 to which the second voltage V2 low is applied form a third sub-capacitance structure C V21 ; the second conductive pattern 120 in the conductive structure M2 to which the second voltage V2 low is applied and the second conductive pattern 120 in the conductive structure M3 to which the second voltage V3 low is applied form a third sub-capacitance structure C V22 ; and the second conductive pattern 120 in the conductive structure M(n-1) to which the second voltage V(n-1) low is applied and the second conductive pattern 120 in the conductive structure Mn to which the second voltage Vn low is applied form a third sub-capacitance structure C V2(n－1) . That is, the capacitance structure 100 includes (n-1) third sub-capacitance structures 136, i.e., the third sub-capacitance structures C V21 , C V22 , C V23 , …, and C V2（n－1） .

[0079] In some embodiments, the resistance values of the (n-1) first adjustable resistances 138 can be the same or different. In some embodiments, the resistance values of the first adjustable resistance 138, the third adjustable resistance 142, and the fifth adjustable resistance 146 can be the same or different. In some embodiments, when the resistance value of the third adjustable resistance 142 is 0, the first voltage Vn high is the same as the ground voltage VSS. In some embodiments, when the resistance value of the fifth adjustable resistance 146 is 0, the first voltage V1 high is the same as the voltage V high of the first voltage node 150.

[0080] In some embodiments, the resistance values of the (n-1) second adjustable resistances 140 can be the same or different. In some embodiments, the resistance values of the second adjustable resistance 140, the fourth adjustable resistance 144, and the sixth adjustable resistance 148 can be the same or different. In some embodiments, when the resistance value of the fourth adjustable resistance 144 is 0, the second voltage Vn low is the same as the ground voltage VSS. In some embodiments, when the resistance value of the sixth adjustable resistance 148 is 0, the second voltage V1 low is the same as the voltage Vlow same.

[0081] Combination Figure 1 and Figure 5 As shown, the capacitor structure 100 includes two voltage nodes, namely the first voltage node V. high Second voltage node V low By adjusting the resistance values ​​of the first adjustable resistor 138, the third adjustable resistor 142, and the fifth adjustable resistor 146, the voltage values ​​applied to each of the first conductive patterns 108 in the conductive structures M1 to Mn are adjusted, namely V1. high V2 high ... and Vn high By adjusting the resistance values ​​of the second adjustable resistor 140, the fourth adjustable resistor 144, and the sixth adjustable resistor 148, the voltage values ​​applied to each of the second conductive patterns 120 in the conductive structures M1 to Mn are adjusted, namely V1. low V2 low ... and Vn low .

[0082] In some specific embodiments, when the resistance values ​​of (n-1) first adjustable resistors 138 are the same, and are also the same as the resistance values ​​of the third adjustable resistor 142 and the fifth adjustable resistor 146, a first voltage V1 is applied to the first conductive pattern 108 in the conductive structure M1. high =n*V high / (n+1); Apply a first voltage V2 to the first conductive pattern 108 in the conductive structure M2. high = (n-1)*V high / (n+1); Apply a first voltage V3 to the first conductive pattern 108 in the conductive structure M3. high = (n-2)*V high / (n+1); ...; Apply a first voltage Vn to the first conductive pattern 108 in the conductive structure Mn. high =V high / (n+1). Thus, the first voltage applied to the n first conductive patterns 108 stacked along the D1 direction is gradient-arranged.

[0083] For example, when V high =24V, n=5, V1 high =20V, V2 high =16V, V3 high =12V, V4 high =8V, V5 high =4V.

[0084] In some embodiments, when the resistance values of the (n-1) second adjustable resistors 140 are the same, and the resistance values of the fourth adjustable resistor 144 and the sixth adjustable resistor 148 are the same, the second voltage V1 applied to the second conductive pattern 120 in the conductive structure M1 is low = n*V low / (n+1); the second voltage V2 applied to the second conductive pattern 120 in the conductive structure M2 is low = (n-1)*V low / (n+1); the second voltage V3 applied to the second conductive pattern 120 in the conductive structure M3 is low = (n-2)*V low / (n+1); and so on; the second voltage Vn applied to the second conductive pattern 120 in the conductive structure Mn is low = V low / (n+1). Thus, the second voltages applied to the n second conductive patterns 120 stacked in the D1 direction are arranged in a gradient.

[0085] For example, when V low = 12V and n = 5, V1 low = 10V, V2 low = 8V, V3 low = 6V, V4 low = 4V, and V5 low = 2V.

[0086] In some embodiments, the first voltage and the second voltage in each voltage group are different, i.e., V1 high ≠ V1 low , V2 high ≠ V2 low , V3 high ≠ V3 low , and so on; the two first voltages applied to any two first conductive patterns 108 arranged adjacently in the D1 direction are different, i.e., V1 high ≠ V2 high , V2 high ≠ V3 high , V3 high ≠ V4 high , and so on; and the two second voltages applied to any two second conductive patterns 120 arranged adjacently in the D1 direction are different, i.e., V1 low ≠ V2 low , V2 low ≠ V3 low , V3 low ≠ V4 low , and so on. Figure 1 Figure 5 In some embodiments, the first voltage and the second voltage in each voltage group are different, i.e., V1 high ≠ V1 low , V2 high ≠ V2 low , V3 high ≠ V3 low , and so on; the two first voltages applied to any two first conductive patterns 108 arranged adjacently in the D1 direction are different, i.e., V1 high ≠ V2 high , V2 high ≠ V3 high , V3 high ≠ V4 high , and so on; and the two second voltages applied to any two second conductive patterns 120 arranged adjacently in the D1 direction are different, i.e., V1 low ≠ V2 low , V2 low ≠ V3 low , V3 low ≠ V4 low , and so on.low and V3 low Different, V3 low and V4 low Different, ..., V(n-1) low and Vn low The difference lies in the fact that the total capacitance of capacitor structure 100 includes the capacitance of n first sub-capacitor structures 132, (n-1) second sub-capacitor structures 134, and (n-1) third sub-capacitor structures 136; a first sub-capacitor structure 132 is formed between the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102; a second sub-capacitor structure 134 is formed between two first conductive patterns 108 in two adjacent conductive structures 102 arranged along the D1 direction; and a third sub-capacitor structure 136 is formed between two second conductive patterns 120 in two adjacent conductive structures 102 arranged along the D1 direction. In other words, the total capacitance of capacitor structure 100 here includes the capacitance of all MOM capacitors and the capacitance of all MIM capacitors.

[0087] For example, when V high =24V, V low =12V, n=5; V1 high =20V, V2 high =16V, V3 high =12V, V4 high =8V, V5 high =4V;V1 low =10V, V2 low =8V, V3 low =6V, V4 low =4V, V5 low =2V.

[0088] Combination Figure 1 and Figure 6 As shown, in some embodiments, the first voltage and the second voltage in each voltage group are different, i.e., V1 high and V1 low Different, V2 high and V2 low Different, V3 high and V3 low Different, ..., Vn high and Vn low The two first voltages applied to two first conductive patterns arbitrarily adjacent along the D1 direction are different, i.e., V1 high and V2 high Different, V2 high and V3 high Different, V3 high and V4 high Different, ..., V(n-1)high and Vn high are different; two first voltages applied to any two first conductive patterns arranged adjacently along the D1 direction are the same, i.e., V low , V1 low , V2 low , V3 low , …, and Vn low are all the same; wherein the total capacitance of the capacitance structure 100 includes the capacitances of the n first sub-capacitance structures 132 and the (n-1) second sub-capacitance structures 134; each first sub-capacitance structure 132 is formed between the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102; each second sub-capacitance structure 134 is formed between two first conductive patterns 108 in two conductive structures 102 arranged adjacently along the D1 direction. That is, here, the total capacitance of the capacitance structure 100 includes the capacitances of all the MOM capacitors and the capacitances of some of the MIM capacitors.

[0089] For example, when V high = 24V, V low = 2V, and n = 5; V1 high = 20V, V2 high = 16V, V3 high = 12V, V4 high = 8V, and V5 high = 4V; V1 low = V2 low = V3 low = V4 low = V5 low = 2V.

[0090] In combination with FIGS. Figure 1 and Figure 7 , in some embodiments, the first voltage and the second voltage in each voltage group are different, i.e., V1 high and V1 low are different, V2 high and V2 low are different, V3 high and V3 low are different, …, Vn high and Vn low are different; two first voltages applied to any two first conductive patterns arranged adjacently along the D1 direction are the same, i.e., V high , V1 high , V2 high , V3 high , …, and Vn high are all the same; two second voltages applied to any two second conductive patterns arranged adjacently along the D1 direction are the same, i.e., V low , V1 lowV2 low V3 low … and Vn low are all the same; wherein the total capacitance of the capacitor structure 100 includes the capacitances of the n first sub-capacitor structures 132; each first sub-capacitor structure 132 is formed between the first conductive pattern 108 and the second conductive pattern 120 in each conductive structure 102. That is, here, the total capacitance of the capacitor structure 100 includes the capacitances of all the MOM capacitors.

[0091] For example, when V high = 20V, V low = 10V, and n = 5; V1 high = V2 high = V3 high = V4 high = V5 high = 20V; V1 low = V2 low = V3 low = V4 low = V5 low = 10V.

[0092] In some embodiments, the first voltage and the second voltage in each voltage group are the same, i.e., V1 high and V1 low are the same, V2 high and V2 low are the same, V3 high and V3 low are the same, …, Vn high and Vn low are the same; the two first voltages applied to any two first conductive patterns 108 arranged adjacently along the D1 direction are different, i.e., V1 high and V2 high are different, V2 high and V3 high are different, V3 high and V4 high are different, …, V(n-1) high and Vn high are different; the two second voltages applied to any two second conductive patterns 120 arranged adjacently along the D1 direction are different, i.e., V1 low and V2 low are different, V2 low and V3 low are different, V3 low and V4 low are different, …, V(n-1) low and Vn lowThe difference lies in the fact that the total capacitance of capacitor structure 100 includes the capacitance of (n-1) second sub-capacitor structures 134 and the capacitance of (n-1) third sub-capacitor structures 136; a second sub-capacitor structure 134 is formed between two first conductive patterns 108 in two adjacent conductive structures 102 arranged along the D1 direction; and a third sub-capacitor structure 136 is formed between two second conductive patterns 120 in two adjacent conductive structures 102 arranged along the D1 direction. In other words, the total capacitance of capacitor structure 100 here includes the capacitance of all MIM capacitors.

[0093] For example, when V high =V low =24V, n=5; V1 high =V1 low =20V, V2 high =V2 low =16V, V3 high =V3 low =12V, V4 high =V4 low =8V, V5 high =V5 low =4V.

[0094] Figure 5 The diagram illustrates that the total capacitance of capacitor structure 100 includes the capacitance of all MOM capacitors and the capacitance of all MIM capacitors. Figure 6 The diagram illustrates that the total capacitance of capacitor structure 100 includes the capacitance of all MOM capacitors and the capacitance of a portion of the MIM capacitors. Figure 7 The diagram illustrates that the total capacitance of capacitor structure 100 includes the capacitance of all MOM capacitors. The total capacitance of capacitor structure 100 can be adjusted by changing the voltage values ​​of the first and second voltages in each voltage group. For MOM capacitors, the total capacitance of capacitor structure 100 may exclude the MOM capacitor values, include a portion of the MOM capacitor values, or include all of the MOM capacitor values; for MIM capacitors, the total capacitance of capacitor structure 100 may exclude the MIM capacitor values, include a portion of the MIM capacitor values, or include all of the MIM capacitor values. In other words, the total capacitance of capacitor structure 100 can be dynamically adjusted.

[0095] It should be understood that the term "in one embodiment" or "in an embodiment" as used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Therefore, appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-mentioned processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence of the above-mentioned embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0096] The preferred embodiments of the disclosure are described above, and the patent scope of the disclosure is not limited thereto. Any equivalent structure transformation made according to the disclosure, or direct / indirect application in other related technical fields within the concept of the disclosure is included in the patent protection scope of the disclosure.

Claims

1. A capacitive structure, characterized by, The capacitor structure comprises: n conductive structures arranged in a stack along a first direction, each of the conductive structures comprising a first conductive pattern and a second conductive pattern arranged along a second direction, the first conductive pattern and the second conductive pattern in each of the conductive structures forming an interdigital structure; wherein two of the first conductive patterns in two of the conductive structures arranged adjacently along the first direction at least partially overlap, and two of the second conductive patterns in two of the conductive structures arranged adjacently along the first direction at least partially overlap; the first direction and the second direction are perpendicular to each other, and n is an integer greater than 1.

2. The capacitance structure of claim 1, wherein, The capacitor structure comprises n first sub-capacitor structures, (n-1) second sub-capacitor structures, and (n-1) third sub-capacitor structures; wherein the first conductive pattern and the second conductive pattern in each of the conductive structures form the first sub-capacitor structure; two of the first conductive patterns in two of the conductive structures arranged adjacently along the first direction form the second sub-capacitor structure; and two of the second conductive patterns in two of the conductive structures arranged adjacently along the first direction form the third sub-capacitor structure.

3. The capacitance structure of claim 1, wherein, The n conductive structures comprise a first conductive structure and a second conductive structure arranged oppositely along the first direction; and the capacitor structure further comprises: (n-1) first adjustable resistance sets, each of the first adjustable resistance sets comprising a first adjustable resistance and a second adjustable resistance, two ends of each of the first adjustable resistances being used for connecting two of the first conductive patterns in two of the conductive structures arranged adjacently along the first direction, and two ends of each of the second adjustable resistances being used for connecting two of the second conductive patterns in two of the conductive structures arranged adjacently along the first direction; a second adjustable resistance set comprising a third adjustable resistance and a fourth adjustable resistance, two ends of the third adjustable resistance being used for connecting the first conductive pattern in the first conductive structure and a ground voltage, and two ends of the fourth adjustable resistance being used for connecting the second conductive pattern in the first conductive structure and the ground voltage; a third adjustable resistance set comprising a fifth adjustable resistance and a sixth adjustable resistance, two ends of the fifth adjustable resistance being used for connecting the first conductive pattern in the second conductive structure and a first voltage node, and two ends of the sixth adjustable resistance being used for connecting the second conductive pattern in the second conductive structure and a second voltage node.

4. The capacitance structure of claim 1, wherein, The first conductive pattern comprises: a first connecting portion extending along a third direction; a plurality of first tooth portions extending along the second direction, each of the first tooth portions comprising a first end portion and a second end portion arranged oppositely along the second direction, and the first end portion of each of the first tooth portions being connected to the first connecting portion; The second conductive pattern comprises: a second connecting portion extending along the third direction; a plurality of second tooth portions extending along the second direction, the second tooth portions comprising third end portions and fourth end portions oppositely arranged along the second direction, and the third end portions of the plurality of second tooth portions being connected with the second connecting portion; The second end portions of the plurality of first tooth portions are towards the second connecting portion, and the fourth end portions of the plurality of second tooth portions are towards the first connecting portion.

5. The capacitance structure of claim 1, wherein, The projections of the two first conductive patterns in the two conductive structures adjacently arranged along the first direction on a plane perpendicular to the first direction coincide with each other; The projections of the two second conductive patterns in the two conductive structures adjacently arranged along the first direction on a plane perpendicular to the first direction coincide with each other.

6. A method of adjusting the capacitance of a capacitive structure, comprising: The method is used for adjusting the total capacitance of the capacitive structure as claimed in any one of claims 1 to 5, and the method comprises: n voltage groups are provided, each of the voltage groups comprising a first voltage and a second voltage; wherein the n conductive structures and the n voltage groups are in one-to-one correspondence; n first voltages are respectively applied to the n first conductive patterns, and n second voltages are respectively applied to the n second conductive patterns.

7. The capacitance adjustment method according to claim 6, wherein The first voltage and the second voltage in each of the voltage groups are different; two first voltages applied to two first conductive patterns adjacently arranged along the first direction are different, and two second voltages applied to two second conductive patterns adjacently arranged along the first direction are different; The total capacitance of the capacitive structure comprises capacitances of n first sub-capacitive structures, capacitances of (n-1) second sub-capacitive structures, and capacitances of (n-1) third sub-capacitive structures; the first sub-capacitive structure is formed between the first conductive pattern and the second conductive pattern in each of the conductive structures; the second sub-capacitive structure is formed between two first conductive patterns in two conductive structures adjacently arranged along the first direction; and the third sub-capacitive structure is formed between two second conductive patterns in two conductive structures adjacently arranged along the first direction.

8. The capacitance adjustment method according to claim 6, wherein The first voltage and the second voltage in each of the voltage groups are different; two first voltages applied to two first conductive patterns adjacently arranged along the first direction are different, and two second voltages applied to two second conductive patterns adjacently arranged along the first direction are the same; The total capacitance of the capacitive structure comprises capacitances of n first sub-capacitive structures and capacitances of (n-1) second sub-capacitive structures; the first sub-capacitive structure is formed between the first conductive pattern and the second conductive pattern in each of the conductive structures; and the second sub-capacitive structure is formed between two first conductive patterns in two conductive structures adjacently arranged along the first direction.

9. The capacitance adjustment method according to claim 6, wherein The first voltage and the second voltage in each of the voltage groups are different; two first voltages applied to two first conductive patterns arranged adjacent along the first direction are the same, and two second voltages applied to two second conductive patterns arranged adjacent along the first direction are the same; The total capacitance value of the capacitive structure includes capacitance values of n first sub-capacitive structures; the first sub-capacitive structures are formed between the first conductive pattern and the second conductive pattern in each of the conductive structures.

10. The capacitance adjustment method of claim 6, wherein, The first voltage and the second voltage in each of the voltage groups are the same; two first voltages applied to two first conductive patterns arranged adjacent along the first direction are different, and two second voltages applied to two second conductive patterns arranged adjacent along the first direction are different; The total capacitance value of the capacitive structure includes capacitance values of (n-1) second sub-capacitive structures and (n-1) third sub-capacitive structures; the second sub-capacitive structures are formed between two first conductive patterns in two conductive structures arranged adjacent along the first direction; and the third sub-capacitive structures are formed between two second conductive patterns in two conductive structures arranged adjacent along the first direction.

Images