Modular exponentiation optimization method and device, equipment and storage medium

Abstract

The invention discloses a modular exponentiation optimization method, device and equipment and a storage medium, and relates to the technical field of cryptographic algorithms, and the modular exponentiation optimization method comprises the following steps: determining a target index according to a modular exponentiation task; based on a breadth-first search (BFS) algorithm, iterative node expansion is carried out, parallel modular exponentiation operation is carried out on sub-computing nodes obtained by each time of node expansion until the sub-computing nodes are expanded to target computing nodes, the optimal computing path and the final computing result of the modular exponentiation operation task are determined, and the target computing nodes are the target indexes. According to the scheme, the BFS algorithm and the modular exponentiation operation are deeply fused, and the parallel modular exponentiation operation is performed on the sub-computing nodes obtained by node expansion each time, so that the path search and the modular exponentiation operation are synchronously performed, the final computing result is obtained while the optimal computing path is found, and the execution efficiency of the modular exponentiation operation is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cryptography algorithms, and particularly relates to a modular exponentiation optimization method and device, equipment and a storage medium. BACKGROUND

[0002] RSA algorithm is a widely used asymmetric encryption algorithm in cryptography, and modular exponentiation is a core and time-consuming operation in RSA algorithm. The fast power algorithm is widely used in the industry to perform modular exponentiation, which alternately performs square and multiplication modulo operations by judging the binary bits of the exponent.

[0003] However, when facing an exponent of 4096 bits or larger, the calculation overhead of modular exponentiation using the fast power algorithm is huge, and there is a problem of insufficient operation efficiency, which is difficult to meet the needs of high-performance or real-time application scenarios.

[0004] Based on the above, how to improve the operation efficiency of modular exponentiation is a problem to be solved.

[0005] The above content is only used to assist in understanding the technical solutions of the present application, and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0006] The main purpose of the present application is to provide a modular exponentiation optimization method, device, equipment and storage medium, aiming at solving the technical problem of how to improve the operation efficiency of modular exponentiation.

[0007] To achieve the above purpose, the present application provides a modular exponentiation optimization method, which comprises: According to the modular exponentiation task, the target exponent is determined; Based on the breadth-first search (BFS) algorithm, the iterative node expansion is performed, and the parallel modular exponentiation is performed on the sub-computing nodes obtained by each node expansion until the target computing node is expanded, so as to determine the optimal computing path and the final computing result of the modular exponentiation task, wherein the target computing node is the target exponent.

[0008] In an embodiment, the step of performing iterative node expansion based on the breadth-first search (BFS) algorithm and performing parallel modular exponentiation on the sub-computing nodes obtained by each node expansion until the target computing node is expanded comprises: Initialize the computing queue, wherein the computing queue comprises an initial computing node and a computing step number of the initial computing node; Based on the BFS algorithm, the node expansion is performed on the initial computing node to obtain a plurality of sub-computing nodes, and the computing queue is updated according to the plurality of sub-computing nodes; performing parallel modular exponentiation on the plurality of sub-computing nodes to obtain modular exponentiation results of the plurality of sub-computing nodes, and storing the modular exponentiation results in a pre-computation table; When the plurality of sub-computing nodes do not include the target computing node, performing node expansion on the plurality of sub-computing nodes based on the BFS algorithm, updating a computing queue, and returning to performing parallel modular exponentiation on the plurality of sub-computing nodes to obtain modular exponentiation results of the plurality of sub-computing nodes, and storing the modular exponentiation results in a pre-computation table, until the plurality of sub-computing nodes include the target computing node.

[0009] In an embodiment, the step of performing node expansion on the plurality of sub-computing nodes based on the BFS algorithm and updating a computing queue comprises: For any sub-computing node, performing multiplication processing on the sub-computing node based on the BFS algorithm to obtain multiplication sub-nodes of the sub-computing node; Updating the computing queue according to the multiplication sub-nodes of the plurality of sub-computing nodes.

[0010] In an embodiment, the step of performing multiplication processing on the sub-computing node based on the BFS algorithm to obtain multiplication sub-nodes of the sub-computing node comprises: Based on the BFS algorithm, obtaining a preset number of multiplication computing nodes according to a preset number threshold; Multiplying the sub-computing node by the multiplication computing nodes to obtain a preset number of multiplication sub-nodes.

[0011] In an embodiment, the step of performing parallel modular exponentiation on the plurality of sub-computing nodes to obtain modular exponentiation results of the plurality of sub-computing nodes comprises: Based on a plurality of parallel units of a field programmable gate array (FPGA), performing parallel calculation to obtain modular exponentiation results of the preset number of multiplication sub-nodes according to an operation rule of a modulus and the pre-computation table.

[0012] In an embodiment, before the step of updating the computing queue according to the plurality of sub-computing nodes, the method comprises: Performing access checking on the plurality of sub-computing nodes through bit mask checking and / or parallel lookup table to determine unvisited sub-computing nodes; The step of updating the computing queue according to the plurality of sub-computing nodes comprises: Updating the computing queue according to the unvisited sub-computing nodes and the computing steps of the unvisited sub-computing nodes.

[0013] In an embodiment, the step of determining the optimal computing path and the final computing result of the modular exponentiation task comprises: determining a computing step number of the target computing node based on the computing queue, to obtain an optimal computing path of the modular exponentiation task; obtaining a modular exponentiation result of the target computing node from the pre-computed table as a final computing result of the modular exponentiation task.

[0014] In addition, to achieve the above object, the present application further provides a modular exponentiation optimization device, which comprises: a determining module configured to determine a target index according to a modular exponentiation task; a node expansion module configured to perform iterative node expansion based on a breadth-first search (BFS) algorithm, and perform parallel modular exponentiation on a sub-computing node obtained by each node expansion until the target computing node is expanded, to determine an optimal computing path and a final computing result of the modular exponentiation task, wherein the target computing node is the target index.

[0015] In addition, to achieve the above object, the present application further provides a modular exponentiation optimization device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the modular exponentiation optimization method as described above.

[0016] In addition, to achieve the above object, the present application further provides a storage medium, which is a computer-readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the modular exponentiation optimization method as described above.

[0017] The one or more technical solutions provided by the present application have at least the following technical effects: The modular exponentiation optimization method, device, equipment and storage medium provided by the present application specifically determine a target index according to a modular exponentiation task, perform iterative node expansion based on a breadth-first search (BFS) algorithm, and perform parallel modular exponentiation on a sub-computing node obtained by each node expansion until the target computing node is expanded, to determine an optimal computing path and a final computing result of the modular exponentiation task, wherein the target computing node is the target index.

[0018] The BFS algorithm is deeply integrated with the modular exponentiation operation, the node expansion of the target calculation node is performed through the iteration of the BFS algorithm, the parallel modular exponentiation operation is performed on the sub-calculation nodes obtained through each node expansion, the path search and the modular exponentiation operation are simultaneously performed, the calculation path generated by the BFS algorithm is more optimal than the fast power algorithm, the calculation amount is reduced, the calculation efficiency is improved by calculating the modular exponentiation result corresponding to the sub-calculation node of each node expansion in real time, the final calculation result is obtained while ensuring that the optimal calculation path is found, and the execution efficiency of the modular exponentiation operation is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings incorporated into the specification and constituting a part of the specification show embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings from these drawings without any creative effort.

[0021] Figure 1 A flowchart is provided for the first embodiment of the modular exponentiation optimization method of the present application. Figure 2 A flowchart is provided for the second embodiment of the modular exponentiation optimization method of the present application. Figure 3 A flowchart is provided for the third embodiment of the modular exponentiation optimization method of the present application. Figure 4 A flowchart is provided for the fourth embodiment of the modular exponentiation optimization method of the present application. Figure 5 A module structure diagram of the modular exponentiation optimization device of the embodiment of the present application is provided. Figure 6 A device structure diagram of the hardware running environment involved in the modular exponentiation optimization method in the embodiment of the present application is provided.

[0022] The purpose implementation, functional features and advantages of the present application will be further described with reference to the drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0024] In order to better understand the technical solutions of the present application, the drawings in the specification and the specific embodiments will be described in detail.

[0025] The main solution of the embodiment of the application is: determining a target exponent according to a modular exponentiation task; performing iterative node expansion based on a breadth-first search (BFS) algorithm, and performing parallel modular exponentiation on a sub-computing node obtained by each node expansion until the target computing node is expanded to, to determine an optimal computing path and a final computing result of the modular exponentiation task, wherein the target computing node is the target exponent.

[0026] Technical terms involved in the application: BFS (Breadth First Search) algorithm: the BFS algorithm is a graph traversal algorithm, and the core is to traverse the graph by level, starting from the starting node, preferentially accessing all adjacent nodes, and then expanding by level to perform node traversal until the target node is found.

[0027] FPGA (Field-Programmable Gate Array): FPGA is a customizable parallel computing hardware, which is programmed through a hardware description language, and the logic function is burned into the chip to realize hardware-level parallel processing. It is commonly used in communication signal processing, chip prototype verification, artificial intelligence acceleration and high-performance computing scenarios.

[0028] The RSA algorithm is a widely used asymmetric encryption algorithm in cryptography, and the modular exponentiation is a core and time-consuming operation in the RSA algorithm. The fast power algorithm is widely used in the industry to perform modular exponentiation, which alternately performs square and multiplication modulo operations by judging the binary bits of the exponent.

[0029] However, when facing an exponent of 4096 bits or larger, the calculation overhead of using the fast power algorithm for modular exponentiation is huge, and there is a problem of insufficient operation efficiency, which is difficult to meet the needs of high-performance or real-time application scenarios.

[0030] The application provides a solution that deeply integrates the BFS algorithm with modular exponentiation, expands nodes with the target exponent as the target computing node through BFS algorithm iteration, performs parallel modular exponentiation on the sub-computing node obtained by each node expansion, realizes simultaneous path search and modular exponentiation, generates a more optimal computing path than the fast power algorithm through the BFS algorithm, reduces the amount of calculation, and improves the computing efficiency by calculating the modular exponentiation result corresponding to each node expansion sub-computing node in real time, ensures that the optimal computing path is found while obtaining the final computing result, and effectively improves the execution efficiency of the modular exponentiation.

[0031] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a modular exponentiation optimization device capable of performing the above functions. The following description uses a modular exponentiation optimization device as an example to illustrate this embodiment and the subsequent embodiments.

[0032] Based on this, embodiments of this application provide an optimization method for modular exponentiation, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the modular exponentiation optimization method of this application.

[0033] In this embodiment, the modular exponentiation optimization method includes steps S110~S120: Step S110: Determine the target exponent based on the modular exponentiation task; Since this application applies to modular exponentiation in the RSA algorithm, the modular exponentiation task in this application addresses the large exponent modular exponentiation calculation requirements generated during the encryption process of the RSA algorithm, such as a^e mod n. Here, a is the target base of the modular exponentiation task, e is the target exponent, and n is the target modulus. The aforementioned modular exponentiation task is characterized by a huge exponent width, making direct calculation infeasible. The target exponent e is typically a large integer of 1024 bits or even 4096 bits in the RSA algorithm.

[0034] First, the modular exponentiation optimization device needs to determine the target exponent for the modular exponentiation task, which will then serve as the target node for the subsequent BFS algorithm to search for the optimal path.

[0035] Step S120: Based on the breadth-first search (BFS) algorithm, iterative node expansion is performed, and parallel modular exponentiation is performed on the sub-computation nodes obtained by each node expansion until the target computation node is reached. The optimal computation path and final computation result of the modular exponentiation task are determined, wherein the target computation node is the target exponent.

[0036] In this embodiment, the modular exponentiation task is transformed into a pathfinding problem using the BFS algorithm. Specifically, the optimal computation path for the modular exponentiation task is determined by searching the shortest path in the graph, which is the computation path that requires the fewest multiplications from the starting node to the target computation node.

[0037] Understandably, in this embodiment, the computational nodes in the search space constructed using the BFS algorithm correspond to a specific modular exponentiation intermediate value, and their node values ​​are the exponents of the modular exponentiation operation. For example, computational node k corresponds to the modular exponentiation calculation result of a^k mod n.

[0038] Since the modular exponentiation of the target index e needs to rely on the decomposition of the target index, the modular exponentiation result of the target index e is obtained by using the modular exponentiation intermediate value of the decomposed index to perform multiplication processing, and the following formula is referred to: a^e mod n=((a^e1 mod n)*(a^e2 mod n)) mod n, where e=e1+e2.

[0039] In the process of the BFS algorithm based on the graph to search the shortest path, the next layer of child computing nodes is obtained by expanding the nodes from the starting node. While determining the next layer of child computing nodes, the modular exponentiation processing of the next layer of child computing nodes is simultaneously performed by using multiple hardware threads of the hardware device in the same clock cycle to obtain the modular exponentiation intermediate value of the next layer of child computing nodes. The hardware device can be a multi-core processor, a GPU acceleration card or an FPGA hardware circuit.

[0040] When the next layer of child computing nodes is further expanded from the child computing nodes, the modular exponentiation intermediate value of the next layer of child computing nodes is calculated according to the modular exponentiation intermediate value calculated in the foregoing, and the final calculation result of the modular exponentiation task is calculated by relying on the calculated modular exponentiation intermediate value, and the optimal calculation path to the target computing node e is determined according to the visited path of the BFS algorithm in the search space.

[0041] The embodiment provides a modular exponentiation optimization method, which determines a target index according to a modular exponentiation task, performs iterative node expansion based on a breadth-first search BFS algorithm, and performs parallel modular exponentiation on child computing nodes obtained by each node expansion until the target computing node is expanded, to determine an optimal calculation path and a final calculation result of the modular exponentiation task, wherein the target computing node is the target index.

[0042] The BFS algorithm and the modular exponentiation are deeply integrated in the application, the node expansion with the target index as the target computing node is performed by the BFS algorithm iteration, the parallel modular exponentiation is performed on the child computing nodes obtained by each node expansion, the path search and the modular exponentiation are simultaneously performed, the BFS algorithm generates a more optimal calculation path than the fast power algorithm, the calculation amount is reduced, the calculation efficiency is improved by calculating the modular exponentiation result of the child computing nodes obtained by each node expansion in real time, the final calculation result is obtained while the optimal calculation path is ensured, and the execution efficiency of the modular exponentiation is effectively improved.

[0043] Based on the first embodiment of the application, in the second embodiment of the application, the same or similar contents as the above embodiments can be referred to the foregoing description, and will not be described hereinafter. On this basis, please refer to Figure 2, the breadth first search (BFS) algorithm, iteratively expands nodes and performs parallel modular exponentiation on each sub-computing node obtained by the node expansion until the target computing node is reached, and comprises steps S210-S240: Step S210, initializing a computing queue, wherein the computing queue comprises an initial computing node and a computing step number of the initial computing node; In order to realize node expansion and parallel modular exponentiation on sub-computing nodes, the modular exponentiation optimization device needs to initialize a computing queue for storing computing nodes to be processed.

[0044] The computing queue generally follows the first-in first-out principle, that is, the computing node entering the queue first is processed first. The initial computing node is stored in the computing queue, and the initial computing node is the starting point of the BFS algorithm for graph-based shortest path search. In this embodiment, the index corresponding to the initial computing node is 1, that is, the initial computing node is node 1.

[0045] The computing step number of the computing node refers to the minimum number of multiplication operations required to reach the computing node from the starting point, and the computing step number of the initial computing node is set to 0.

[0046] Step S220, based on the BFS algorithm, expanding nodes based on the initial computing node to obtain a plurality of sub-computing nodes, and updating the computing queue according to the plurality of sub-computing nodes; Step S230, performing parallel modular exponentiation on the plurality of sub-computing nodes to obtain modular exponentiation results of the plurality of sub-computing nodes, and storing the modular exponentiation results in a pre-computation table; Specifically, according to the BFS algorithm, the optimal computing path search of the modular exponentiation task is performed from the initial computing node, the initial computing node is expanded to the next layer of sub-computing nodes, a plurality of sub-computing nodes corresponding to the initial computing node are obtained, and then the plurality of sub-computing nodes of the next layer obtained by the expansion are put into the computing queue, and the computing queue is updated.

[0047] At the same time of expanding the plurality of sub-computing nodes corresponding to the initial computing node, the parallel computing unit of the FPGA performs parallel modular exponentiation processing on the plurality of sub-computing nodes of the next layer, thereby obtaining modular intermediate values corresponding to the plurality of sub-computing nodes, improving the computing efficiency, and solving the problem that the traditional fast power algorithm cannot be processed in parallel.

[0048] Then the modular intermediate values corresponding to the plurality of sub-computing nodes are stored in the pre-computation table, so as to continue the modular exponentiation processing by using the pre-computation table subsequently.

[0049] Step S240, when the target computing node does not exist in the plurality of sub-computing nodes, based on the BFS algorithm, node expansion is performed on the plurality of sub-computing nodes, the computing queue is updated, and the step of performing parallel modular exponentiation operation on the plurality of sub-computing nodes is returned to be executed until the target computing node exists in the plurality of sub-computing nodes.

[0050] Specifically, in the process of the BFS algorithm searching for the shortest path based on the graph, it is necessary to determine whether to continue the iterative search of the nodes by judging the condition of the plurality of sub-computing nodes obtained by each expansion. Specifically, it is determined whether to continue the node expansion by determining whether the target computing node exists in the plurality of sub-computing nodes of the next layer.

[0051] When it is determined that the target computing node e does not exist in the plurality of sub-computing nodes of the next layer, the plurality of sub-computing nodes are expanded again as parent nodes based on the BFS algorithm, the sub-computing nodes of the next layer are expanded again, and the plurality of sub-computing nodes obtained by the new round of node expansion are taken as the objects to be calculated in parallel, and the computing queue is updated synchronously. Step S230 is continued to obtain the modular intermediate values corresponding to the plurality of sub-computing nodes obtained by the new round of node expansion, and the modular intermediate values are stored in the pre-computation table until the node expansion reaches the target computing node e, it is determined that the target computing node e exists in the plurality of sub-computing nodes of the next layer, and the steps of node expansion and parallel modular exponentiation operation on the sub-computing nodes are stopped.

[0052] Further, since there may be repeated sub-computing nodes in the process of node expansion, before the step of updating the computing queue according to the plurality of sub-computing nodes, the step A1 is further included: Step A1, the plurality of sub-computing nodes are accessed and checked by bit mask checking and / or parallel lookup table to determine the unvisited sub-computing nodes. Specifically, in an embodiment, the modular exponentiation optimization device queries the node access state by bit mask checking, thereby distinguishing the visited sub-computing nodes from the unvisited sub-computing nodes. A bit array is used to record the access state of the nodes, wherein each bit represents whether a specific node has been processed, and the value of the corresponding bit (such as 0 representing unvisited and 1 representing visited) is checked to quickly determine the repeated nodes. In another embodiment, the modular exponentiation optimization device queries the node access state by parallel lookup table, specifically by constructing a key-value pair storage structure (i.e. parallel lookup table) supporting parallel query, taking the index value of the sub-computing node as the key and taking the flag bit representing whether it exists as the value, to quickly confirm whether the node has been accessed.

[0053] The step of updating the calculation queue according to the plurality of sub-computation nodes comprises step A2: Step A2, updating the calculation queue according to the unvisited sub-computation node and the calculation step number of the unvisited sub-computation node.

[0054] Specifically, the modular exponentiation optimization device puts the unvisited sub-computation node into the calculation queue while updating the calculation step number of the unvisited sub-computation node to its parent node algorithm step number plus 1. By associating the sub-computation node with its calculation step number and storing it in the calculation queue, not only the breadth-first traversal order required by the BFS algorithm is maintained, but also a basis for subsequent generation of the optimal calculation path is provided.

[0055] The embodiment provides a modular exponentiation optimization method, initializes a calculation queue, the calculation queue comprises an initial computation node and a calculation step number of the initial computation node; based on the BFS algorithm, node expansion is performed on the initial computation node to obtain a plurality of sub-computation nodes, and the calculation queue is updated according to the plurality of sub-computation nodes; parallel modular exponentiation is performed on the plurality of sub-computation nodes to obtain modular exponentiation results of the plurality of sub-computation nodes, and the modular exponentiation results are stored in a pre-computation table; when the plurality of sub-computation nodes do not contain the target computation node, based on the BFS algorithm, node expansion is performed on the plurality of sub-computation nodes to update the calculation queue, and the step of performing parallel modular exponentiation on the plurality of sub-computation nodes to obtain modular exponentiation results of the plurality of sub-computation nodes and storing the modular exponentiation results in the pre-computation table is returned until the plurality of sub-computation nodes contain the target computation node.

[0056] The embodiment performs graph-based optimal calculation path search through the BFS algorithm, and synchronously utilizes the hardware characteristics of the FPGA to distribute the modular exponentiation tasks of the sub-computation nodes obtained through each node expansion to a plurality of parallel computing units for execution, greatly compresses the overall calculation time of the modular exponentiation tasks of the target exponent, and thus effectively improves the modular exponentiation efficiency.

[0057] Based on the above-mentioned embodiments of the application, in the third embodiment of the application, the same or similar contents as the above-mentioned embodiments can be referred to the above introduction, and will not be described in detail. On this basis, please refer to Figure 3 The step of updating the calculation queue according to the plurality of sub-computation nodes comprises steps S310-S330: Step S310, for any sub-computation node, based on the BFS algorithm, multiplication processing is performed on the sub-computation node to obtain multiplication sub-nodes of the sub-computation node; Specifically, the modular exponentiation optimization device obtains the next layer of sub-computing nodes corresponding to the sub-computing nodes, i.e., multiplication sub-nodes, through multiplication processing in the process of node expansion of a plurality of sub-computing nodes.

[0058] In this embodiment, for any one sub-computing node to be expanded, the operation of multiplying the exponent value corresponding to the current sub-computing node k by a multiple of 2, i.e., multiplying the sub-computing node by itself, i.e., calculating 2k or k+k, obtains the multiplication sub-node 2k of the current sub-computing node, wherein the operation of multiplying the exponent value corresponding to the sub-computing node k by a multiple of 2 is equivalent to the squaring operation in the modular exponentiation operation.

[0059] Through the BFS algorithm, the addition operation of the exponent value corresponding to the current sub-computing node k and the exponent value corresponding to a visited sub-computing node m is performed, i.e., k+m is calculated, to obtain the multiplication sub-node k+m of the current sub-computing node. The addition operation of the exponent values is equivalent to the multiplication operation in the modular exponentiation operation. The visited sub-computing node refers to a sub-computing node that has been visited in the shortest path search process of the BFS algorithm and generates a corresponding modular exponentiation intermediate value.

[0060] In an implementable manner, the step S310 includes steps B1-B2: Step B1, based on the BFS algorithm, a predetermined number of multiplication computing nodes are obtained according to a predetermined number threshold; Step B2, multiplying the sub-computing node by the multiplication computing node to obtain a predetermined number of multiplication sub-nodes.

[0061] Specifically, in order to avoid the exponential explosion of multiplication sub-nodes, the modular exponentiation optimization device does not select multiplication with all visited sub-computing nodes when expanding the multiplication sub-nodes of the current sub-computing node.

[0062] By setting a threshold E for the multiplication sub-nodes in advance, the last E-1 visited sub-computing nodes are found in reverse order from the visited sub-computing nodes, and the current sub-computing node is multiplied by the multiplication computing nodes together with the current sub-computing node. The predetermined number threshold is a value set by relevant personnel according to the actual needs (such as efficiency) of modular exponentiation optimization.

[0063] By multiplying the E multiplication computing nodes with the current sub-computing node respectively, E multiplication sub-nodes are generated.

[0064] For example, in a specific embodiment, the current sub-computing node k = 3, the accessed sub-computing node set contains node 1 and node 2. When the preset number threshold E = 2, only the recently accessed 1 node (assuming node 2) and node 3 itself are used as multiplication computing nodes to perform multiplication processing, generating multiplication sub-node 5 and multiplication sub-node 6.

[0065] In this embodiment, the computing complexity of node expansion is controlled by adding a preset number threshold to reduce invalid node generation, so that the path search image of the BFS algorithm is as single-sided as possible, saving computing space.

[0066] Step S320, updating the computing queue according to the multiplication sub-nodes of the plurality of sub-computing nodes. For the plurality of sub-computing nodes of the current layer, the node expansion is performed through the above step S310, and the new sub-computing nodes obtained by the node expansion, i.e. the multiplication sub-nodes of the plurality of sub-computing nodes of the current layer, are used as the sub-computing nodes to be processed by the modular exponentiation operation.

[0067] Further, the step of performing parallel modular exponentiation operation on the plurality of sub-computing nodes to obtain the modular exponentiation operation results of the plurality of sub-computing nodes comprises the following step C1: Step C1, based on a plurality of parallel units of a field programmable gate array (FPGA), performing parallel calculation according to the modulus operation rule and the pre-computed table to obtain the modular exponentiation operation results of the preset number of multiplication sub-nodes.

[0068] Specifically, the modular exponentiation optimization device utilizes a plurality of parallel computing units of the FPGA to perform calculation processing according to the modulus multiplication operation rule of the same base power, such as ((a^b mod n) * (a^c mod n)) mod n = a^(b+c) mod n, that is, first calculating the modular exponentiation intermediate value of a^b mod n, then calculating the modular exponentiation intermediate value of a^c mod n, then multiplying the two modular exponentiation intermediate values, and then taking the product mod n again, and finally obtaining the result equal to the result of directly calculating a^(b+c) mod n.

[0069] Specifically, according to the above modulus multiplication operation rule of the same base power, the modular exponentiation intermediate value of the sub-computing node is obtained from the pre-computed table to perform square processing and take modulus, or the modular exponentiation intermediate value of the sub-computing node and other multiplication computing nodes is obtained from the pre-computed table to perform multiplication processing and take modulus, to obtain the modular exponentiation operation result of the multiplication sub-node of the sub-computing node.

[0070] The embodiment expands the next layer of sub-computing nodes by performing multiplication processing on the sub-computing nodes, and further expands the path search space. The multiplication processing can combine different explored paths to discover new computing possibilities, and further discover shorter computing paths, so as to quickly find the optimal computing path of the modular exponentiation operation task and improve the modular exponentiation operation efficiency.

[0071] Based on the above embodiments, in the fourth embodiment of the present application, the same or similar contents as the above embodiments can be referred to the above description, and will not be described in detail. On this basis, please refer to Figure 4 The step of determining the optimal computing path and the final computing result of the modular exponentiation operation task includes steps S410-S420. Step S410, based on the computing queue, determining the computing step number of the target computing node, and obtaining the optimal computing path of the modular exponentiation operation task. Specifically, when the target computing node e is first accessed, the modular exponentiation operation optimization device needs to obtain the computing step number information of the target computing node from the computing queue, so as to determine the minimum number of multiplication operations required to reach the target computing node e from the initial computing node.

[0072] Then, the optimal computing path of the modular exponentiation operation task is reconstructed in reverse according to the minimum number of multiplication operations and the predecessor node of each sub-computing node recorded by each expansion node.

[0073] Step S420, obtaining the modular exponentiation result of the target computing node from the pre-computed table as the final computing result of the modular exponentiation operation task.

[0074] Specifically, the modular exponentiation operation optimization device queries the modular exponentiation result corresponding to the target computing node e in the pre-computed table to obtain the final computing result of the modular exponentiation operation task, that is, the modular exponentiation result corresponding to the target index e, the value of a^e mod n.

[0075] The embodiment combines the BFS algorithm with the parallel computing unit of the FPGA to synchronously implement the optimal computing path search based on the graph and the modular exponentiation operation processing on the sub-computing nodes in parallel, finally determines the optimal computing path of the modular exponentiation operation task according to the computing queue, and determines the final computing result of the modular exponentiation operation task according to the pre-computed table.

[0076] The present application also provides a modular exponentiation operation optimization device, please refer to Figure 5 The modular exponentiation operation optimization device includes: A determination module 10 is configured to determine a target index according to a modular exponentiation operation task. The node expansion module 20 is configured to perform iterative node expansion based on a breadth-first search (BFS) algorithm, and perform parallel modular exponentiation on each sub-computing node obtained through the node expansion until a target computing node is reached, so as to determine an optimal computing path and a final computing result of the modular exponentiation task, wherein the target computing node is the target exponent.

[0077] The modular exponentiation optimization device provided in the present application adopts the modular exponentiation optimization method in the above embodiment, and can solve the technical problem of how to improve the operation efficiency of modular exponentiation. Compared with the prior art, the modular exponentiation optimization device provided in the present application has the same beneficial effects as the modular exponentiation optimization method provided in the above embodiment, and other technical features in the modular exponentiation optimization device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0078] The present application provides a modular exponentiation optimization device, which comprises a processor and a memory connected with the processor in communication. The memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to perform the modular exponentiation optimization method in the above embodiment.

[0079] Reference will be made to the following description Figure 6 which shows a structural schematic diagram of a modular exponentiation optimization device suitable for implementing the embodiments of the present application. The modular exponentiation optimization device in the embodiments of the present application can include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description), PMPs (Portable Media Player), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. Figure 6 The modular exponentiation optimization device shown is only an example, and should not impose any limitation on the functions and use range of the embodiments of the present application.

[0080] As Figure 6As shown, the modular exponentiation optimization device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read-only memory 1002 or loaded from a storage device 1003 into a random access memory 1004. Various programs and data required for the modular exponentiation optimization device to operate are also stored in the random access memory 1004. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other by a bus 1005. An input / output interface 1006 is also connected to the bus. Generally, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the modular exponentiation optimization device to communicate with other devices wirelessly or by wire to exchange data. Although the modular exponentiation optimization device with various systems is shown in the figure, it should be understood that all the shown systems are not required to be implemented or possessed. More or fewer systems can be alternatively implemented or possessed.

[0081] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program codes for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication device, or installed from the storage device 1003, or installed from the read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are performed.

[0082] The modular exponentiation optimization device provided by the present application adopts the modular exponentiation optimization method in the above embodiments, and can solve the technical problem of how to improve the operation efficiency of modular exponentiation. Compared with the prior art, the modular exponentiation optimization device provided by the present application has the same beneficial effects as the modular exponentiation optimization method provided by the above embodiments, and other technical features in the modular exponentiation optimization device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0083] It should be understood that various aspects of the disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any appropriate manner in any one or more embodiments or examples.

[0084] The above description is merely illustrative of the application and is not intended to limit the scope of the application. Any variations and modifications that can be made by any person skilled in the art within the spirit and scope of the application are intended to be encompassed by the application. The scope of the application is defined by the appended claims.

[0085] The application provides a computer readable storage medium having computer readable program instructions (i.e. computer programs) stored thereon, the computer readable program instructions being used to perform the modular exponentiation optimization method in the above embodiments.

[0086] The computer readable storage medium provided by the application may, for example, be a U disk, but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system or device, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present embodiment, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer readable storage medium can be transmitted by any appropriate medium, including but not limited to electrical wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0087] The above computer readable storage medium can be included in the modular exponentiation optimization device; or can exist separately and not be assembled into the modular exponentiation optimization device.

[0088] The computer readable storage medium described above carries one or more programs, when the one or more programs are executed by the modular exponentiation optimization device, cause the modular exponentiation optimization device to: determine a target exponent according to a modular exponentiation task; perform iterative node expansion based on a breadth-first search (BFS) algorithm, and perform parallel modular exponentiation on a sub-computing node obtained by each node expansion until a target computing node is expanded, to determine an optimal computing path and a final computing result of the modular exponentiation task, wherein the target computing node is the target exponent.

[0089] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0090] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functionalities, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a procedure, or a part of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that noted in the figures. For example, two blocks noted in succession can in fact be executed substantially concurrently or in the opposite order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0091] The modules involved in the embodiments of the present application can be implemented in a software manner or in a hardware manner. In some cases, the names of the modules do not constitute a limitation on the modules themselves.

[0092] The readable storage medium provided by the present application is a computer readable storage medium, which stores computer readable program instructions (i.e. computer program) for executing the modular exponentiation optimization method described above, and can solve the technical problem of how to improve the operation efficiency of modular exponentiation. Compared with the prior art, the computer readable storage medium provided by the present application has the same beneficial effects as the modular exponentiation optimization method provided by the above-mentioned embodiments, and will not be described here.

[0093] The present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the modular exponentiation optimization method as described above.

[0094] The computer program product provided by the present application can solve the technical problem of how to improve the operation efficiency of modular exponentiation. Compared with the prior art, the computer program product provided by the present application has the same beneficial effects as the modular exponentiation optimization method provided by the above-mentioned embodiments, and will not be described here.

[0095] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent processing scope of the present application.

Claims

1. A method for optimizing modular exponentiation, characterized in that, The modular exponentiation optimization method includes: Determine the target exponent based on the modular exponentiation task; Based on the breadth-first search (BFS) algorithm, iterative node expansion is performed, and parallel modular exponentiation is carried out on the sub-computation nodes obtained by each node expansion until the target computation node is reached. The optimal computation path and final computation result of the modular exponentiation task are determined, wherein the target computation node is the target exponent.

2. The modular exponentiation optimization method as described in claim 1, characterized in that, The steps of iteratively expanding nodes based on the breadth-first search (BFS) algorithm, and performing parallel modular exponentiation on the sub-computation nodes obtained in each expansion until the target computation node is reached, include: Initialize the computation queue, which includes the initial computation node and the computation steps of the initial computation node; Based on the BFS algorithm, the initial computing node is expanded to obtain several sub-computing nodes, and the computing queue is updated according to the several sub-computing nodes. Parallel modular exponentiation is performed on the plurality of sub-computation nodes to obtain the modular exponentiation results of the plurality of sub-computation nodes, and the modular exponentiation results are stored in a pre-computation table; When the target computing node is not present among the several sub-computing nodes, based on the BFS algorithm, the several sub-computing nodes are expanded, the computing queue is updated, and the execution steps are returned: parallel modular exponentiation is performed on the several sub-computing nodes to obtain the modular exponentiation results of the several sub-computing nodes, and the modular exponentiation results are stored in the pre-computation table until the target computing node exists among the several sub-computing nodes.

3. The modular exponentiation optimization method as described in claim 2, characterized in that, The steps of expanding the number of sub-computing nodes and updating the computation queue based on the BFS algorithm include: For any sub-computation node, based on the BFS algorithm, multiplication is performed on the sub-computation node to obtain the multiplication sub-node of the sub-computation node; Update the computation queue based on the multiplication sub-nodes of the aforementioned sub-computation nodes.

4. The modular exponentiation optimization method as described in claim 3, characterized in that, The step of performing multiplication on the sub-computation nodes based on the BFS algorithm to obtain the multiplied sub-nodes of the sub-computation nodes includes: Based on the BFS algorithm, a preset number of multiplication calculation nodes are obtained according to a preset number threshold. Multiply the sub-computation node with the multiplication calculation node to obtain a preset number of multiplication sub-nodes.

5. The modular exponentiation optimization method as described in claim 4, characterized in that, The step of performing parallel modular exponentiation on the plurality of sub-computing nodes to obtain the modular exponentiation results of the plurality of sub-computing nodes includes: Based on multiple parallel units of a field-programmable gate array (FPGA), and according to the modulo operation rules and the pre-calculation table, the modular exponentiation results of the preset number of multiplication sub-nodes are calculated in parallel.

6. The modular exponentiation optimization method as described in claim 2, characterized in that, Before the step of updating the computing queue based on the plurality of sub-computing nodes, the following are included: Access checks are performed on the plurality of sub-computing nodes by bitmask checking and / or parallel lookup tables to determine the unaccessed sub-computing nodes; The step of updating the computing queue based on the plurality of sub-computing nodes includes: Update the computation queue based on the number of computation steps for each unvisited child compute node.

7. The modular exponentiation optimization method as described in claim 2, characterized in that, The steps for determining the optimal computation path and final computation result of the modular exponentiation task include: Based on the computation queue, the number of computation steps for the target computation node is determined, and the optimal computation path for the modular exponentiation task is obtained. The modular exponentiation result of the target computing node is obtained from the pre-computation table and used as the final calculation result of the modular exponentiation task.

8. A modular exponentiation optimization device, characterized in that, The modular exponentiation optimization device includes: The determination module is used to determine the target exponent based on the modular exponentiation task; The node expansion module is used to iteratively expand nodes based on the breadth-first search (BFS) algorithm, and perform parallel modular exponentiation operations on the sub-computation nodes obtained by each node expansion until the target computation node is reached. The module determines the optimal computation path and the final computation result of the modular exponentiation task, wherein the target computation node is the target exponent.

9. A modular exponentiation optimization device, characterized in that, The modular exponentiation optimization device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the modular exponentiation optimization method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the modular exponentiation optimization method as described in any one of claims 1 to 7.

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