GPU fragment stream processing method

Abstract

The invention provides a GPU (Graphics Processing Unit) fragment stream processing method, which comprises the following steps that: in a graphic rendering pipeline, after series coordinate conversion, primitives in a scene body are sent to a Raster for rasterization scanning, and the Raster scans and outputs the primitives according to a row mode on the basis of the input sequence of the primitives; distributing the plurality of fragments subjected to rasterization scanning to a plurality of shaders for coloring; the colored fragments are sequentially sent to a plurality of ROP units according to the row mode for fragment operation processing, and each ROP unit carries out fragment operation processing on the fragments of the fixed row; and outputting the fragment pixels processed by each ROP unit according to a sequence, and writing the fragment pixels back to the frame buffer area through the fragment cache. According to the method, all processing is carried out according to the input sequence of the primitives when the primitives are subjected to rasterization scanning, fragment coloring, fragment operation and writing back to the frame buffer area, and all processing multifunctional components are completely independent, so that the sequence and data consistency in the processing process of numerous primitive fragments is ensured.

Description

Technical Field

[0001] This invention relates to the field of GPU graphics rendering, and more specifically, to a GPU fragment stream processing method. Background Technology

[0002] With the continuous increase in the complexity of graphics rendering and the improvement of display resolution and frame rate, GPUs (Graphics Processing Units) have evolved into innovative architectures with multiple dedicated computing cores. This has enabled a fundamental transformation from quickly processing single tasks to parallel processing of massive tasks, and from dedicated graphics processors to general-purpose parallel computing engines, supporting the technological foundation for high-fidelity real-time graphics rendering and high-performance computing. However, in addition to the unified shader handling highly realistic lighting effects, fog effects, and texture mapping, high-fidelity graphics rendering also involves a large amount of computation in fragment streams. Key operations such as depth testing, stencil testing, color blending, logical operations, and multi-buffer accumulation in fragment operations also contribute to the rendering of complex visual effects.

[0003] In the process of processing numerous primitives, when the Raster receives small and complex primitives (many vertices and few fragments), the fragments rendered by different shaders may not be on the same layer. In this case, fragment shading may result in out-of-order reception and transmission, which can easily lead to data consistency issues. Summary of the Invention

[0004] This invention addresses the technical problems existing in the prior art by providing a GPU fragment stream processing method that can overcome the issues of sequence and data consistency in primitive processing.

[0005] This invention provides a GPU fragment stream processing method, comprising:

[0006] In the graphics rendering pipeline, after a series of coordinate transformations, the primitives within the view volume are sent to the Raster for rasterization scanning. The Raster scans and outputs the primitives in rows based on the order of primitive input.

[0007] Assign multiple segments of the rasterized scan to multiple shaders for coloring;

[0008] The colored fragments are sent to multiple ROP units in a row-by-row manner for fragment operation processing. Each ROP unit performs fragment operation processing only on fragments in a fixed row.

[0009] The pixel information processed by each ROP unit is output in sequence and written back to the frame buffer after passing through the fragment buffer.

[0010] This invention provides a GPU fragment stream processing method. In the graphics rendering pipeline, after a series of coordinate transformations, primitives within the view frustum are sent to a raster for rasterization scanning. The raster scans and outputs the primitives in rows based on their input order. Multiple rasterized fragments are assigned to multiple shaders for shading. The shaded fragments are then sent to multiple ROP units in row-wise order for fragment operation processing. Each ROP unit performs fragment operation processing only on a fixed row of fragments. The processed fragment pixels from each ROP unit are output in sequence and written back to the frame buffer via a fragment buffer. This invention performs all processing according to the primitive input order during primitive rasterization scanning, fragment shading, fragment operation, and writing back to the frame buffer. Furthermore, all processing multi-functional components are completely independent, ensuring the order and data consistency throughout the processing of numerous primitive fragments. Attached Figure Description

[0011] Figure 1 A flowchart of a GPU fragment stream processing method provided in one embodiment of the present invention;

[0012] Figure 2 This is an architecture diagram of a GPU fragment stream processing procedure according to an embodiment of the present invention;

[0013] Figures 3(a) to 3(f) A diagram illustrating multiple shader tasks performed by multiple shaders;

[0014] Figure 4 This is a schematic diagram of the internal structure of ROP Cache;

[0015] Figure 5 A schematic diagram of the binary tree structure for the improved PLRU algorithm. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0017] Before describing the present invention, the concepts involved in the present invention will be explained.

[0018] ROP: Render Output Unit.

[0019] Primitive occlusion refers to the phenomenon where, when viewing a scene from a specific perspective, primitives closer to the camera (such as triangles or line segments) block primitives behind or overlapping with them, preventing them from being seen.

[0020] Layers: A core graphic organization method that breaks down a complex visual image into multiple transparent planes stacked one on top of the other.

[0021] View volume: Defines the area in 3D space that is "seen" by the virtual camera and is about to be rendered onto the screen. It is usually a pyramid shape with the top truncated, enclosed by the near clipping plane, the far clipping plane, and the four side clipping planes. Objects within this view volume are visible, while objects outside this range are automatically culled by the system and not rendered.

[0022] Data consistency: The core concept of measuring whether data is in the same logical state across the entire system or multiple nodes does not require that the physical copies of the data be exactly the same at all times. Rather, it ensures that no matter from which access point the data is read, the data can present the latest update results or follow the predetermined business rules, thereby avoiding contradictions or confusion.

[0023] Core utilization: quantifies how busy one or more processor cores are performing effective computing tasks within a specific time period.

[0024] Pixel fill rate: A key performance indicator for measuring the rendering capability of a graphics processing unit (GPU). It is the maximum number of pixels that the GPU can draw on the screen in one second. This value directly reflects the speed at which the GPU processes rasterized segments (i.e., pixels). Its level is mainly determined by the core rendering frequency and the number of ROPs.

[0025] In high-fidelity graphics rendering, the speed at which pixels are written back to the frame buffer is one of the main factors determining the final frame rate of the GPU. However, fast write-back is not an isolated operation, but rather the ultimate manifestation of efficient collaboration throughout the entire rendering pipeline. This goal is achieved through a combination of methods, including selecting appropriate rendering paths and functionalities, optimizing shading programs, and utilizing GPU hardware features.

[0026] In addition, operations such as data processing between multiple buffers, clearing and masking buffers require the design of an efficient and universal ROP cache suitable for graphics rendering (applicable to both color and depth / stencil) to accelerate data reading and writing.

[0027] GPUs now mostly employ multi-core computing arrays to process data / tasks in parallel, which is also designed to accelerate fragment shading and improve fragment stream output. To match the processing power of GPU multi-core computing, ROPs (Render Output Units) are usually designed in multiples. To improve the write-back speed of the entire GPU pixel, color information and depth / stencil information in the ROP unit also need to be processed in parallel. This invention provides a complete design method for fragment stream processing to accelerate the efficiency of primitive fragment processing while solving the data consistency problem during parallel processing.

[0028] In particular, GPU graphics rendering is often highly sensitive to the order of the rendered objects. Multi-core computing arrays have very powerful data / task processing capabilities. The rendering of various tasks (vertex shading, tessellation, geometry shading and fragment shading) is carried out completely independently and in parallel among multiple processors. However, the rendered vertex data and primitive information need to be output in a specified order, otherwise it will cause occlusion problems between the front and back.

[0029] Based on this Figure 1 This invention illustrates a GPU fragment stream processing method, such as... Figure 1 and Figure 2 As shown, the method includes the following steps:

[0030] Step 1: In the graphics rendering pipeline, after a series of coordinate transformations, the primitives within the view volume are sent to the Raster for rasterization scanning. The Raster scans and outputs the primitives in rows based on the order of primitive input.

[0031] Understandably, in the field of GPU graphics rendering, primitives undergo a series of coordinate transformations in the graphics rendering pipeline before being sent to a raster for rasterization scanning. In this embodiment of the invention, rasterization scans and outputs basic primitives such as points, lines, and triangles in a row-by-row manner.

[0032] Specifically, the primitives within the scene are sent to the raster for rasterization scanning, including:

[0033] Record the order in which multiple graphic elements are input;

[0034] Based on the order of multiple primitive inputs, each primitive is scanned row by row to obtain all scanned segments, and all scanned segments are output in chronological order.

[0035] Step 2: Assign multiple segments of the rasterized scan to multiple shaders for shading.

[0036] In one embodiment of the present invention, assigning multiple segments of rasterized scanning to multiple shaders for coloring includes:

[0037] All segments after rasterization scanning are divided into multiple coloring tasks in chronological order, and each coloring task includes multiple segments to be colored;

[0038] Multiple shading tasks are assigned to multiple shaders for shading, resulting in shading fragments. All shading fragments are then output in sequence, with the next fragment only output after all fragments of a primitive have been output.

[0039] Understandably, the data consistency handling mechanism during fragment scanning and shading is as follows: When the Raster receives large and simple primitives (few vertices, many fragments), the continuity of the scanned fragments is good. When all shaders render fragments on the same layer, there are no fragment processing dependencies, and fragment shading can be received and sent out of order without queuing. When the Raster receives small and complex primitives (many vertices, few fragments), fragments rendered by different shaders may not be on the same layer. In this case, the order of primitive input must be recorded, fragment shading must be performed in sequence, and fragment shading must be completed according to the recorded primitive order before sending the fragments of the next primitive.

[0040] When coloring the scanned fragments, all fragments after rasterization scanning are divided into multiple coloring tasks in chronological order, with each coloring task containing multiple fragments to be colored. Then, the multiple coloring tasks are assigned to multiple shaders.

[0041] In one embodiment of the present invention, each shader can process multiple fragments in parallel and cache multiple fragments that have completed the shading process and are waiting to be output at the same time.

[0042] The process of assigning multiple shading tasks to multiple shaders for shading, obtaining shaded fragments, and outputting all shaded fragments in sequential order includes:

[0043] Multiple shader tasks are assigned to multiple shaders in sequence, where a shader can only execute one shader task at a time.

[0044] Each shader colors the fragments to be colored in its assigned shader task and caches the colored fragments. After caching, the shader can receive new coloring tasks for coloring processing.

[0045] Each shader outputs its shaders in the order they are scheduled to be shaded. If a shader that has been shaded earlier has not yet been output, it must wait for the shader to output the shader in its buffer before it outputs the shader in its buffer.

[0046] Understandably, to improve the core utilization of shaders, each shader can not only process multiple fragment data in parallel at the same time, but also cache a batch of processed fragment data waiting to be output. For example, if there are currently 4 shaders with 9 fragment coloring tasks to execute, when all shaders are in an idle state, a task is assigned to each shader in turn. At this time, all shaders are in a busy state and need to wait for the task to be completed and the result to be stored in the cache before they can receive a new task. At this time, the shader is processing the new task while waiting for the cached data to be sent. If the new task has been completed but the cached data has not yet been output, the shader will be in a waiting state.

[0047] Figures 3(a) to 3(f) illustrate the process of four shaders executing nine fragment shading tasks. In Figure 3(a), all four shaders are in an idle state. In Figure 3(b), tasks 0 through 3 are assigned to shaders 0 through 3 respectively. In Figure 3(c), task 2 is completed and the shading fragment cache is full; at this point, shader 2 can accept the new task 4 for shading. In Figure 3(d), tasks 1 and 3 are completed and the shading fragment cache is full; shaders 1 and 3 can accept the new tasks 5 and 6. In Figure 3(e), task 0 is completed and the shading fragment cache is full; shader 0 accepts the new task 7. At this point, cache 0 outputs the shading fragment, cache 0 becomes empty, and after shader 0 completes shading task 7, it stores the shading fragment in cache 7. In Figure 3(f), shader 0 can accept the new task 8 for shading.

[0048] In the above-described coloring process, in a worst-case scenario, as shown in Figure 3(d), the first batch of tasks assigned to shaders 1, 2, and 3 has been executed and cached, and the second batch of tasks has been received. When the second batch of tasks for shaders 1, 2, and 3 has also been executed, but task 0 assigned to shader 0 has not yet been executed, all shaders will be in a waiting state. Only after shader 0 has executed and cached task 0 can task 7 be assigned, and at this time it can only be assigned to shader 0. Since cached data must be output strictly in the order of recording, data from cache 1, etc., cannot be output until all data from cache 0 has been output. The entire task allocation process is shown in Figures 3(a) to 3(f). Because the underlying driver usually splits / merges tasks, the allocated tasks are mostly relatively balanced.

[0049] To maximize pixel fill rate and improve GPU performance, the scan rate of the Raster, the processing speed of the shaders, and the execution rate of fragment operations in the ROP (Render Output Unit) need to be balanced. In this design, each shader can process a maximum of 32 fragments at the same time and can also cache a maximum of 32 fragment data. Therefore, when all scanned fragments are divided into multiple shading tasks in sequence, a single shading task can only contain a maximum of 32 fragments.

[0050] Multiple shaders color the fragments in sequence, outputting the colored fragments for each primitive and each scan line in turn.

[0051] Step 3: The colored fragments are sent to multiple ROP units in a row-by-row manner for fragment operation processing. Each ROP unit performs fragment operation processing only on fragments in a fixed row.

[0052] Understandably, the colored fragments from step 2 are processed in a row-by-row manner, with each row's colored fragment sent to the corresponding ROP unit for fragment operation. Each ROP unit processes only a fixed number of rows of fragments (e.g., with 4 ROP units, ROP unit 0 processes 4n rows, ROP unit 1 processes 4n+1 rows, ROP unit 2 processes 4n+2 rows, and ROP unit 3 processes 4n+3 rows, where n is a natural number). Each ROP unit also needs a corresponding synchronization mechanism to ensure that commands and data correspond perfectly for each fragment operation, and that the fragment output order matches the input order perfectly. However, multiple ROP units can process fragments within different primitives simultaneously. Since each ROP unit processes only a fixed number of rows of fragments, this indirectly solves the problem of ROPCache data consistency.

[0053] Specifically, the steps for fragment operations include:

[0054] Generate a fragment queue by order of all colored fragments, and divide all fragments in the fragment queue into rows.

[0055] Assign the fragment and command data of each line to the corresponding ROP unit;

[0056] Each ROP unit parses the command, performs fragment operations on the corresponding line fragments according to the parsed command configuration, and sends all the operated fragments to the corresponding fragment cache.

[0057] Understandably, see Figure 2The process involves generating a fragment queue from all shaded fragments in chronological order, and then dividing all fragments in the queue into rows. Each row of fragments and its associated command is then assigned to a corresponding ROP unit. The ROP unit first parses the command to obtain its command configuration, which specifies the operations the ROP unit will perform on the fragment, including testing the fragment's color, depth, and stencil information.

[0058] In this embodiment of the invention, the ROP unit performs fragment operations by testing the color information, template information, and / or depth information of each fragment according to a command. After the test is passed, each ROP unit sends all the fragments after the fragment operation test to the fragment cache in chronological order, and accesses the memory of all the fragments after the operation based on the fragment cache.

[0059] Step 4: Output the pixel information processed by each ROP unit in sequence and write it back to the frame buffer through the fragment buffer.

[0060] Understandably, after multiple ROP units have operated on all fragments, they output the processed fragment information (including fragment color information, template information, and depth information) in sequence and allocate it to the corresponding fragment buffer. The fragment information is then written back to the frame buffer after passing through the fragment buffer. The number of fragment buffers is the same as the number of ROP units; the fragment information processed by one ROP unit is sent to the corresponding fragment buffer.

[0061] In one embodiment of the present invention, each fragment cache includes two mirrored ROP caches, one of which can process the color information of the fragment, and the other of which can process the depth / template information of the fragment. Each ROP cache includes multiple cache lines, and each cache line can store 32 pixels of color components, or 32 pixels of depth components and template components, i.e., 128B, wherein the color components are 32 bits, the depth components are 24 bits, and the template components are 8 bits.

[0062] Understandably, to enable parallel processing of color and depth / stencil information, each fragment cache contains two completely mirrored ROP caches. The cache functionality can vary depending on the application scenario, and there's no longer a strict distinction between color and depth / stencil caches. For the ROP cache, in addition to reading and writing data, it needs to support clearing, copying, and reading / writing specified buffers—that is, handling large blocks of data. Furthermore, it needs to support the operation of flushing all client data back to the server after an OpenGL frame of graphics rendering is complete. Since the entire graphics processing is highly order-sensitive, the cache should also adhere to the order of fragments, while also satisfying the write-before-read order. That is, the read operation must be completed after the previous batch of data has been written (not necessarily written back to the frame buffer; it can remain in the cache, but the read data must be the updated data) before responding to the read operation.

[0063] See Figure 4 In one embodiment of the present invention, each ROP Cache includes an input arbitration module, a cache controller, a miss module, a write cache unit, and a replacement unit.

[0064] The input arbitration module receives requests from the ROP unit, arbitrates them according to the priority of clear request > write request > read request > refresh request, and sends the arbitration result to the Cache controller.

[0065] The cache controller processes requests sent from the ROP unit and controls data storage, mask storage, dirty bit storage, and tag information storage.

[0066] The replacement unit receives the miss information from the cache controller and performs cache line replacement according to the replacement algorithm.

[0067] The miss module caches read / write miss request information and initiates a read request to the specified buffer, and caches the data read back from the specified buffer. If data needs to be written back to the specified buffer, the write request and write data are cached, and then the write cache unit initiates a write operation to write the data back to the specified buffer.

[0068] Understandably, the overall structure of ROP Cache is as follows: Figure 4As shown, the input arbitration module receives, caches, and arbitrates requests sent by the ROP unit, arbitrating them according to the priority of clear request > write request > read request > refresh request, and sends the arbitration result to the Cache controller for operation to control the storage of read and write data, mask information, "dirty" information, and tag information. The replacement unit receives cache miss information from the Cache controller, performs cache line replacement according to the replacement algorithm, and simultaneously caches read and write miss request information and initiates a read request to the designated buffer, while also caching the data read back from the designated buffer. If data needs to be written back to the designated buffer, the miss module needs to cache the write request and write data, and then the write cache module initiates the write operation. The write strategy in the cache adopts the Write Back + Write Allocation method.

[0069] The replacement unit receives cache miss information from the cache controller and performs cache line replacement according to the replacement algorithm, including:

[0070] A binary tree structure is used to store the historical access order information of multiple cache lines in the same group;

[0071] Multiple registers are configured to store the root node information of the binary tree structure. When an access is missing, the cache line to be replaced is determined based on the values ​​of the multiple registers.

[0072] Understandably, cache line replacement strategies have always been a key focus of graphics processing research. For scenarios where graphics rendering data exhibits good locality, the LRU (Least Recently Used) replacement algorithm is typically used. However, this algorithm requires recording every cache line and updating it with each incoming request, resulting in significant hardware overhead. This invention provides an improved PLRU replacement algorithm that uses a flag on each node to record the access status of the corresponding cache line, thereby determining which cache lines are least recently used and then replacing them.

[0073] Following the general PLRU (Pseudo-LRU) design, a binary tree structure is used to store the historical access order information of cache lines. When a cache line is accessed, it is updated according to the update rules. However, analysis revealed that if a cache line in the same group has just been accessed, another cache line, even if it has been the least used, will not be replaced. Therefore, the PLRU algorithm was improved. For example, each group includes four cache lines, and two registers are added to each group to store root node information. When a cache line is missing, the root node register is used to determine how to replace it. For details on the binary tree structure, see [link to binary tree structure]. Figure 5 , Figure 5 This paper demonstrates a binary tree structure for an improved pseudo-LRU (PLRU) algorithm used for replacement decisions in a 4-way set-associative cache. The core of this algorithm is to record the access history of cache lines using status bits and a tree structure, achieving efficient replacement block selection. The following is a detailed explanation of each component:

[0074] 1. Top-level status registers (P1, P0, B0):

[0075] P1 and P0: 2-bit registers used to mark "whether the same top-level group is accessed continuously", which is a core new design improvement of PLRU.

[0076] Values ​​00 or 11 indicate that the same top-level group is accessed consecutively (replacement must be prioritized within this group).

[0077] Values ​​01 or 10 indicate non-continuous access (regressing to the global replacement logic of the underlying PLRU).

[0078] B0: The root node, which is the top-level branch point of the binary tree. The branch direction of the next level is determined by the state of P1 and P0 (0 or 1).

[0079] 2. Middle-level nodes (B1, B2):

[0080] B1: Left subtree node, corresponding to "top-level group G0" (containing two cache lines, WAY L0 and WAY L1).

[0081] B2: Right subtree node, corresponding to "top-level group G1" (containing two cache lines, WAY L2 and WAY L3).

[0082] The branch direction (0 or 1) is determined by the upper-level node (B0) and the status bits (P1, P0), and is used to filter "subgroups that have not been visited for a longer time".

[0083] 3. Low-level Cache Line (WAY L0~L3):

[0084] WAY L0~L3: Represents the four cache lines (i.e., the four memory blocks within the set) in a 4-way set-associative network.

[0085] WAY L0 and L1 belong to the top-level group G0 (managed by node B1);

[0086] WAY L2 and L3 belong to the top-level group G1 (managed by node B2).

[0087] 4. Replace decision logic (combining structure and state bits):

[0088] When a cache access is missing, the replacement process is as follows:

[0089] Determine the status of continuous access: Determine whether the same top-level group is accessed continuously by using the values ​​of P1 and P0.

[0090] If P1 and P0 are 00 or 11: Force the selection of a replacement block within the currently accessed group (e.g., if P1P0=00, then select group G0, i.e., WAY L0 / L1 under branch B1).

[0091] If P1P0 is 01 or 10: According to the basic PLRU logic, starting from the root node B0, the least accessed cache line is selected level by level according to the branch direction (0 / 1).

[0092] Traverse the binary tree to select the replacement block: from B0 to B1 / B2, and then to WAY L0~L3. The branch direction of each level is determined by the corresponding state bit (such as the internal state of B1 and B2), and finally locate the "least accessed" cache line for replacement.

[0093] The replacement module selection is shown in Table 1.

[0094] Table 1 Improved PLRU Replacement Block Selection Table

[0095]

[0096] The core idea of ​​ROP Cache is to leverage the spatial locality of fragment access to cache the color and depth / template information of neighboring fragments in on-chip high-speed memory. This allows most depth testing, blending, and other operations to quickly obtain the color or depth / template information values ​​in the target buffer, reducing the access frequency of off-chip memory and meeting the high throughput real-time rendering requirements of the GPU.

[0097] The GPU fragment stream processing method provided in this embodiment of the invention has the following effects:

[0098] (1) It provides a complete solution for GPU fragment stream processing, from fragment scanning to fragment shading to fragment operation to the final pixel write-back to the frame buffer. The processing method is advanced. Fragment scanning, fragment shading and fragment operation are performed according to the order of primitive input, and the processed fragments are output in the order of input. It solves the long-standing problem of data consistency in graphics processing. Furthermore, from method design and software modeling to the final simulation verification, the feasibility of the design method and the rationality and efficiency of the structural design are confirmed.

[0099] (2) The ROP Cache has a clear and easy-to-implement circuit structure, which significantly improves the read and write access performance of large blocks of data and is suitable for graphics processing applications. In particular, the improved PLRU replacement strategy optimizes the block selection method, greatly reduces the complexity of circuit design, saves resource overhead, reduces power consumption, and improves the cache hit rate.

[0100] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0102] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A GPU fragment stream processing method, characterized in that, include: In the graphics rendering pipeline, after a series of coordinate transformations, the primitives within the view volume are sent to the Raster for rasterization scanning. The Raster scans and outputs the primitives in rows based on the order of primitive input. Assign multiple segments of the rasterized scan to multiple shaders for coloring; The colored fragments are sent to multiple ROP units in a row-by-row manner for fragment operation processing. Each ROP unit performs fragment operation processing only on fragments in a fixed row. The pixel information processed by each ROP unit is output in sequence and written back to the frame buffer after passing through the fragment buffer.

2. The GPU fragment stream processing method according to claim 1, characterized in that, The step of sending primitives within the scene to the raster for rasterization scanning includes: Record the order in which multiple graphic elements are input; Based on the sequential order of multiple primitive inputs, each primitive is scanned row by row to obtain all the scanned segments; The step of assigning multiple segments of rasterized scanning to multiple shaders for shading includes: All segments after rasterization scanning are divided into multiple coloring tasks in chronological order, and each coloring task includes multiple segments to be colored; Multiple shading tasks are assigned to multiple shaders for shading, resulting in shading fragments. All shading fragments are then output in sequence, with the next fragment only output after all fragments of a primitive have been output.

3. The GPU fragment stream processing method according to claim 2, characterized in that, Each shader can process multiple fragments in parallel at the same time and buffer multiple fragments that have completed the shading process and are waiting to be output; The process of assigning multiple shading tasks to multiple shaders for shading, obtaining shaded fragments, and outputting all shaded fragments in sequential order includes: Multiple shader tasks are assigned to multiple shaders in sequence, where a shader can only execute one shader task at a time. Each shader colors the fragments to be colored in its assigned shader task and caches the colored fragments. After caching, the shader can receive new coloring tasks for coloring processing. Each shader outputs its shaders in the order they are scheduled to be shaded. If a shader that has been shaded earlier has not yet been output, it must wait for the shader to output the shader in its buffer before it outputs the shader in its buffer.

4. The GPU fragment stream processing method according to claim 2, characterized in that, Each shader can process a maximum of 32 fragments at any given time, and can also cache a maximum of 32 fragments. Each shading task includes a maximum of 32 fragments to be shaded.

5. The GPU fragment stream processing method according to claim 1, characterized in that, The colored fragments are sent to multiple ROP units in a row-by-row manner for fragment operation processing. Each ROP unit performs fragment operation processing on a fixed number of rows of fragments, including: Generate a fragment queue by order of all colored fragments, and divide all fragments in the fragment queue into rows. Assign the fragments and commands of each line to the corresponding ROP unit; Each ROP unit parses the command, performs fragment operations on the corresponding row of fragments according to the parsed command configuration, and sends all pixel information after the operation to the corresponding fragment buffer. The number of fragment buffers is the same as the number of ROP units.

6. The GPU fragment stream processing method according to claim 5, characterized in that, Perform fragment operations on the corresponding rows of fragments according to the parsed command configuration, and send all pixel information after the operation to the corresponding fragment buffer, including: Each ROP unit sends all pixel information after the fragment operation to the corresponding fragment buffer in the order of the operation, and accesses all fragments after the operation based on the fragment buffer.

7. The GPU fragment stream processing method according to claim 5, characterized in that, Perform fragment operations on the corresponding rows of fragments according to the parsed command configuration, and send all pixel information after the operation to the corresponding fragment buffer, including: Each segment is tested according to the command configuration; After the test is passed, the color information and depth / template information of each segment are written back to the frame buffer through the segment buffer in sequence.

8. The GPU fragment stream processing method according to claim 7, characterized in that, Each fragment cache includes two mirrored ROP caches. One ROP cache processes the fragment's color information, and the other ROP cache processes the fragment's depth / template information. Each ROP cache includes multiple cache lines, and each cache line can store 32 color components or depth / template components of a fragment, wherein the color component is 32 bits, the depth component is 24 bits, and the template component is 8 bits.

9. The GPU fragment stream processing method according to claim 8, characterized in that, Each of the ROP Caches includes an input arbitration module, a cache controller, a miss module, a write cache unit, and a replacement unit; The input arbitration module receives requests sent by the ROP unit, arbitrates them according to the priority of clear screen request > write request > read request > refresh request, and sends the arbitration result to the Cache controller. The Cache controller operates on requests sent by the ROP unit and controls data storage, mask storage, dirty bit storage, and tag information storage. The replacement unit receives the miss information from the Cache controller and performs Cache Line replacement according to the replacement algorithm. The miss module caches read / write miss request information and initiates a read request to a specified buffer, and caches the data read back from the specified buffer. If data needs to be written back to the specified buffer, the write request and write data are cached, and then the write cache unit initiates a write operation to write the data back to the specified buffer.

10. The GPU fragment stream processing method according to claim 9, characterized in that, The replacement unit receives the cache miss information from the cache controller and performs cache line replacement according to the replacement algorithm, including: A binary tree structure is used to store the historical access order information of multiple cache lines in the same group; Multiple registers are configured to store the root node information of the binary tree structure. When an access is missing, the cache line to be replaced is determined based on the values ​​of the multiple registers.

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