High-energy-efficiency logarithm floating point multiplier based on truncation error compensation

Abstract

The invention discloses a high-energy-efficiency logarithm floating point multiplier based on truncation error compensation. The system comprises a compensation parameter modeling unit and a floating point multiplier module. The compensation parameter modeling unit obtains an optimal compensation value k through linear fitting and parameter optimization, and realizes regional self-adaptive compensation in combination with block modeling so as to reduce truncation errors; the floating point multiplier module comprises a special value detection module, a symbol exclusive or module, an exponential addition module and a mantissa truncation compensation module. In a logarithm domain, multiplication is replaced by addition, and compensation logic is introduced to correct errors. The multiplier supports various floating point precisions and configurable truncation bit widths, provides three representative structures to give consideration to both the precision and the energy efficiency, and is suitable for high-energy-efficiency calculation scenes such as neural networks and image processing.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuit design and approximate computing, and particularly relates to a high energy-efficient logarithmic floating-point multiplier based on truncated error compensation. BACKGROUND

[0002] With the rapid development of artificial intelligence and Internet of Things technology, floating-point multiplication operation has become the main source of energy consumption in neural network forward calculation and image processing applications. The floating-point multiplication under the traditional IEEE754 standard needs to perform complex mantissa multiplication, exponent addition and result normalization operations, resulting in large hardware resource occupation and high power consumption.

[0003] In application scenarios with certain fault tolerance characteristics, such as neural networks and image processing, approximate computing techniques can significantly improve energy efficiency while allowing for slight precision loss. The logarithmic approximation method proposed by Mitchell converts the mantissa multiplication operation into addition, thereby simplifying the calculation process. However, due to the systematic negative bias of the linear approximation model, it is easy to cause cumulative error, affecting the overall calculation reliability.

[0004] Although existing logarithmic floating-point multipliers have proposed various improvement algorithms, there is still a problem of difficulty in balancing precision and energy efficiency. Some designs can approach the precision of the exact multiplier in terms of precision, but the hardware area and power consumption are limited; other structures achieve significant resource savings, but at the cost of large precision loss. Therefore, there is an urgent need for a high energy-efficient logarithmic floating-point multiplication structure that can effectively reduce power consumption and hardware complexity while ensuring calculation accuracy, to achieve a better balance between precision and energy efficiency. SUMMARY

[0005] The purpose of the present application is to provide a high energy-efficient logarithmic floating-point multiplier based on truncated error compensation. By establishing a truncated error model and performing parameterized compensation optimization, the power consumption, delay and hardware complexity are significantly reduced while maintaining acceptable calculation accuracy. The technical solution of the present application is described as follows.

[0006] A high energy-efficient logarithmic floating-point multiplier based on truncated error compensation can be used in edge AI chips, neural network accelerators and image processing chips, which includes a sign bit XOR module, an exponent bit addition module and a mantissa bit truncation addition and compensation module; The sign bit XOR module is used to perform XOR operation on the sign bits of two input operands to obtain the result sign; The exponent bit addition module is used to perform addition on the exponents of two operands in the shift code representation, and to realize exponent summation through one-time bias correction, thereby reducing the calculation delay; The mantissa bit truncation addition and compensation module is used for bit width truncation of input mantissa to reduce hardware overhead, and the truncated mantissa is converted from multiplication to addition through logarithmic transformation; in the logarithmic transformation process, a straight line m+k is used to linearly fit a logarithmic function log2(m+1), so that a piecewise linear plane is used to approximate a hyperbolic paraboloid corresponding to a mantissa product in a three-dimensional space; fixed or block compensation logic is introduced in the addition stage and the inverse logarithmic transformation stage to compensate and correct system errors caused by logarithmic linearization based on the parameter k, so that the energy-efficient recovery of the mantissa operation result is realized.

[0007] In the application, the special case processing module is also included, which is used for detecting whether the input operand is infinite or non-number value, and setting the corresponding flag bit when the special value is detected to indicate that the operation result is invalid.

[0008] In the application, the mantissa bit truncation addition and compensation module performs unbiased truncation operation on the input mantissa, reduces the bit width from q bits to q-t bits, t represents the number of truncated bits, and forces 1 on the least significant bit after truncation to offset the systematic deviation.

[0009] In the application, the fixed compensation logic in the mantissa bit truncation addition and compensation module includes: using a discrete sampling and numerical optimization algorithm to optimize the parameter k, and minimizing the objective function to realize global minimization of the truncation error, and the optimal compensation parameter k is taken as its binary approximation value in hardware implementation to reduce the calculation complexity. In a specific embodiment, the numerical optimization algorithm is L-BFGS-B algorithm, and the objective function is , wherein, represents the approximate product result of the i-th group of data, represents the corresponding accurate reference value.

[0010] In the application, the mantissa bit truncation addition and compensation module is configured in two structure modes based on the fixed compensation logic: The LTAM1 structure adopts the fixed carry injection and all-1 bit supplement strategy to realize hardware priority design; The LTAM2 structure introduces a one-stage independent adder in the compensation and inverse transformation stage to improve the calculation accuracy, and includes an overflow detection mechanism.

[0011] In the application, the block compensation logic in the mantissa bit truncation addition and compensation module includes: dividing the input mantissa space into a plurality of blocks , and independently solving the optimal compensation parameter for each block; the block mode includes uniform division and non-uniform division mode, the compensation parameter k is obtained by minimizing the average absolute error of each block, and the look-up table type region adaptive compensation is realized according to the high bit index of the input mantissa.

[0012] In this invention, the mantissa truncation, addition, and compensation module is configured with the following structural mode based on block compensation logic: The LTAM-LUT structure uses a region adaptive lookup table compensation method, which selects the corresponding block compensation value based on the high-order index of the input mantissa.

[0013] In this invention, the mantissa truncation, addition and compensation module also transmits a carry signal to the exponent part in the mantissa operation result to adjust the floating-point number format; finally, the multiplier output is a floating-point number output that conforms to the IEEE 754 standard, formed by combining the compensated mantissa with the corresponding exponent and sign bit.

[0014] In this invention, the multiplier supports multiple floating-point precision formats, including IEEE 754 double precision (FP64), single precision (FP32), half precision (FP16), and custom floating-point formats with lower bit widths; the mantissa truncation bit width can be flexibly configured according to application requirements, and while maintaining a balance between computational accuracy and hardware resources, a dynamic trade-off between energy efficiency and accuracy can be achieved by adjusting the truncation depth.

[0015] Compared with existing approximate floating-point multipliers, the present invention has the following advantages: High structural scalability: This invention proposes three representative compensation mechanisms and circuit structures for different application scenarios, which can be flexibly selected according to hardware resources and accuracy requirements. For the block error compensation method, the number of blocks can be adjusted to meet the accuracy requirements of different applications. This compensation strategy is applicable to various accuracy specifications (such as FP32, FP16) and has good scalability and adaptability.

[0016] Balancing energy efficiency and accuracy: This invention significantly reduces the bit width and carry propagation path of mantissa calculation by introducing a truncation strategy during logarithmic and antilogarithmic transformations, thereby reducing the area and power consumption of the adder and inverse transformation circuit. An error compensation mechanism is introduced in the logarithmic domain to effectively suppress the systematic negative bias introduced by the Mitchell linear approximation. Through fixed compensation or lookup table compensation mechanisms, the performance of the power-delay product (PDP) can be significantly improved with only a slight loss of accuracy.

[0017] Wide applicability: This invention adopts a modular structure design with clear logic, good synthesizability and portability, and is easy to implement on FPGA or ASIC platforms. This structure can be widely used in edge AI chips, neural network accelerators, and image processing chips, and has high versatility and engineering value. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the three-dimensional error distribution in the product domain for exact multiplication and the traditional Mitchell approximation algorithm.

[0019] Figure 2 The diagram shows the two-dimensional error distribution and block compensation schematic of the exact multiplication and the traditional Mitchell approximation algorithm.

[0020] Figure 3 This is a block diagram of the overall structure of the logarithmic floating-point multiplier described in this invention, and a schematic diagram of the structure of three mantissa calculation optimization circuits (LTAM1, LTAM2, LTAM-LUT).

[0021] Figure 4 The graph shows a performance comparison of the three logarithmic floating-point multipliers proposed in this invention under MRED and PDP metrics, and compares them with existing advanced approximation multipliers.

[0022] Figure 5 This graph shows the performance comparison results between the multiplier of this invention and an accurate multiplier in image processing and neural network applications. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0024] This invention provides a high-efficiency logarithmic floating-point multiplier based on truncation error compensation, comprising a compensation parameter modeling unit and a floating-point multiplier hardware module; wherein: Compensation parameter modeling unit: In the logarithmic transformation process, a straight line is used. Logarithmic function A linear fit is performed to approximate the hyperbolic paraboloid relationship corresponding to the mantissa product in three-dimensional space as a piecewise linear plane. The optimal compensation parameters are then iteratively solved by discretely sampling the input mantissas and combining this with a numerical optimization algorithm. This minimizes the global mean relative error (MRED); further, the mantissa input space is divided into several blocks according to the high-order index. The optimal compensation value is calculated independently within each block. A regional adaptive compensation model is constructed based on the criterion of minimizing the mean absolute error, thereby effectively improving the uniformity of error distribution and enhancing the overall numerical accuracy and stability. The floating-point multiplier hardware module includes units for special value detection, signed XOR, exponent addition, and mantissa truncation compensation. In the operation process, the input is first checked for infinity or non-numerical values; then, the sign bit is XORed to obtain the sign of the result; the exponents are added in offset binary representation and bias correction is performed; the mantissa is truncated and the addition operation is completed in the logarithmic field. Compensation logic is introduced during the addition and antilogarithmic transformation stages to correct linearization errors, ultimately outputting a floating-point result conforming to the IEEE 754 standard.

[0025] In this invention, within the floating-point multiplier hardware module, a special case handling module uses a comparator to detect the exponent and mantissa fields of the input operands. When operand A or B is infinity (Inf) or not a number (NaN), the corresponding flag is set to 1 to indicate that the result of this operation is invalid. The exponent width is denoted as w, and the result width after the operation is w+2. The two highest bits are used as sign extension bits for overflow detection. When the two highest bits are 2'b01, it indicates a positive overflow, and the result saturates to infinity; when the two highest bits are 2'b11, it indicates a negative overflow, and the result output is zero; in other cases, the valid value of the lower w bits is retained.

[0026] In this invention, in the floating-point multiplier hardware module, the exponent addition module first subtracts the bias amount in the IEEE 754 standard to eliminate the bias effect, then adds the two exponents, and then adds the bias amount back. To simplify the calculation, this invention combines the above three steps into an equivalent operation of "adding the exponents and then subtracting the bias amount", thereby reducing the calculation delay.

[0027] In this invention, the mantissa truncation, addition, and compensation module in the floating-point multiplier hardware module first truncates the input mantissa to reduce the bit width and decrease circuit area and power consumption. Simultaneously, the least significant bit after truncation is forcibly set to 1 to compensate for systematic biases. The truncated mantissa is transformed to the logarithmic domain, converting multiplication to addition. Compensation logic is introduced during the addition stage to correct approximation errors and improve computational accuracy. In the antilogarithmic transformation stage, mantissa recovery is achieved through bit rearrangement and padding, further compensating for approximation errors. During mantissa operations, a carry signal is also transmitted to the exponent to adjust the floating-point format. Finally, the compensated mantissa, combined with the corresponding exponent and sign bit, forms a floating-point output conforming to the IEEE 754 standard.

[0028] In this invention, to further improve energy efficiency in different scenarios, three representative structures are proposed in the mantissa truncation, addition, and compensation module: (1) LTAM1 structure (hardware priority): This structure achieves fixed compensation based on the k value obtained from modeling without adding an additional adder stage. The compensation logic effectively suppresses systematic errors while maintaining a minimal circuit design by injecting a carry signal into the mantissa adder and forcing the truncation bit to 1 during the inverse logarithmic transformation stage.

[0029] (2) LTAM2 structure (precision priority): This structure introduces an independent compensated adder, which can perform compensation calculations based on the k value more accurately. Although it increases the addition delay by one level, it significantly improves the accuracy stability and is suitable for scenarios that require higher precision calculations.

[0030] (3) LTAM-LUT structure (lookup table compensation): This structure divides the mantissa interval into multiple error blocks. The optimal k value is pre-calculated within each block and stored in a miniature lookup table. During computation, the corresponding compensation value is accessed based on the high-order index of the input mantissa to achieve regional adaptive compensation. This method further reduces MRED under controllable hardware costs and has strong scalability and flexibility.

[0031] The following are specific examples.

[0032] like Figure 1 As shown, for the product of two mantissas (m1 and m2), subtracting the output obtained by the exact multiplier from the result obtained by the traditional Mitchell approximation yields the corresponding error distribution surface. From a three-dimensional perspective, this error surface lies entirely above the zero plane, indicating that the Mitchell approximation exhibits a systematic underestimation across the entire product domain. Projecting this three-dimensional error surface from above yields a two-dimensional error distribution map, as shown below. Figure 2 As shown, it can be clearly observed that the error is mainly concentrated in the boundary region near m1 + m2 = 3. Therefore, a specific compensation strategy is needed to effectively correct the systematic bias caused by the Mitchell approximation. The approximation formula after correction by the compensation parameter k is as follows:

[0033] This formula is equivalent to using a straight line m + k to linearly fit the logarithmic function log2(m + 1) during the logarithmic transformation, thus approximating the hyperbolic paraboloid corresponding to the mantissa product in three-dimensional space using a piecewise linear plane. To determine the optimal value of parameter k, the input mantissas m1 and m2 are first discretized, and 1000 points are uniformly sampled within the interval to construct a 10 6 Groups of product data samples. Based on the L-BFGS-B algorithm, to minimize the global relative error and the objective function. To optimize the criterion, the parameter k is iteratively adjusted until it gradually converges to the optimal solution. Among these adjustments, This represents the approximate product result of the i-th set of data. This represents the corresponding precise reference value. The final result is k = 0.02251, corresponding to an MRED of approximately 2.56%. Compared to the Mitchell approximation, this method introduces both positive and negative errors during the fitting process, allowing them to cancel each other out during calculation, thus significantly improving the accuracy of the results. The compensation value after logarithmic summation is calculated as 2k = 0.04502, whose binary representation is 0.000010111…. To simplify hardware implementation, the lower-weighted bits are discarded, and the final binary form of the compensation value is determined to be 0.000010111. This compensation value can be further combined with a mantissa truncation strategy to effectively reduce circuit complexity and power consumption while maintaining computational accuracy, thereby achieving higher energy efficiency optimization.

[0034] To further improve the uniformity of error distribution and reduce local error peaks, this invention proposes a lookup table compensation mechanism based on block modeling. In this scheme, the mantissa input space is divided into a 4×4 grid, and in each block... The optimal compensation parameters are determined by minimizing the mean absolute error (MAE). ,like Figure 2 As shown, this invention performs post-processing on the compensation parameters of each block: the compensation value of the lower left region is directly applied, the compensation value of the upper right region is half of its value, and the compensation value of the diagonal region is divided by 1.5. This mapping effectively reflects the transformation law from the linear product domain to the logarithmic addition domain, making the compensation process more consistent with the characteristics of the logarithmic domain. The average error of each block, after being corrected under the MAE criterion, is considered the optimal compensation value, thereby achieving adaptive correction for different input intervals. After compensation processing, local peak values ​​are significantly reduced, and the error distribution tends to be more uniform. Experimental results show that the standard deviation of the error distribution decreases significantly, indicating that the error concentration phenomenon is effectively suppressed, thus achieving more stable computational performance in hardware implementation.

[0035] This invention proposes a complete logarithmic floating-point multiplier structure based on truncation error compensation, such as... Figure 3 As shown in (a), this architecture constructs a complete arithmetic path including the sign bit, exponent part, and mantissa part, and integrates a special value handling mechanism to ensure that the calculation conforms to the IEEE 754 standard. In the input stage, the circuit first uses combinational logic to detect whether operands A and B are special values ​​(such as Inf or NaN). The detection logic uses a parallel comparator to determine the exponent and mantissa fields. When a special value is detected, the corresponding flag bit is set to 1 to indicate that the result of this operation is invalid.

[0036] For ordinary floating-point number input, the sign bit is determined by the XOR operation of the operand signs. The exponent processing unit is responsible for exponent summation and overflow management. The input exponent is first subtracted from the IEEE 754 bias value. The result is converted to two's complement form and then summed. This combines the traditional three steps of bias restoration, addition, and re-biasing into a single operation, thus shortening the critical path. The resulting exponent Ep is w+2 bits, where the two highest bits are used for overflow determination: when Ep[w+1:w]=2'b01, it indicates a positive overflow, and the output saturates to infinity; when Ep[w+1:w]=2'b11, it indicates a negative overflow, and the output is set to zero; otherwise, Ep[w-1:0] is retained as the result exponent.

[0037] The mantissa processing unit transforms the mantissa into the logarithmic domain to perform addition. Compensation logic is introduced in both the addition and antilogarithm transformation stages to correct approximation errors. Simultaneously, antilogarithm transformation is achieved through bit rearrangement and padding, thus restoring the multiplication result without introducing additional arithmetic circuitry. This architecture supports flexible configuration, including mantissa truncation depth, compensation methods, and padding modes, to achieve a balance between computational accuracy and hardware overhead. The mantissa calculation process consists of four key stages: (1) Truncation operation phase: Perform the following on the input mantissa. and By reducing the bit width from q bits to (qt) bits and performing truncation during logarithmic transformation, circuit area and power consumption can be effectively reduced. To maintain the unbiasedness of the truncation process, this invention forces a 1 on the least significant bit after truncation to compensate for systematic truncation bias. Considering the balance between computational accuracy and hardware resource overhead, this embodiment retains a 6-bit mantissa width after truncation, thus achieving an optimal trade-off between energy efficiency and accuracy.

[0038] (2) Logarithmic field addition stage: By utilizing the equivalence relation of logarithmic multiplication and addition, the multiplication log(A×B) is transformed into the addition log(A)+log(B), thereby realizing the rapid combination and simplified operation of mantissas in the logarithmic field, significantly reducing the complexity of the multiplier. At the same time, the error of logarithmic transformation is compensated by adding an adder or using carry signals to improve the calculation accuracy.

[0039] (3) Anti-logarithmic transformation stage: According to different compensation strategies, error compensation is introduced in the bit recombination and padding mode implementation process to correct the system error caused by the anti-logarithmic transformation, thereby achieving a balance between computational accuracy and hardware overhead. At the same time, the anti-logarithmic transformation is completed and the carry signal Tag for exponential normalization is generated during this process.

[0040] (4) Result encapsulation stage: The mantissa after compensation is concatenated with the corresponding exponent and sign bit to form a floating-point output result that conforms to the IEEE 754 standard format.

[0041] like Figure 3 As shown in (b), the LTAM1 structure (hardware-first) first truncates the mantissa to 6 bits using an unbiased truncation method. Based on the aforementioned error modeling analysis, the theoretical ideal compensation value is 0.000010111000…000. To balance hardware friendliness and approximate accuracy, LTAM1 employs an "all-1 padding" mode combined with a strategy of fixing the carry as 1, thereby achieving an approximate compensation value of 0.00000111…111. This compensation value is numerically close to the theoretical optimum and also possesses an extremely simple circuit implementation: by fixing the carry input of the adder to 1 and fixing the truncated carry... t Setting all bits to 1 allows for connection via wires, eliminating the need for additional logic gates and effectively reducing circuit complexity and latency.

[0042] like Figure 3 As shown in (c), the LTAM2 structure (precision-first) introduces a higher-precision compensation mechanism based on LTAM1 to further reduce the systematic errors caused by logarithmic and anti-logarithmic transformations. Unlike LTAM1, LTAM2 introduces an additional adder in the compensation and inverse transformation stages to increase the compensation value. 0.000010 And use a fill mode when the number of anti-variables changes. 11100…000 To more accurately approximate the theoretical optimal compensation value. 0.000010111000…000 Meanwhile, LTAM2 introduces an overflow detection mechanism to ensure numerical stability. This mechanism monitors the carry signal of the most significant bit of the adder. OF To determine if the result exceeds the range [0,1). OF = 1 When the product result exceeds 2 in the linear domain, the multiplexer is in a state where... OF Under the control of [the system], the high-order bits of the mantissa are filled with all 1s to achieve saturation protection; when [the mantissa is filled with all 1s]... OF = 0 If the condition is met, the compensation result will be output normally. Through this mechanism, LTAM2 improves accuracy while ensuring numerical stability.

[0043] like Figure 3As shown in (d), the LTAM-LUT structure (adaptive compensation) employs a micro lookup table (micro LUT) to implement a region adaptive compensation method. In this embodiment, the region index consists of the two most significant bits of the input mantissa, i.e., select = {MA[q−1:q−2], MB[q−1:q−2]}, thus dividing the input space into 16 regions. Unlike the globally unified compensation value used by LTAM1 and LTAM2, LTAM-LUT configures compensation parameters independently for each region, which are obtained by calculating MAE. The results show that the optimal compensation value is concentrated in a few discrete values, so the lookup table can be implemented by combinational logic without additional storage units. Compensation only applies to the high-order part of the mantissa to correct the main truncation error, thereby reducing latency and power consumption while ensuring accuracy.

[0044] like Figure 4 The figure shows a comprehensive comparison of three representative approximate floating-point multipliers in this embodiment with advanced floating-point multipliers in terms of MRED and power-delay product (PDP) at 32-bit floating-point precision (FP32). MRED was obtained by testing 1 million randomly generated datasets using simulation software and comparing the results with those of the precise multiplier. The power consumption and delay in the PDP metrics were obtained using Synopsys' EDA logic synthesis tool, DesignCompiler (DC), under 28nm CMOS process, 0.9V power supply voltage, and 25°C conditions with the "ultra compile" optimization option. All three multiplication structures in this invention employ a truncation design retaining 6 bits. The results show that the LTAM1, LTAM2, and LTAM-LUT structures collectively form a Pareto optimal front in the figure, indicating that this invention maintains high computational accuracy while significantly reducing power consumption and hardware complexity, fully demonstrating its high energy efficiency design advantages.

[0045] like Figure 5As shown, this embodiment further demonstrates its application effects in image processing and neural network inference tasks. The image processing part includes two types of algorithms: smoothing filtering and sharpening filtering. Three representative HDR images were selected for testing. The neural network part uses a Multilayer Perceptron (MLP) model for handwritten digit recognition (MNIST dataset) and a Convolutional Neural Network (CNN) model for image classification (CIFAR-10 dataset). Image processing performance is evaluated using Peak Signal-to-Noise Ratio (PSNR), and neural network performance is expressed as classification accuracy. Both are compared with the results of the exact multiplier implementation at FP32 and FP16 accuracies. Experimental results show that in the filtering task, the overall performance of the three multipliers is LTAM-LUT better than LTAM2, and LTAM2 better than LTAM1, consistent with the MRED metric results. Although the PSNR is slightly lower than that of the exact multiplier by about 30 dB, it still remains around 60 dB overall. When the PSNR is greater than 40 dB, the human eye can hardly distinguish the difference, verifying the practicality and high energy efficiency of this invention in image processing scenarios. In neural network tasks, the three multiplication structures of this invention maintain the same classification accuracy (97.9%) as the exact multiplier in the handwritten digit recognition task (MNIST). In the more complex CIFAR-10 classification task, the accuracy of the three multipliers decreases by about 0.3%, 0.4%, and 1.1% respectively compared to the exact multiplier. This level of accuracy loss is completely acceptable in neural network inference applications, demonstrating the feasibility and robustness of this invention in artificial intelligence computing.

[0046] In summary, this invention provides a high-efficiency logarithmic floating-point multiplier based on truncation error compensation. Through mantissa truncation and unbiased correction, logarithmic domain addition and compensation, antilogarithmic transformation, and carry signal transmission, it achieves high-precision recovery of the multiplication result. Combined with a global or block-based adaptive compensation strategy, this invention effectively reduces hardware complexity, power consumption, and latency while maintaining computational accuracy. Experiments show that this structure performs excellently in floating-point arithmetic accuracy, energy efficiency, and image processing and neural network inference tasks, fully demonstrating its technical advantages of high energy efficiency, high precision, and strong application adaptability.

[0047] The above examples are only for illustrating the technical concept and features of the present invention. Their purpose is to more clearly explain the purpose, technical solution and advantages of the present invention, and they are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high energy-efficient logarithmic floating-point multiplier based on truncated error compensation, characterized by, It comprises a sign bit XOR module, an exponent bit addition module and a mantissa bit truncated addition and compensation module; The sign bit XOR module is configured to perform XOR operation on the sign bits of the two input operands to obtain a result sign; The exponent bit addition module is configured to perform addition on the exponents of the two operands in the shift code representation, and to realize exponent summation through one-time bias correction, thereby reducing the calculation delay; The mantissa bit truncated addition and compensation module is configured to perform bit width truncation on the input mantissa m to reduce hardware overhead, and to realize the conversion from multiplication to addition through logarithmic transformation on the truncated mantissa, wherein a straight line m + k containing a compensation parameter k is used to linearly fit the logarithmic function log2 (m + 1) in the logarithmic transformation process, so as to approximate the hyperbolic paraboloid corresponding to the mantissa product by using a piecewise linear plane in a three-dimensional space, and to introduce fixed or block compensation logic in the addition stage and the inverse logarithmic transformation stage to compensate and correct the system error caused by logarithmic linearization based on the parameter k, thereby realizing the high energy efficiency recovery of the mantissa operation result.

2. The high energy-efficient logarithm floating-point multiplier based on truncated error compensation according to claim 1, characterized in that, The special case processing module is further configured to detect whether the input operands are infinite or non-numerical values, and to set corresponding flag bits when the special values are detected, so as to indicate that the operation result is invalid.

3. The high energy-efficient logarithm floating-point multiplier based on truncated error compensation according to claim 1, characterized in that, The mantissa bit truncated addition and compensation module performs unbiased truncation operation on the input mantissa, reduces the bit width from q bits to q-t bits, and forces 1 on the least significant bit after truncation to offset the systematic bias.

4. The high energy-efficient logarithm floating-point multiplier based on truncated error compensation according to claim 3, characterized in that, The fixed compensation logic in the mantissa bit truncated addition and compensation module comprises: using a discrete sampling and numerical optimization algorithm to optimize the parameter k, and minimizing the objective function to realize global minimization of the truncation error, and taking the binary approximation value of the obtained optimal compensation parameter k in hardware implementation to reduce the calculation complexity.

5. The high energy-efficient logarithm floating-point multiplier based on truncated error compensation according to claim 4, characterized in that, The mantissa bit truncated addition and compensation module is configured in two structure modes based on the fixed compensation logic: The LTAM1 structure adopts a fixed carry injection and all-1 bit compensation strategy to realize hardware priority design; The LTAM2 structure introduces a one-stage independent adder in the compensation and inverse transformation stage to improve the calculation accuracy, and includes an overflow detection mechanism.

6. The high energy-efficient logarithm floating point multiplier based on truncated error compensation as claimed in claim 1, wherein, The block compensation logic in the significand bit-truncation adding and compensation module comprises: dividing an input significand space into multiple blocks , and independently solving optimal compensation parameters for each block ; the block division mode comprises uniform division and non-uniform division modes, the compensation parameter k is obtained by minimizing the average absolute error of each block, and a lookup table type region adaptive compensation is realized according to the high bit index of the input significand.

7. The high energy-efficient logarithm floating-point multiplier based on truncated error compensation according to claim 6, characterized in that, The mantissa bit truncated addition and compensation module is configured in the following structure modes based on the block compensation logic: The LTAM-LUT structure adopts a region adaptive lookup table compensation method, and selects a corresponding block compensation value according to the high bit index of the input mantissa.

8. The high energy-efficient logarithm floating point multiplier based on truncated error compensation according to claim 1, characterized in that, The mantissa operation result of the mantissa bit truncated addition and compensation module further transmits a carry signal to the exponent part, which is used to adjust the floating point number format; finally, the multiplier outputs the compensated mantissa and the corresponding exponent and sign bit combination to form a floating point number output conforming to the IEEE 754 standard.

9. The high energy-efficient log floating-point multiplier based on truncated error compensation according to any one of claims 1 to 8, characterized in that, The multiplier supports multiple floating point precision formats, including IEEE 754 double precision FP64, single precision FP32, half precision FP16 and custom floating point formats with lower bit width.

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