Single-instruction multi-thread SRAM (Static Random Access Memory) in-memory computing unit control system
By implementing a single-instruction, multi-threaded SRAM in-memory computing unit control system, and utilizing SIMT control flow and independent computing blocks, the system addresses the issues of low flexibility and efficiency of SRAM in-memory computing units, reduces power consumption and storage pressure, and improves computing performance.
Patent Information
- Application Number
- CN202511584606.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-30
AI Technical Summary
Existing SRAM in-memory computing units suffer from poor computational flexibility, low efficiency, high power consumption, and high pressure on the storage structure.
The system employs a single-instruction, multi-threaded SRAM in-memory computing unit control system. Through multiple independently computed control blocks and thread blocks, it utilizes SIMT control flow for instruction scheduling and data exchange, thereby reducing the concentration and burstiness of memory access.
It improves the flexibility and efficiency of computing, reduces power consumption, reduces the pressure on storage structures, and enhances computing performance.
Smart Images
Figure CN121433731A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of in-memory computing of static random access memory, in particular to a single instruction multi-thread SRAM in-memory computing unit control system, a processor and an electronic device. BACKGROUND
[0002] The in-memory computing technology of static random access memory (SRAM) is a new high-performance solution, which can effectively solve the processor performance problem caused by power consumption and memory bandwidth limitation. The in-memory computing technology of SRAM adds additional peripheral computing circuit to the SRAM array, so that the SRAM has computing capability, and thus the computation can be directly performed in the SRAM. Compared with the ALU implemented based on the logic circuit, the computation using the in-memory computing technology of SRAM does not need to move data from the storage to the logic computing unit, thereby reducing the use of energy consumption and data transmission bandwidth. At the same time, due to the unique computing mode of the in-memory computing of SRAM, it can support high parallelism computation.
[0003] The traditional computing structure based on the in-memory computing of SRAM uses single instruction multiple data (SIMD) execution flow control. In this architecture, all SRAM in-memory computing devices are controlled by a same control unit to issue instructions. The word lines of the SRAM in-memory computing devices are divided into multiple synchronous computing columns according to the computing direction, and a unified state machine is used to synchronously control all computing columns to perform computation.
[0004] Although the SIMD controller is simple to implement, it uses one instruction to control the entire SRAM in-memory computing architecture. All computing columns of all computing units need to execute the instruction in a completely synchronous manner, and only by selectively writing back data can different operations be performed on different computing columns. This seriously limits the computing flexibility of the SRAM in-memory computing unit, resulting in a large amount of idling in the computing unit, reducing the computing efficiency and increasing the power consumption. At the same time, due to the high parallelism, a large number of memory access requests are concentratedly issued when performing memory access, which significantly increases the pressure on the memory structure. SUMMARY
[0005] Therefore, the technical problem to be solved by the present application is to overcome the problems of poor computing flexibility, low efficiency, high power consumption and high memory structure pressure of the prior art static random access memory.
[0006] To solve the above technical problems, the present application provides a single instruction multi-thread SRAM in-memory computing unit control system, comprising: a plurality of single instruction multi-thread in-memory computing control blocks for independent computation, each control block being configured to schedule a static random access memory in-memory thread block thereunder to execute an issued instruction, The thread block comprises a plurality of static random access memory in-memory computing units, and a static random access memory array in each static random access memory in-memory computing unit is divided into registers of independent threads. The system-level memory access unit is configured to receive the memory access requests of the control blocks, interact with an external storage, and send memory access responses to the control blocks.
[0007] Preferably, the single instruction multiple thread in-memory computing control block comprises: The single instruction multiple thread in-memory computing control unit is configured to schedule the static random access memory in-memory computing thread blocks under its jurisdiction to execute the issued instructions. The plurality of static random access memory in-memory computing thread blocks are configured to execute the in-memory computing instructions sent by the single instruction multiple thread in-memory computing control unit and send the computing result information to the single instruction multiple thread in-memory computing control unit after the computation is completed. The control block memory access unit is configured to accept and concentrate the memory access requests sent by the thread blocks, interact with the system memory access unit, and send the received memory access responses to the thread blocks.
[0008] Preferably, the plurality of static random access memory in-memory computing thread blocks are synchronized through a synchronization type special instruction and exchange information through the shared memory in the control block memory access unit through a communication type special instruction.
[0009] Preferably, the single instruction multiple thread in-memory computing control unit comprises: The thread block scheduler is configured to read the state register information of all the static random access memory in-memory computing thread blocks in each cycle, select a thread block to emit the next instruction according to the execution state, and send the program counter information of the selected thread block to the program memory. The program memory is configured to read the instructions and send them to the decoder. The decoder is configured to decode the instructions and send them to the corresponding thread blocks to perform in-memory computing.
[0010] Preferably, the static random access memory in-memory computing thread block comprises: The instruction queue is configured to receive and store the instructions sent by the single instruction multiple thread in-memory computing control unit and emit new instructions to the static random access memory in-memory computing array controller after the static random access memory in-memory computing unit is idle. The plurality of static random access memory in-memory computing units are controlled by a single static random access memory in-memory computing array controller. A plurality of static random access memory in-memory computing array controllers are used to enter the corresponding state after obtaining the next instruction to be executed from the instruction queue, and control the corresponding static random access memory in-memory computing unit to complete the calculation. A thread block memory access unit is used to obtain the memory access request from each static random access memory in-memory computing unit, send the read and write to the control block memory access unit for storage after processing, and return the read data provided by the control block memory access unit to the corresponding static random access memory in-memory computing unit. A state register is used to maintain the execution state of the thread block and provide it to the single instruction multi-thread in-memory computing control unit.
[0011] Preferably, the state register comprises: A program counter is used to record the current execution position. A thread mask is used to control which threads participate in the calculation.
[0012] Preferably, the static random access memory in-memory computing unit comprises: A static random access memory array capable of multi-word line activation and bit line calculation is divided into a plurality of independent thread registers. A row decoder capable of multi-row activation; A set of signal amplifiers and peripheral computing circuits capable of reading data from the bit line of the static random access memory array and processing.
[0013] Preferably, the specific division of the static random access memory array is: In the word line direction, a plurality of bit lines form a group, each group of bit lines is determined as a logical thread, and in the bit line direction, a plurality of word lines form a group, each group of word lines is determined as a physical register of the logical thread.
[0014] The application also provides a processor comprising the single instruction multi-thread SRAM in-memory computing unit control system as described above.
[0015] The application also provides an electronic device comprising the processor as described above.
[0016] The above technical solutions of the application have the following advantages compared with the prior art: The single instruction multiple thread SRAM in-memory computing unit control system has higher flexibility, can effectively reduce the idle rotation of the computing column when a relatively complex program logic is encountered, and thus has higher performance and reduces the power consumption of the computing. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to make the content of the present application more easily understood, the present application is further described in detail below according to specific embodiments of the present application and in combination with the drawings, in which: Figure 1 is a structural schematic diagram of an SRAM in-memory computing control block; Figure 2 is a structural schematic diagram of an SRAM in-memory computing thread block; Figure 3 is a structural schematic diagram of an SRAM in-memory computing unit. DETAILED DESCRIPTION
[0018] The core of the present application is to provide a single instruction multiple thread SRAM in-memory computing unit control system, a processor and an electronic device, which has higher flexibility, can effectively reduce the idle rotation of the computing column when a relatively complex program logic is encountered, and thus has higher performance and reduces the power consumption of the computing, and simultaneously, the use of the SIMT control flow for control divides the entire computing architecture into a plurality of relatively independent computing control blocks, significantly reduces the centralization and burst of the storage access, reduces the pressure of the storage structure, and improves the computing efficiency.
[0019] In order to make the person in the technical field better understand the present application scheme, the present application is further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person of ordinary skill in the art without making creative labor belong to the protection scope of the present application.
[0020] The present application provides a single instruction multiple thread SRAM in-memory computing unit control system; specifically comprising: a plurality of independent computing single instruction multiple thread in-memory computing control blocks, each of the control blocks being used to schedule the static random access memory in-memory computing thread block thereunder to execute the issued instruction, The thread block contains a plurality of static random access memory in-memory computing units, and a static random access memory array in each static random access memory in-memory computing unit is divided into registers of a plurality of independent threads. It should be noted that each control block is a powerful computing unit, and a plurality of control blocks can process large-scale and high-parallel computing tasks in parallel to provide extremely high system-level computing power.
[0021] The system-level memory access unit is configured to receive the memory access requests of the control blocks, interact with an external storage, and send the memory access replies to the control blocks.
[0022] It should be noted that the control block is responsible for receiving and sending the memory access requests and replies of all control blocks, and is a key interface for connecting the storage and computing architecture on the chip to the external main memory (such as a DRAM) or other storage levels. It manages the system-level storage access traffic.
[0023] As Figure 1 Based on the above embodiments, in some embodiments, the single instruction multi-thread in-memory computing control block comprises: The single instruction multi-thread in-memory computing control unit is configured to schedule the static random access memory in-memory computing thread block thereunder to execute the issued instruction; The plurality of static random access memory in-memory computing thread blocks are configured to execute the in-memory computing instruction sent by the single instruction multi-thread in-memory computing control unit, and send the computing result information to the single instruction multi-thread in-memory computing control unit after the computation is completed; It should be noted that it receives the instruction transmitted by the control block and performs the computation. The plurality of thread blocks in the control block can be independently and asynchronously executed, or can be synchronized through a special instruction, and communicate through the shared memory in the control block memory access unit.
[0024] The control block memory access unit is configured to accept and concentrate the memory access requests sent by each thread block, interact with the system memory access unit, and send the received memory access replies to each thread block.
[0025] It should be noted that it serves as a unified memory access interface of the control block. The memory access requests of all thread blocks thereunder are concentrated and sent to the system-level storage structure; and the external returned data is distributed to the corresponding thread block memory access unit. This effectively reduces the “burstiness” of memory access.
[0026] In some embodiments, the plurality of static random access memory in-memory computing thread blocks are synchronized through a synchronization type special instruction, and exchange information through the shared memory in the control block memory access unit through a communication type special instruction.
[0027] Note that when the calculation result of a certain thread block is the data needed by another thread block, or multiple thread blocks need to update a shared data together, they must be ensured to be "in step" at a certain point in time, otherwise data errors will occur. The role of the synchronization special instruction: forcibly control all (or a specified group of) thread blocks in the control block to pause at the execution of the instruction, waiting for all other included thread blocks to also execute to this position. When all specified thread blocks arrive, they are released at the same time and continue to execute the subsequent instructions. This establishes a clear execution barrier.
[0028] Note that when the thread block executes the task, it often needs to exchange data or share intermediate results. The role of the communication special instruction: this type of instruction allows thread blocks to read and write shared memory in the control block memory access unit. A thread block can write data to a specific location in the shared memory through a special instruction, and another thread block can read data from that location through a special instruction. Combined with the synchronization special instruction, it can ensure that the "write" operation is completed before the "read" operation, thereby achieving safe and reliable data sharing.
[0029] Based on the above embodiments, in some embodiments, the single instruction multiple thread in-memory computing control unit comprises: A thread block scheduler for reading the state register information of all static random access memory in-memory computing thread blocks in each cycle, selecting a thread block to emit the next instruction according to the execution state, and sending the program counter information of the selected thread block to the program memory; Note that it reads the state register of all thread blocks under its jurisdiction in each cycle, and according to its execution state (such as whether it is stalled, waiting, etc.), selects a suitable thread block to emit the next instruction. This is the core of SIMT flexible scheduling.
[0030] A program memory for reading instructions and sending them to the decoder; Note that it stores all the instruction codes that the thread blocks need to execute. It receives the program counter address sent by the scheduler and outputs the corresponding instructions.
[0031] A decoder for decoding instructions and sending them to the corresponding thread blocks for in-memory computing.
[0032] Note that it receives instructions read from the program memory, decodes them, parses the operation code and operand, and generates micro-operations or control signals that can be directly executed by the thread block.
[0033] It should be noted that the SRAM in-memory computing control block includes a plurality of independently executed SRAM in-memory computing thread block, a thread block scheduler, a program memory, a decoder and a control block memory access unit. The thread block scheduler reads the state register information of all thread blocks every cycle and selects a suitable thread block to transmit the next instruction. After selecting the thread block, the scheduler sends the program counter information of the corresponding thread block to the program memory to read the instruction. After completing the instruction reading, the instruction is sent to the decoder for decoding and then to the instruction queue of the corresponding thread block for execution. The control block memory access unit communicates with the memory access units of each thread block through the bus. The control block memory access unit concentrates the memory access requests of the thread blocks and sends them to the external storage structure for storage reading and writing. At the same time, after receiving the memory access information, the control block memory access unit returns the data to the corresponding thread block for processing through the bus. All thread blocks in the control block can be synchronized through special instructions, and information exchange can be performed through the shared memory in the control block memory access unit.
[0034] As Figure 2 , based on the above embodiments, in some embodiments, the static random access memory in-memory computing thread block comprises: an instruction queue for receiving and storing instructions sent by the single instruction multi-thread in-memory computing control unit, and transmitting new instructions to the static random access memory in-memory computing array controller after the static random access memory in-memory computing unit is idle; It should be noted that it receives and buffers the decoded instructions from the upper control block. When the internal SRAM computing array controller is idle, the next instruction is transmitted to it, which plays a role in smoothing the instruction flow and improving efficiency.
[0035] a plurality of static random access memory in-memory computing units, each of which is controlled by a separate static random access memory in-memory computing array controller; It should be noted that it belongs to the plurality of computing units of the thread block, stores the data of each thread under its jurisdiction, and executes the computing tasks issued by the controller.
[0036] a plurality of static random access memory in-memory computing array controllers for entering the corresponding state to control the corresponding static random access memory in-memory computing unit to complete the computation after obtaining the next instruction to be executed from the instruction queue; It should be noted that it is a finite state machine. It takes instructions from the instruction queue, analyzes them to generate specific control signals, and controls the row decoder and peripheral computing circuit of the SRAM in-memory computing unit to perform the computation, storage or memory operation required by the instruction.
[0037] a thread block memory access unit, configured to obtain a memory access request from each SRAM in-memory computing unit, send the memory access request to the control block memory access unit after processing, and perform read and write of storage, and return read data provided by the control block memory access unit to the corresponding SRAM in-memory computing unit; It is to be noted that the thread block memory access unit is an access agent of the thread block. The thread block memory access unit collects memory access requests sent by all computing units in the thread block, and sends the memory access requests to the control block memory access unit. Meanwhile, the thread block memory access unit receives memory access reply data from the control block memory access unit, and returns the memory access reply data to the corresponding computing unit.
[0038] a state register, configured to maintain an execution state of the thread block, and provide the execution state to the single instruction multiple thread in-memory computing control unit.
[0039] In some embodiments, the state register includes: a program counter, configured to record a current execution position; a thread mask, configured to control which threads participate in computation.
[0040] It is to be noted that the state register stores dynamic execution states of the thread block, including but not limited to the program counter and the thread mask. The thread mask is used to control which threads in the thread block participate in execution of a current instruction. The state information is visible to a higher-level scheduler.
[0041] It is to be noted that each SRAM in-memory computing thread block includes an instruction queue, a set of state registers, a program counter, a memory access unit, and a plurality of SRAM in-memory computing units provided with a computing array controller. All threads in a thread block execute the same instruction at the same time, and the thread mask in the state register is used to control whether each thread in the thread block participates in computation. Each SRAM in-memory computing unit is controlled by a separate SRAM computing array controller. The controller is a finite state machine, which enters a corresponding state after obtaining a next instruction to be executed from the instruction queue, and controls a row decoder and a peripheral computing circuit of the SRAM in-memory computing unit to complete a corresponding function of the instruction. The memory access unit obtains a memory access request from each in-memory computing unit, sends the memory access request to an outer structure after processing, and performs read and write of storage; and is responsible for returning read data provided by the outer structure to the corresponding SRAM in-memory computing unit. The instruction queue of the thread block is used to obtain an instruction to be executed from the outer structure, and deliver the instruction to the SRAM computing unit in the thread block. The state register is responsible for maintaining an execution state of the thread block (such as the program counter and the thread mask), and providing the execution state to the outer structure.
[0042] As Figure 3 , based on the above embodiments, in some embodiments, the SRAM in-memory computing unit includes: A static random access memory array capable of multi-wordline activation and bitline computation, which is divided into several independent thread registers; Note that this is the core storage and computing medium. Unlike traditional SRAM, which only serves as a memory, it can directly implement analog computation (such as "wire and" logic) on the bit line by simultaneously activating multiple word lines, thus completing the computation operation inside the storage unit.
[0043] A row decoder capable of multi-row activation; Note that it receives instructions from the controller and simultaneously selects and activates multiple word lines, which is the key circuit for realizing the parallelism of in-memory computation.
[0044] A set of signal amplifiers and peripheral computing circuits capable of reading data from the bit lines of a static random access memory array and processing them.
[0045] Note that it is located at the end of the bit line and is used to read the weak analog computation results ("wire and" results) from the bit line, amplify the signal, perform analog-to-digital conversion, and further process them to complete the macro digital computation function (such as logic operation, arithmetic operation).
[0046] In some embodiments, the specific division of the static random access memory array is as follows: Along the word line direction, multiple bit lines form a group, and each group of bit lines is determined as a logical thread. Along the bit line direction, multiple word lines form a group, and each group of word lines is determined as a physical register of the logical thread. From a logical view, the physical array is divided into multiple threads (grouped along the bit line direction) and multiple physical registers (grouped along the word line direction within each thread). This allows a physical computing unit to provide data storage and computing services for multiple logical threads.
[0047] Note that in the SRAM in-memory computation unit, we complete the wire and computation on the bit line by simultaneously activating multiple word lines, and further process the wire and results in the peripheral circuit below to complete the macro computation function. Therefore, we divide the SRAM array into multiple threads according to the bit line direction. Each thread is allocated the same number of bit lines, but the specific number can be changed according to the specifications of the SRAM array and the computation needs. Each thread should have multiple register units for computation to store data. We divide the bit line resources allocated to each thread into several registers according to the word line direction.
[0048] In a specific embodiment, we allocate two bit lines to each thread and divide every four word lines into a register, thus transforming an SRAM array into an SRAM in-memory computation unit with 8-bit registers.
[0049] The embodiment of the present application further provides a processor comprising the single instruction multiple thread SRAM in-memory computing unit control system.
[0050] The embodiment of the present application further provides an electronic device comprising the processor.
[0051] Obviously, the above embodiment is only an example for clearly illustrating the present application, and is not intended to limit the implementation. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the implementations are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A single-instruction, multi-threaded SRAM in-memory computing unit control system, characterized in that, The system comprises: a plurality of single instruction multiple thread in-memory computing control blocks, each of which is used to schedule a static random access memory in-memory computing thread block under its jurisdiction to execute an issued instruction, wherein the thread block contains a plurality of static random access memory in-memory computing units, and a static random access memory array inside each static random access memory in-memory computing unit is divided into a plurality of registers for independent threads; a system-level memory access unit used to receive memory access requests of each control block, interact with an external storage, and send a memory access reply to the control block.
2. The SIMT SRAM in-memory computing unit control system of claim 1, wherein, The single instruction multiple thread in-memory computing control block comprises: a single instruction multiple thread in-memory computing control unit used to schedule a static random access memory in-memory computing thread block under its jurisdiction to execute an issued instruction; a plurality of static random access memory in-memory computing thread blocks used to execute in-memory computing instructions sent by the single instruction multiple thread in-memory computing control unit and send computing result information to the single instruction multiple thread in-memory computing control unit after the computation is completed; a control block memory access unit used to accept and concentrate memory access requests sent by each thread block, interact with a system memory access unit, and send a received memory access reply to each thread block.
3. The SIMT SRAM in-memory computing unit control system of claim 1, wherein, The plurality of static random access memory in-memory computing thread blocks are synchronized through a synchronization type special instruction and exchange information through a shared memory in the control block memory access unit through a communication type special instruction.
4. The SIMT SRAM on-chip computing unit control system of claim 2, wherein, The single instruction multiple thread in-memory computing control unit comprises: a thread block scheduler used to read state register information of all static random access memory in-memory computing thread blocks in each cycle, select a thread block to emit a next instruction according to an execution state, and send program counter information of the selected thread block to a program memory; the program memory used to read an instruction and send it to a decoder; the decoder used to decode the instruction and send it to a corresponding thread block to execute in-memory computing.
5. The SIMT SRAM in-memory computing unit control system of claim 2, wherein, The static random access memory in-memory computing thread block comprises: an instruction queue used to receive and store an instruction sent by the single instruction multiple thread in-memory computing control unit and emit a new instruction to a static random access memory in-memory array controller after a static random access memory in-memory computing unit is idle; a plurality of static random access memory in-memory computing units, each of which is controlled by a single static random access memory in-memory array controller; a plurality of static random access memory in-memory array controllers used to enter a corresponding state after obtaining a next instruction to be executed from the instruction queue, control a corresponding static random access memory in-memory computing unit to complete computation; a thread block memory access unit used to obtain a memory access request from each static random access memory in-memory computing unit, send a read-write memory access request to a control block memory access unit for storage after processing, and return read data provided by the control block memory access unit to the corresponding static random access memory in-memory computing unit; a state register used to maintain an execution state of the thread block and provide it to the single instruction multiple thread in-memory computing control unit.
6. The SIMT SRAM on-chip computing unit control system of claim 5, wherein, The state register comprises: a program counter for recording the current execution position; a thread mask for controlling which threads participate in the calculation.
7. The SIMT SRAM on-chip computing unit control system of claim 5, wherein, The static random access memory in-memory computing unit comprises: a static random access memory array capable of multi-word line activation and bit line calculation, which is divided into a plurality of independent thread registers; a row decoder capable of multi-row activation; a set of signal amplifiers and peripheral computing circuits capable of reading data from the bit lines of the static random access memory array and processing the data.
8. The SIMT SRAM on-chip computing unit control system of claim 7, wherein, The specific division mode of the static random access memory array is: In the direction of the word line, a plurality of bit lines form a group, and each group of bit lines is determined as a logical thread. In the direction of the bit line, a plurality of word lines form a group, and each group of word lines is determined as a physical register of the logical thread.
9. A processor, comprising: The single instruction multiple thread SRAM in-memory computing unit control system comprises the single instruction multiple thread SRAM in-memory computing unit according to any one of claims 1-8.
10. An electronic device, comprising: The processor comprises the processor according to claim 9.