Reconfigurable two-dimensional floating gate memory

Abstract

The invention discloses a reconfigurable two-dimensional floating gate memory which is of a layered structure, and a reconfigurable memory mechanism mainly depends on the photosensitive characteristic of a floating gate layer material, that is, illumination can improve the off-state current of the floating gate layer material. In a dark-state small gate voltage range, the floating gate layer is in a closed state, and at the moment, a storage mechanism is a capacitance coupling effect and shows short-term memory; under the action of illumination, the floating gate layer is opened, and a storage mechanism is switched to a Fowler-Nordheim tunneling effect, which is represented as long-term memory. The invention aims to solve the defects of single function and limited regulation and control means of the existing memory, realizes short-term and long-term memory dual-mode in the device through the '2T1C' layered structure design and the photosensitive characteristic of the two-dimensional material, can realize flexible switching of the two modes through external voltage or illumination, has the advantages of high-speed response of a DRAM and long-term maintenance of a Flash, and has the advantages of high-speed response of the DRAM and long-term maintenance of the Flash. And an efficient and flexible storage solution is provided for the fields of intelligent storage, brain-like computing and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a reconfigurable two-dimensional floating gate memory. BACKGROUND

[0002] Memory technology can be roughly divided into two categories: volatile memory and non-volatile memory. Volatile memory (such as dynamic random access memory (DRAM)) relies on the charging and discharging of capacitors to store information, has the advantages of fast reading and writing and low power consumption, but the information can only be maintained when the power is on, and once the power is off, the stored data will be lost, so it is called volatile memory. DRAM is widely used in computer memory and cache, and is suitable for occasions with high requirements on reading and writing speed but low requirements on data retention time. However, due to the need for periodic refresh and short retention time, DRAM cannot be used as a long-term storage solution. Non-volatile memory (such as flash memory) stores data through charge trapping mechanism or tunneling effect, and the stored data can still be maintained even after the power is turned off, so it is called non-volatile memory. Non-volatile memory has a longer data retention time and is widely used in solid state disks, USB storage devices, smart phones and other scenarios that require long-term data storage. However, the erase and write speed of non-volatile memory is slow, and the number of erase and write times is limited, which performs poorly in applications with frequent writing and deletion.

[0003] In recent years, two-dimensional materials (such as graphene, transition metal dichalcogenides, etc.) have become an important direction of research on new memory devices due to their atomic thickness, excellent electrical properties and tunability. Two-dimensional materials not only have high electron mobility and flexible electrical control, but also can effectively reduce the size of the device due to their extremely thin characteristics, meeting the demand for high-density storage. In addition, two-dimensional materials also have excellent photoelectric response capability, which can control the conductance characteristics through light, providing an innovative solution for new adjustable memories.

[0004] Short-term memory characteristics are crucial for brain-like computing and neuromorphic computing, which can help intelligent robots, autonomous driving systems and other systems quickly access transient data, make real-time decisions and perform efficient computing. Long-term memory is used for long-term storage of big data and plays a role in data centers, medical, financial and other fields, ensuring data stability and power failure without data loss, and meeting the data storage needs of the Internet of Things. However, existing two-dimensional material-based memory devices still have the problem of single function. For example, two-dimensional material-based capacitive memory can only provide short-term memory characteristics, while two-dimensional material-based floating gate memory relies on tunneling effect to provide long-term memory. The limitation of these traditional memories is that they cannot simultaneously realize the functions of short-term memory and long-term memory in the same device, so they cannot meet the demand of high-speed response and long-time stable storage in some application scenarios. Especially in the field of brain-like computing and neuromorphic computing, the memory needs to be able to simulate the memory characteristics of the human brain and have the ability of short-term memory and long-term memory, but the existing technology cannot meet this demand. SUMMARY

[0005] The main purpose of the present application is to provide a reconfigurable two-dimensional floating gate memory, which is a layered structure and sequentially includes a substrate (1), an oxide dielectric layer (2), a two-dimensional floating gate layer (8), a two-dimensional insulating gate tunneling layer (7) and a two-dimensional semiconductor channel layer (6) from bottom to top.

[0006] The memory further includes a source electrode (4), a drain electrode (5) and a floating gate electrode (3), the source electrode (4) and the drain electrode (5) are arranged on the surface and both sides of the two-dimensional semiconductor channel layer (6), and the floating gate electrode (3) is arranged on the surface of the two-dimensional floating gate layer (8).

[0007] The material of the two-dimensional floating gate layer (8) is tungsten selenide, the material of the two-dimensional semiconductor channel layer (6) is molybdenum telluride, and the material of the two-dimensional insulating gate tunneling layer (7) is hexagonal boron nitride.

[0008] The equivalent circuit components of the memory are: the two-dimensional floating gate layer (8) as a first transistor, the two-dimensional semiconductor channel layer (6) as a second transistor, the coupling region of the floating gate electrode (3) and the substrate (1) as a first capacitor, the coupling region formed between the two-dimensional semiconductor channel layer (6) and the two-dimensional floating gate layer (8) through the two-dimensional insulating gate tunneling layer (7) as a second capacitor, and the coupling region of the two-dimensional floating gate layer (8) directly below the two-dimensional semiconductor channel layer (6) and the substrate (1) as a third capacitor.

[0009] In an embodiment, the substrate (1) serves as the control gate of the memory, the source electrode (4) serves as the source electrode of the memory, and the drain electrode (5) serves as the drain electrode of the memory.

[0010] If positive and negative scanning voltages are applied in the dark state and in the small control gate voltage range, the drain-source current of the transfer characteristic curve forms a hysteresis direction of "left order right reverse"; corresponding to the application of positive / negative pulse on the control gate, the drain-source current shows short-term memory effect;

[0011] If positive and negative scanning voltages are applied in the dark state and in the large control gate voltage range, or in the light state and in the small control gate voltage range, the drain-source current of the transfer characteristic curve forms a hysteresis direction of "left reverse right order"; corresponding to the application of positive / negative pulse on the control gate, the drain-source current shows long-term memory effect.

[0012] In an embodiment, the first transistor functions as a switch to control the size of the drain-source current of the second transistor; the second transistor provides a path for the channel output current of the memory; the first capacitor can accommodate the charge generated by capacitive coupling before the first transistor is turned on; the second capacitor is used to isolate the charge exchange between the two-dimensional semiconductor channel layer (6) and the two-dimensional floating gate layer (8), to avoid excessive leakage current; the third capacitor is used to assist in adjusting the potential distribution of the two-dimensional floating gate layer (8) and optimize the memory characteristics.

[0013] In an embodiment, the mechanism for realizing the reconfigurable memory function of the memory is:

[0014] The short-term memory mechanism is realized by the coupling capacitor of the two-dimensional floating gate layer (8) and the floating gate electrode (3) and the substrate (1). In the dark state, when a positive control gate voltage is applied, the first transistor is in the off state, the first capacitor starts to charge negative charges, the potential of the floating gate region under the channel cannot reach the tunneling potential difference of the tunneling layer, and the channel layer cannot inject charges into the floating gate layer. When the positive control gate voltage is removed, the first capacitor starts to discharge, and this process has a time constant, which shows short-term memory.

[0015] The long-term memory mechanism is realized by the tunneling layer, which is divided into the following two cases:

[0016] In the dark state, when a larger positive control gate voltage is applied, the first transistor is turned on, the original charge stored in the first capacitor leaks quickly, the entire two-dimensional floating gate layer (8) is a whole, and the Fowler-Nordheim tunneling condition is reached between the two ends of the tunneling layer. The negative charges in the channel are injected into the floating gate layer and are retained for a long time, showing long-term memory.

[0017] In the light state, since the two-dimensional floating gate layer (8) has photosensitive characteristics, when the same positive control gate voltage as in the dark state is applied, the first transistor is turned on, the entire two-dimensional floating gate layer (8) is a whole, and when the voltage reaches the Fowler-Nordheim tunneling threshold of the tunneling layer, the negative charges in the channel are injected into the floating gate layer and are retained for a long time, showing long-term memory.

[0018] In an embodiment, the memory is in a short-term memory state when the substrate control gate is in a dark state and a small pulse voltage is applied to the control gate;

[0019] The memory is in a long-term memory state when a large voltage is applied to the control gate or a photoelectric cooperative pulse is applied at a low voltage.

[0020] In an embodiment, the memory can be switched between short-term and long-term memory states under the action of an external voltage or light, and the switching between the two memory states depends on the switching state of the two-dimensional floating gate layer (8).

[0021] In an embodiment, the short-term memory retention time is less than 10 2 s, and the long-term memory retention time is greater than 10 3 s; the short-term memory retention time can be adjusted by different light intensities.

[0022] In an embodiment, the two-dimensional semiconductor channel layer material molybdenum telluride can be replaced by other two-dimensional semiconductor materials such as molybdenum sulfide, tungsten selenide, and black phosphorus; the two-dimensional insulating gate tunneling layer material hexagonal boron nitride can be replaced by other dielectric layer materials such as hafnium dioxide and antimony trioxide; and the two-dimensional floating gate layer material tungsten selenide can be replaced by other semiconductor materials having the same or similar photoelectric properties as tungsten selenide.

[0023] In an embodiment, the simulation results of the equivalent circuit model of the memory in SPICE simulation are consistent with the experimental results, so that the memory can be extended to other memory devices with the same electrical behavior, and the SPICE equivalent circuit model consists of the following parts:

[0024] The two-dimensional floating gate layer (8) is equivalent to two back-to-back series PMOS and NMOS and a photoresistor in parallel, the two-dimensional insulating gate tunneling layer (7) is equivalent to two back-to-back series voltage stabilizing diodes and a second capacitor in parallel, and the two-dimensional semiconductor channel layer (6) is equivalent to two back-to-back series PMOS and NMOS and a fixed resistor in parallel.

[0025] In an embodiment, the capacitance values of the first, second, and third capacitors have the following relationship: the first capacitor is greater than the second capacitor, which is greater than the third capacitor.

[0026] In an embodiment, the memory is used for brain-like computing, intelligent edge computing, medical health monitoring, financial data storage, or data storage in Internet of Things devices.

[0027] Therefore, the present application has the following beneficial effects:

[0028] The application provides a reconfigurable two-dimensional floating gate memory, which is a layered structure and sequentially comprises a substrate (1), an oxide dielectric layer (2), a two-dimensional floating gate layer (8), a two-dimensional insulating gate tunnel layer (7) and a two-dimensional semiconductor channel layer (6) from bottom to top; the memory further comprises a source electrode (4), a drain electrode (5) and a floating gate electrode (3), the source electrode (4) and the drain electrode (5) are arranged on the surface and both sides of the two-dimensional semiconductor channel layer (6), and the floating gate electrode (3) is arranged on the surface of the two-dimensional floating gate layer (8); the material of the two-dimensional floating gate layer (8) is tungsten selenide, the material of the two-dimensional semiconductor channel layer (6) is molybdenum telluride, and the material of the two-dimensional insulating gate tunnel layer (7) is hexagonal boron nitride; the equivalent circuit components of the memory are as follows: the two-dimensional floating gate layer (8) as a first transistor, the two-dimensional semiconductor channel layer (6) as a second transistor, the coupling area of the floating gate electrode (3) and the substrate (1) as a first capacitor, the coupling area formed between the two-dimensional semiconductor channel layer (6) and the two-dimensional floating gate layer (8) through the two-dimensional insulating gate tunnel layer (7) as a second capacitor, and the coupling area of the two-dimensional floating gate layer (8) directly below the two-dimensional semiconductor channel layer (6) and the substrate (1) as a third capacitor. The application aims to solve the defects of single function and limited regulation means of the existing memory, realizes short-term and long-term memory dual modes in a single device through the design of the "2T1C" layered structure and the photosensitive characteristics of two-dimensional materials, and can realize flexible switching of the two modes through external voltage or light, so that the advantages of high-speed response of DRAM and long-term retention of Flash are combined, and an efficient and flexible storage solution is provided for the field of intelligent storage, brain-like computing and the like. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0030] Figure 1 It is a whole structure schematic diagram of the reconfigurable two-dimensional floating gate memory of the application.

[0031] Figure 2 It is a "2T1C" equivalent circuit schematic diagram of the reconfigurable two-dimensional floating gate memory of the application.

[0032] Figure 3 It is a photoelectric performance schematic diagram of the WSe2 transistor in the application.

[0033] Figure 4 It is a working principle and storage characteristic schematic diagram of the application in a dark state and a low gate voltage.

[0034] Figure 5 The working principle and storage characteristics of the application under illumination are shown in the schematic diagram.

[0035] Figure 6 The transfer characteristics curve and hysteresis direction of the device in the application in long and short term mode are shown in the schematic diagram.

[0036] Figure 7 The circuit model based on SPICE simulation of the application is shown in the schematic diagram. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the application clearer, the technical scheme in the application will be described clearly and completely below in combination with the drawings in the application. Obviously, the described embodiments are part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0038] It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0039] In view of the defects of the prior art, the technical scheme provided by the application is a reconfigurable two-dimensional floating gate memory, which comprises:

[0040] Structural design: from top to bottom, it is two-dimensional semiconductor channel layer molybdenum telluride (MoTe2), two-dimensional insulating gate tunneling layer hexagonal boron nitride (h-BN), two-dimensional floating gate layer tungsten selenide (WSe2), silicon dioxide, and single crystal silicon, wherein the two-dimensional semiconductor channel layer is completely covered by the two-dimensional floating gate layer, which facilitates the floating gate layer to capture channel charges; the memory also comprises a source electrode, a drain electrode and a floating gate electrode; the source electrode and the drain electrode are arranged on the surface and both sides of the two-dimensional semiconductor channel layer, and the floating gate electrode is arranged on the surface of the semiconductor floating gate; the memory is of a "2T1C" structure, wherein the WSe2 constitutes a first transistor, the MoTe2 constitutes a second transistor, and the two form a "2T" structure; the switching state of the WSe2 transistor is used to control the turn-on and turn-off of the MoTe2 transistor. The first capacitor is formed between the floating gate electrode and the silicon substrate, constituting a "1C" structure.

[0041] Working mode: in the dark state and when the control gate voltage is 10 V, the WSe2 is in the off state at this time, and the memory mainly relies on the capacitive coupling effect of the first capacitor to realize short-term memory, and the retention time can be adjusted by 0~270 uW / cm 2 The light intensity is adjusted by 455 nm light, the range is 10~500 ms, and the corresponding transfer characteristic curve presents a "left forward and right reverse" hysteresis direction; when the control gate voltage is 20 V, or under the gate voltage of 10 V, there is 455 nm light (light intensity 116.06 mW / cm2 ), WSe2 is turned on, the potential of the floating gate under the channel is lifted to the Fowler-Nordheim tunneling condition, the tunneling effect occurs, the carriers in the channel tunnel to the floating gate layer, realizing long-term memory, and the retention time is greater than 10 4 s, and the corresponding transfer characteristic curve presents a "left reverse and right forward" hysteresis direction. The capacitive coupling effect refers to the phenomenon that energy or signals between two conductors interact with each other through an electric field due to the existence of a capacitor; and the Fowler-Nordheim tunneling effect is a quantum tunneling phenomenon that electrons penetrate the potential barrier between the metal and the insulating layer under the action of a strong electric field.

[0042] Reconfigurable mechanism: the switching of short-term and long-term memory modes is caused by the competition between the capacitive coupling effect and the tunneling effect caused by the on-state resistance regulation of the two-dimensional floating gate layer WSe2; external light and gate voltage can be used as a double regulation means to realize flexible switching of the memory mode.

[0043] Verification means: the dual-mode characteristics of short-term / long-term memory are verified by a series of electrical performance tests on the memory; further, a SPICE simulation model of the "2T1C" equivalent circuit is built, and the simulation results are consistent with the experimental data, verifying the feasibility and universality of the present application.

[0044] The embodiment of the present application provides a reconfigurable two-dimensional floating gate memory, the overall structure of which is shown in Figure 1 , wherein Figure 1 -a is a three-dimensional schematic diagram of the memory, Figure 1 -b is a two-dimensional cross-sectional schematic diagram of the memory. The memory is sequentially from bottom to top: a substrate Si (1), an oxide dielectric layer SiO2 (2), a two-dimensional floating gate layer WSe2 (8), a two-dimensional insulating gate tunneling layer h-BN (7) and a two-dimensional semiconductor channel layer MoTe2 (6); in addition, it also includes a source electrode S (4), a drain electrode D (5) and a floating gate electrode FGE (3), wherein the source electrode and the drain electrode are arranged on the surface and both sides of the two-dimensional semiconductor channel layer, and the floating gate electrode is arranged on the surface of the two-dimensional floating gate layer.

[0045] The equivalent structure and circuit schematic diagram of the reconfigurable two-dimensional floating gate memory are shown in Figure 2 . Among them, as shown in Figure 2 -a, WSe2 constitutes a first transistor, MoTe2 constitutes a second transistor, and the two form a "2T" structure; the on-off state of the WSe2 transistor is used to control the conduction and turn-off of the MoTe2 transistor. The floating gate electrode and the Si substrate form a capacitor C1, constituting a "1C" structure. As shown in Figure 2As shown in -a, the MoTe2 transistor can be equivalent to a second capacitor, the WSe2 transistor can be equivalent to a variable resistance and a third capacitor, and the overall equivalent circuit of the floating gate memory is a first capacitor and a variable resistance in series, both of which are in parallel with a third capacitor, and the three are in series with a second capacitor.

[0046] The above-mentioned two-dimensional materials related to the two-dimensional floating gate layer WSe2 (8), the two-dimensional insulating gate tunneling layer h-BN (7), and the two-dimensional semiconductor channel layer MoTe2 (6) can be obtained by mechanical exfoliation, chemical vapor deposition, molecular beam epitaxy, etc., and stacked on a SiO2 / Si substrate by a dry transfer process. In this embodiment, mechanical exfoliation and dry transfer are preferred. Subsequently, metal electrodes (such as Cr / Au) are deposited by thermal evaporation to construct the source, drain and floating gate electrodes, and a complete "2T1C" device is formed.

[0047] Further, in this embodiment, as shown in Figure 3 WSe2 plays an important role in the reconfigurable floating gate memory. In order to better study the short-term memory behavior of the floating gate memory, the photoelectric properties of the WSe2 transistor are first studied. Figure 3 -a is a device structure and equivalent circuit schematic diagram of the WSe2 transistor, in which the WSe2 part is equivalent to a variable photosensitive resistance, and there is a coupling capacitor between the source and drain and the substrate Si. As shown in Figure 3 -b, when the device is under different light intensities (0~116.06 mW / cm 2 ) at 455 nm, and a scanning voltage of -30 V→30 V→-30 V is applied to the Si gate, the transfer characteristic curve is tested, and there is an obvious adjustment range of the on-state and off-state current of the source-drain channel current, and the light can increase the off-state current of the transistor channel, so that the transistor can also be turned on in the low voltage range (-20~10 V). As shown in Figure 3 -c, the transfer characteristic curve of the device is tested in the dark state, and by changing the range of the scanning voltage applied to the Si gate (10 V~60 V), the on-state current of the transistor channel is increased. As shown in Figure 3-d, to further investigate the variable resistance characteristics of WSe2, the source electrode is grounded, and the scan voltage of 0 V→30 V→0 V, 0 V→-30 V→0 V is applied to the Si gate electrode, and the potential change of the drain electrode is tested. It can be seen that the initial drain potential increases with the increase of the Si gate voltage, and when the Si gate voltage reaches 10 V and-20 V, the drain potential begins to decrease and gradually approaches 0 V. It is analyzed that in the range of-20 V~10 V, at this time WSe2 is in the off state, the drain potential is close to the Si gate potential; and once it exceeds 10 V or-20 V, at this time WSe2 is in the on state, the drain potential is equal to the source potential 0 V. During the above change process, light can improve the off-state current of WSe2, so that WSe2 is opened in the range of-20 V~10 V, and the drain potential is equal to the source potential 0 V.

[0048] As shown in Figure 4 , when the two-dimensional floating gate memory is in the dark state, and a positive pulse of 10 V is applied to the Si control gate, C1 is preferentially charged. Since the WSe2 transistor is in the off state, the voltage across the h-BN is not enough to trigger the Fowler-Nordheim tunneling, at this time the device behaves as a short-term memory dominated by capacitive coupling. In this process, the negative charge in WSe2 moves under the floating gate electrode, while the entire WSe2 floating gate is electrically neutral, so an equal amount of positive charge moves to the floating gate under the channel ( Figure 4 -a, Figure 4 -b). When the positive voltage is removed, the positive charge in the floating gate under the channel can electrostatically induce an equal amount of negative charge in the channel ( Figure 4 -c, Figure 4 -d), plus the short time required for the positive and negative charges in the WSe2 floating gate to recombine, so this mechanism explains the hysteresis direction of the short-term memory part of the reconfigurable floating gate memory and the corresponding transfer characteristic curve "left forward and right reverse" ( Figure 6 ). In addition, since light can adjust the off-state current of WSe2, when a 10 V positive pulse with a duration of 100 ms is applied to the two-dimensional floating gate memory, the short-term memory time of the memory gradually shortens when the light intensity is from 0~270 uW / cm 2 ( Figure 4 -e), define the time period when the current decays to 1 / 10 of its peak value as its time constant τ, from Figure 4 -f it can be seen that the short-term memory time of the floating gate memory can be adjusted in the range of 13.56~477.5 ms.

[0049] Further, in the embodiment, as shown in Figure 5As shown, when the two-dimensional floating gate memory is in the light state (455 nm, 116.06 mW / cm 2 ), and a 10 V positive pulse is applied to the Si control gate, at this time the WSe2 transistor is turned on, the entire floating gate is an integral whole, and the floating gate potential is quickly raised to the Fowler-Nordheim tunneling condition. At this time, a high electric field is formed across the h-BN tunneling layer, Fowler-Nordheim tunneling occurs, and the electrons in the channel are attracted by the positive voltage of the Si gate and injected into the floating gate layer and saved Figure 5 -a、 Figure 5 -b). When the positive voltage is removed, the negative charge in the floating gate layer can electrostatically induce an equal amount of positive charge in the channel Figure 5 -c、 Figure 5 -d), and the negative charge in the WSe2 floating gate layer can be long-term maintained. When a 10 V positive pulse or a -10 V negative pulse with a duration of 100 ms is applied to the control gate, the retention time is greater than 10 4 s Figure 5 -e), and thus this mechanism explains the long-term memory part of the reconfigurable floating gate memory and the hysteresis direction of the "left inverse right order" corresponding transfer characteristic curve Figure 6 -b). Similarly, under dark state conditions, when the Si control gate voltage is 20 V, the WSe2 transistor is turned on, the memory characteristics also change to long-term memory, and the retention time is greater than 10 4 s Figure 5 -f), and the corresponding transfer characteristic curve is the "left inverse right order" hysteresis direction Figure 6 -a).

[0050] Further, in the present embodiment, the reconfigurability of the present application is derived from the competitive relationship between the capacitive coupling effect of the floating gate layer WSe2 and the Fowler-Nordheim tunneling effect of the tunneling layer h-BN: when the WSe2 material is in the off state, the floating gate electrode charging and discharging process dominates the short-term memory behavior of the device; when the WSe2 is turned on, the floating gate potential is balanced, and the voltage across the h-BN reaches the Fowler-Nordheim tunneling condition to become long-term memory. Therefore, based on the photosensitive characteristics of the WSe2 material, by adjusting the Si control gate voltage and the light intensity, the on-off state of the WSe2 material can be controlled, and the short-term and long-term memory modes can be flexibly switched.

[0051] Further, in the present embodiment, as Figure 7As shown, the present application further builds a "2T1C" equivalent circuit model and verifies it in the SPICE simulation platform. The simulation circuit includes: MoTe2 transistor model, WSe2 transistor model, floating gate electrode and Si substrate coupling capacitor C1, tunneling layer h-BN capacitor C2, floating gate region below the channel and Si substrate coupling capacitor C3, and equivalent Fowler-Nordheim current channel bidirectional voltage regulator diode of the tunneling layer. To verify the working mechanism of the proposed reconfigurable two-dimensional floating gate memory and the physical realizability of its dual-mode memory behavior, based on the device physical structure and electrical characteristics, the present application builds a highly reduced "2T1C" equivalent circuit model, and models and simulates it in the SPICE (Simulation Program with Integrated Circuit Emphasis) simulation platform. The equivalent circuit model not only truly reflects the structure of the actual device, but also accurately simulates its dynamic response behavior under different external excitations (such as gate voltage, light).

[0052] As shown, Figure 7 The SPICE equivalent circuit model mainly includes the following core elements: first, the MoTe2 channel layer is equivalent to a composite model composed of two back-to-back connected PMOS and NMOS transistors, and is connected in parallel with a fixed resistor to simulate its output current characteristics as the main channel transistor; second, the two-dimensional floating gate layer WSe2 is modeled as a structure of two back-to-back PMOS and NMOS transistors and a photoresistor in parallel, where the resistance of the photoresistor changes dynamically with the incident light intensity, to reflect the photoelectric property of WSe2 material that the off-state current significantly increases under light; third, the coupling region between the floating gate electrode and the Si substrate is equivalent to the first capacitor C1 (the capacitance is about 1.3 pF), which is used to simulate the charge storage process dominated by capacitive coupling in the dark state; fourth, the h-BN tunneling layer between the MoTe2 channel and the WSe2 floating gate is equivalent to the second capacitor C2 (the capacitance is about 0.3 pF) and a pair of reverse series voltage regulator diodes in parallel, which is used to simulate the nonlinear opening characteristics of the Fowler-Nordheim tunneling current, i.e. only when the potential difference across the h-BN exceeds a certain threshold, the diode will be turned on; fifth, the coupling structure formed between the WSe2 floating gate region directly below the channel and the Si substrate is equivalent to the third capacitor C3 (the capacitance is about 1.7 fF), which is used to describe the influence of local electric field distribution on charge injection.

[0053] In the simulation process, different amplitude and polarity pulse voltages are applied to the Si control gate, and the resistance of the photoresistor is adjusted to equivalent different intensity of 455 nm light conditions (light intensity range 0~116.06 mW / cm 2). The simulation results show that when the control gate applies a positive pulse less than 15 V and the photoresistor is in a high resistance state (i.e. dark state), the WSe2 transistor equivalent model is in an off state, C1 is charged, but due to the voltage across the h-BN not reaching the Fowler-Nordheim tunneling threshold, charges cannot be injected into the floating gate, only through the charging and discharging of C1 to achieve a short-term current retention, which exhibits short-term memory behavior, with a retention time in the range of 10-500 ms, and shortens with increasing light intensity; while when the control gate voltage exceeds 15 V (dark state) or light is introduced at a lower voltage (<15 V) (so that the resistance of the photoresistor decreases and WSe2 is turned on), the WSe2 equivalent transistor is turned on, the floating gate potential rises rapidly, the electric field across the h-BN is enhanced, the voltage stabilizing diode is turned on, triggering Fowler-Nordheim tunneling, electrons are injected from the MoTe2 channel into the WSe2 floating gate and long-term reside, and the channel current state can still be maintained after the gate voltage is removed, with a retention time of more than 10 4 seconds, exhibiting long-term memory. By applying different pulse voltages and light equivalent inputs to the control gate, the simulation results obtained are consistent with the actual device test results: short-term memory under low voltage and dark state, and long-term memory under high voltage or light. The results prove the feasibility and universality of the technical scheme of the present application.

[0054] Most importantly, the transfer characteristic curve obtained by simulation has a hysteresis direction highly consistent with the experimental results: the short-term memory mode presents a "left forward and right reverse" hysteresis characteristic, and the long-term memory mode presents a "left reverse and right forward" hysteresis characteristic, which not only verifies the correctness of the dual-mode switching mechanism, but also shows that the equivalent circuit model has good physical fidelity and engineering applicability. In summary, the SPICE simulation not only proves the feasibility of the working principle of the memory device of the present application from the circuit level, but also provides a standardized model that can be directly called for subsequent integrated design, array-level simulation and brain-like computing circuit applications, fully embodying the dual value of the present application in theory and practice.

[0055] Further, in the present embodiment, to improve the material adaptability and process compatibility of the reconfigurable two-dimensional floating gate memory of the present application, and to expand its performance potential in different application scenarios, the key functional layer materials in the device can be reasonably replaced according to actual needs, and the replaced materials should have physical, electrical or optoelectronic properties comparable to or similar to the original materials, to ensure that the overall function of the device is not affected.

[0056] Specifically, the two-dimensional semiconductor channel layer material molybdenum telluride (MoTe2) can be replaced by other two-dimensional semiconductor materials with high carrier mobility, good on-off ratio and stable electrical characteristics, including but not limited to molybdenum disulfide (MoS2), tungsten diselenide (WSe2), black phosphorus (Black Phosphorus), etc. These materials all have atomic thickness, adjustable band gap and excellent field effect characteristics, which can effectively carry source-drain current as the channel layer, and realize stable threshold voltage shift under the regulation of floating gate charge, thereby supporting the realization of short-term and long-term memory behavior.

[0057] The two-dimensional insulating gate tunneling layer material hexagonal boron nitride (h-BN) can be replaced by other high-κ or dielectric layer materials with excellent tunneling characteristics, such as hafnium dioxide (HfO2), antimony trioxide (Sb2O3), etc. Such materials need to meet the following requirements: (1) have a high enough breakdown field strength to support the Fowler-Nordheim tunneling effect to occur under controllable voltage; (2) have a low interface state density to reduce carrier scattering and trap capture, and ensure the reversibility and stability of charge injection / erasure; (3) have good interface compatibility with the upper and lower two-dimensional material layers to avoid device performance degradation due to lattice mismatch or chemical reaction. Especially when using traditional CMOS process compatible materials such as HfO2, the integration potential of the device of the present application with existing integrated circuit manufacturing processes can be significantly improved.

[0058] Further, the two-dimensional floating gate layer material tungsten selenide (WSe2) can be replaced by other two-dimensional semiconductor materials with similar photosensitive properties. Such materials need to meet: in the dark state, a high off-state resistance is presented, and under light (especially visible light or near ultraviolet light), the off-state current is significantly increased, thereby realizing the light-controlled switching function, which is the core mechanism of the present application to realize the photoelectric cooperative regulation of memory mode switching. In addition to WSe2, candidate materials with similar photoelectric response behavior include but are not limited to molybdenum diselenide (MoSe2), some doped or defect-engineering-regulated transition metal chalcogenides (TMDs), and two-dimensional heterostructures with photo-induced conductivity enhancement effect. As long as the new material can effectively turn on under low gate voltage light conditions, the floating gate potential is overall lifted to the threshold value that triggers FN tunneling, which can realize the long-term memory function equivalent to the original WSe2 floating gate layer.

[0059] It needs to be emphasized that the above material replacement is not an arbitrary combination, but should be carried out on the premise of ensuring the integrity of the function of the "2T1C" basic architecture. That is: the channel layer needs to be able to modulate the output current in response to the change of the floating gate charge; the tunneling layer needs to support controllable charge injection under a certain electric field; the floating gate layer needs to have light-controlled conduction capability to realize memory mode switching. Through reasonable material selection and interface engineering optimization, the reconfigurable memory mechanism of the application can be extended to a variety of two-dimensional material systems, significantly enhancing its technical universality and industrialization prospects.

[0060] The application provides a reconfigurable two-dimensional floating gate memory with a "2T1C" structure, which realizes the dual-mode function of short-term and long-term memory through the competition between capacitive coupling and Fowler-Nordheim tunneling effect, and can realize reconfigurable switching through external voltage and light control. The scheme has simple structure and novel function, and is suitable for application in dual-mode memory and optoelectronic fusion intelligent storage circuit, and can also be used for brain-like computing, intelligent edge computing, medical health monitoring, financial data storage or data storage in Internet of Things devices.

[0061] It needs to be emphasized that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or system. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of another identical element in the process, method, article or system including the element.

[0062] The above application example serial numbers are only for description, not representing the advantages and disadvantages of the embodiments.

[0063] It needs to be emphasized that through the description of the above embodiments, those skilled in the art can clearly understand the embodiments, which can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions essentially or say the part that contributes to the prior art can be embodied in the form of software product, which can be stored in a computer readable storage medium such as ROM / RAM, magnetic disk, optical disk, etc., including a plurality of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the method described in each embodiment or some part of the embodiment.

[0064] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the same; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A reconfigurable two-dimensional floating gate memory, characterized in that, The memory has a layered structure, which includes, from bottom to top, a substrate (1), an oxide dielectric layer (2), a two-dimensional floating gate layer (8), a two-dimensional insulating gate tunneling layer (7), and a two-dimensional semiconductor channel layer (6). The memory also includes a source electrode (4), a drain electrode (5) and a floating gate electrode (3). The source electrode (4) and the drain electrode (5) are disposed on the surface and both sides of the two-dimensional semiconductor channel layer (6), and the floating gate electrode (3) is disposed on the surface of the two-dimensional floating gate layer (8). The material of the two-dimensional floating gate layer (8) is tungsten selenide, the material of the two-dimensional semiconductor channel layer (6) is molybdenum telluride, and the material of the two-dimensional insulating gate tunneling layer (7) is hexagonal boron nitride. The equivalent circuit components of the memory are: a two-dimensional floating gate layer (8) as the first transistor, a two-dimensional semiconductor channel layer (6) as the second transistor, the coupling region between the floating gate electrode (3) and the substrate (1) as the first capacitor, the coupling region between the two-dimensional semiconductor channel layer (6) and the two-dimensional floating gate layer (8) through the two-dimensional insulating gate tunnel layer (7) as the second capacitor, and the coupling region between the two-dimensional floating gate layer (8) directly below the two-dimensional semiconductor channel layer (6) and the substrate (1) as the third capacitor.

2. The reconfigurable two-dimensional floating gate memory as described in claim 1, characterized in that, The substrate (1) serves as the control gate of the memory, the source electrode (4) serves as the source of the memory, and the drain electrode (5) serves as the drain of the memory. If positive and negative scanning voltages are applied within the dark-state small control gate voltage range, the drain-source current of the transfer characteristic curve forms a hysteresis direction of "left forward and right reverse"; corresponding to applying positive / negative pulses to the control gate, the drain-source current exhibits a short-term memory effect. If positive and negative scanning voltages are applied within the range of large control gate voltage in the dark state or small control gate voltage in the light state, the drain-source current of the transfer characteristic curve will form a hysteresis direction of "left reverse and right forward". Correspondingly, when positive / negative pulses are applied to the control gate, the drain-source current will exhibit a long-term memory effect.

3. The reconfigurable two-dimensional floating gate memory as described in claim 1, characterized in that, The first transistor acts as a switch to control the drain-source current of the second transistor; the second transistor provides a path for the channel output current of the memory; the first capacitor can accommodate the charge generated by capacitive coupling before the first transistor is turned on; the second capacitor is used to isolate the charge exchange between the two-dimensional semiconductor channel layer (6) and the two-dimensional floating gate layer (8) to avoid excessive leakage current; the third capacitor is used to assist in adjusting the potential distribution of the two-dimensional floating gate layer (8) and optimize memory characteristics.

4. The reconfigurable two-dimensional floating gate memory as described in claim 2, characterized in that, The mechanism by which the memory achieves reconfigurable memory functionality is as follows: The short-term memory mechanism is realized by the two-dimensional floating gate layer (8) and the coupling capacitor between the floating gate electrode (3) and the substrate (1). In the dark state, when a positive control gate voltage is applied, the first transistor is in the off state, and the first capacitor begins to be charged with negative charge. The potential of the floating gate region below the channel does not reach the tunneling potential difference of the tunneling layer, and the channel layer cannot inject charge into the floating gate layer. When the positive control gate voltage is removed, the first capacitor begins to discharge. This process has a time constant, which is manifested as short-term memory. Long-term memory mechanisms are achieved through tunneling layers, and can be categorized into the following two types: In the dark state, when a larger positive control gate voltage is applied, the first transistor turns on and the charge originally stored in the first capacitor leaks out rapidly. The entire two-dimensional floating gate layer (8) is a whole, consistent with the principle of traditional floating gate memory. The potential difference between the two ends of the tunneling layer reaches the Fowler–Nordheim tunneling condition. The negative charge in the channel is injected into the floating gate layer and retained for a long time, which manifests as long-term memory. In the light state, due to the photosensitive properties of the two-dimensional floating gate layer (8), when the same positive control gate voltage as in the dark state is applied, the first transistor is turned on, and the entire two-dimensional floating gate layer (8) is a whole. When the voltage reaches the Fowler–Nordheim tunneling threshold of the tunneling layer, the negative charge in the channel is injected into the floating gate layer and retained for a long time, which is manifested as long-term memory.

5. The reconfigurable two-dimensional floating gate memory as described in claim 4, characterized in that, The memory exhibits short-term memory when it is in a dark state and a small pulse voltage is applied to the substrate control gate; When the control gate voltage of the memory is high, or when a photoelectric co-pulse is applied under low voltage, it exhibits long-term memory characteristics.

6. The reconfigurable two-dimensional floating gate memory as described in claim 4, characterized in that, The memory can switch between short-term and long-term memory modes under external voltage or light, and the switching between the two memory modes depends on the switching state of the two-dimensional floating gate layer (8).

7. The reconfigurable two-dimensional floating gate memory as described in claim 4, characterized in that, The short-term memory retention time is less than 10. 2 s, long-term memory retention time greater than 10 3 The retention time of short-term memory can be adjusted by different light intensities.

8. The reconfigurable two-dimensional floating gate memory as described in claim 1, characterized in that, The two-dimensional semiconductor channel layer material, molybdenum telluride, can be replaced with other two-dimensional semiconductor materials, such as molybdenum sulfide, tungsten selenide, and black phosphorus; the two-dimensional insulating gate tunneling layer material, hexagonal boron nitride, can be replaced with other dielectric layer materials, such as hafnium dioxide and antimony trioxide; and the two-dimensional floating gate layer material, tungsten selenide, can be replaced with other semiconductor materials that have the same or similar photoelectric properties as tungsten selenide.

9. The reconfigurable two-dimensional floating gate memory as described in claim 1, characterized in that, The simulation results of the equivalent circuit model of the memory in SPICE simulation are consistent with the experimental results, thus it can be extended to other memory devices with the same electrical behavior. The SPICE equivalent circuit model consists of the following parts: The two-dimensional floating gate layer (8) is equivalent to two PMOS and NMOS connected back to back in series and a photoresistor connected in parallel. The two-dimensional insulating gate tunnel layer (7) is equivalent to two Zener diodes connected back to back in series and a second capacitor connected in parallel. The two-dimensional semiconductor channel layer (6) is equivalent to two PMOS and NMOS connected back to back in series and a fixed resistor connected in parallel.

10. The reconfigurable two-dimensional floating gate memory according to claim 3, characterized in that, The capacitance values ​​of the first, second, and third capacitors are related as follows: the first capacitor is greater than the second capacitor, which is greater than the third capacitor.

11. The reconfigurable two-dimensional floating gate memory as described in claim 1, characterized in that, The memory is used for data storage in neuromorphic computing, intelligent edge computing, medical and health monitoring, financial data storage, or Internet of Things devices.

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