SSD performance test system and method
By integrating data compression and storage, parallel computing, and resource optimization modules into a hardware simulation acceleration platform, the problems of large storage space consumption and low performance analysis efficiency are solved, enabling more efficient and accurate SSD performance testing.
Patent Information
- Application Number
- CN202511617825.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-02-06
AI Technical Summary
Existing SSD performance testing based on hardware simulation acceleration platforms suffers from problems such as excessive storage space consumption, low performance analysis efficiency, and discrepancies between simulation and real performance.
The hardware simulation acceleration platform is equipped with a data compression and storage module, a parallel computing module, a computing resource optimization and allocation module, and a data analysis and calibration module. It employs efficient data compression algorithms, task scheduling algorithms, and performance calibration algorithms to achieve real-time monitoring, classified storage, and dynamic allocation of computing resources.
It significantly reduces storage space requirements, improves the efficiency and accuracy of performance testing, shortens the testing cycle, and ensures that test results are closer to real performance.
Smart Images
Figure CN121478419A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SSD controller chip development, specifically an SSD performance testing system and method. Background Technology
[0002] In the chip design phase of SSD controller chip development, hardware emulation acceleration platforms are typically used to simulate and test chip performance. The existing SSD performance testing process based on hardware emulation acceleration platforms mainly involves loading specific hardware projects and firmware programs, running a virtual host to simulate the single-port or dual-port operation of the SSD, issuing targeted performance test loads, collecting waveform files, and analyzing certain signals in the waveform files after the test to obtain the simulated performance results. Since waveform files generated from a single test typically occupy more than 50GB of space, waveform analysis is slow and inefficient due to limitations in the storage space, computing power, and hardware resources of the hardware emulation acceleration platform. Furthermore, if the timing of waveform capture is inappropriate, the analyzed performance results may be unsatisfactory, requiring retesting. Additionally, there is a certain difference between simulated and real performance. This leads to problems in existing FPGA simulation testing, such as excessive storage space consumption, low performance analysis efficiency, and discrepancies between simulated and real performance. Summary of the Invention
[0003] To address the shortcomings of existing technologies, this invention provides an SSD performance testing system and method. It integrates an additional data compression and storage module, a parallel computing module, a computing resource optimization and allocation module, and a data analysis and calibration module on a hardware simulation acceleration platform. Employing efficient data compression algorithms, task scheduling algorithms, and performance analysis and calibration algorithms, it supports single-port or dual-port performance testing, thereby improving the efficiency and accuracy of performance testing.
[0004] To solve the aforementioned technical problem, the technical solution adopted by the present invention is: an SSD performance testing system, including a data compression and storage module, a parallel computing module, a computing resource optimization and allocation module, and a data analysis and calibration module deployed on a hardware simulation acceleration platform; The data compression and storage module and the parallel computing module run simultaneously during the performance data acquisition phase. The parallel computing module monitors the read and write performance data in the virtual host in real time and distinguishes between non-critical and critical waveforms. The data compression and storage module discards non-critical waveforms and compresses and classifies the critical waveforms for storage. The data analysis and calibration module first analyzes the stored key waveforms. It first reads out the key waveforms and decompresses them, then analyzes the raw waveforms obtained from the decompression to obtain performance data. Then, it corrects the analysis results according to the calibration model to make them closer to the actual performance. The computational resource optimization and allocation module dynamically allocates the FPGA platform's computational resources based on the priority and computational complexity of the waveform analysis task.
[0005] Furthermore, the data compression and storage module classifies and stores the compressed data as follows: it classifies and stores the data according to the timestamp and test scenario, establishes an index table, and records the storage location and related attributes of the data; during waveform analysis, it quickly locates and reads the compressed data according to the index table, and then performs decompression to restore the original data.
[0006] Furthermore, the computing resource optimization and allocation module dynamically allocates computing resources on the FPGA platform as follows: assign a priority to each performance analysis task, adopt a task scheduling algorithm, monitor the computing resource usage of the FPGA platform in real time, when a new task arrives, allocate the task according to the priority and resource status, and decompose and optimize the computing task, dividing large tasks into multiple small tasks for parallel execution, so as to make full use of the FPGA's parallel computing capabilities.
[0007] Furthermore, the calibration model is derived as follows: establish a mapping relationship between real performance and FPGA test performance, conduct comparative tests simultaneously in real application scenarios and on the FPGA platform, collect performance data under different test conditions, and use regression analysis to establish a calibration model.
[0008] Furthermore, the data analysis and calibration module converts the decompressed raw waveform into a txt format, and then uses a text processing script to calculate the performance data.
[0009] Furthermore, the data compression and storage module uses a hardware compression engine to compress key waveforms, and the hardware compression engine employs a hierarchical data compression algorithm.
[0010] Furthermore, priorities are determined based on the importance and urgency of the task to the test results.
[0011] Furthermore, the task scheduling algorithm adopts a priority-based preemptive scheduling algorithm.
[0012] Furthermore, non-critical waveforms are those from the initialization phase and the performance unstable phase, while critical waveforms are those from the performance stable phase or a specified phase.
[0013] This invention also discloses an SSD performance testing method, which is implemented using the aforementioned testing system and includes the following steps: S01. On the hardware simulation acceleration platform, run the hardware project and firmware program that simulates the operation of the SSD hard drive. After the SSD hard drive starts running, display the firmware power-on and running information through the serial port module. S02. Run a virtual host based on a hardware emulation acceleration platform and connect the PCIe link of the SSD hard drive to the virtual host. S03. After the SSD is detected in the virtual host, it is formatted and then the performance test load is distributed. S04. Execute the test load. The parallel computing module monitors the read and write performance data in the virtual host in real time, distinguishes between non-critical waveforms and critical waveforms, and the data compression and storage module discards non-critical waveforms and compresses and classifies the critical waveforms for storage. S05. After the test is completed, the waveform data is analyzed in conjunction with the order and time of the performance test load distribution, and after data calibration, the final performance data is output. The data analysis and calibration module analyzes the stored key waveforms. First, it reads out the key waveforms and decompresses them. Then, it analyzes the raw waveforms obtained from the decompression to obtain performance data. The computing resource optimization and allocation module dynamically allocates computing resources on the FPGA platform based on the priority and computational complexity of the waveform analysis task. The test result correction module corrects the test results based on the calibration model to make them closer to the actual performance.
[0014] The beneficial effects of this invention are as follows: First, by using a data compression and storage module, this invention significantly reduces the storage space for performance data, lowers storage costs, and improves the convenience of storage management.
[0015] Secondly, the computing resource optimization and allocation module makes full use of the computing power of the FPGA platform, improves computing efficiency, shortens the testing cycle, and meets the needs of rapid product development iteration.
[0016] Finally, the performance calibration module effectively narrowed the gap between FPGA performance and actual performance, improved the accuracy of test results, and provided a more reliable basis for SSD performance evaluation and optimization. Attached Figure Description Figure 1 This is a schematic diagram of the test system. Figure 2 This is a flowchart of the testing method. Detailed Implementation
[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0018] Example 1 This embodiment discloses an SSD performance testing system, such as... Figure 1As shown, this system includes a hardware simulation acceleration platform and a data compression and storage module, a parallel computing module, a computing resource optimization and allocation module, and a data analysis and calibration module deployed on the hardware simulation acceleration platform.
[0019] The data compression and storage module and the parallel computing module run simultaneously during the performance data acquisition phase. The parallel computing module monitors the read and write performance data in the virtual machine in real time, distinguishing between non-critical and critical waveforms. The data compression and storage module discards the non-critical waveforms and compresses and categorizes the critical waveforms for storage. In this embodiment, non-critical waveforms are those from the initialization phase and the performance unstable phase, while critical waveforms are those from the performance stable phase or a specified phase. The data compression and storage module uses a hardware compression engine to compress the critical waveforms. The hardware compression engine employs efficient hierarchical data compression algorithms, such as the LZ77 algorithm and its improved versions in lossless compression algorithms, to compress the waveform data. During storage, the compressed data is stored in a specially designed storage structure, categorized according to the data's timestamp and test scenario, and an index table is established to record the data's storage location and related attributes for subsequent rapid retrieval and reading. This approach significantly reduces the space required for performance data storage and lowers storage costs.
[0020] The data analysis and calibration module first analyzes the stored key waveforms. It first reads and decompresses the key waveforms, then analyzes the decompressed raw waveforms to obtain performance data. During waveform analysis, it quickly locates and reads compressed data using an index table, then decompresses it to restore the original data. The waveform parsing method involves converting the original waveform format (ztdb, etc.) into txt format through a series of operations, and then using a text processing script to calculate the performance data. The test results are then corrected according to a calibration model to make them closer to real-world performance. The calibration model is derived by establishing a mapping relationship between real-world performance and FPGA test performance, conducting comparative tests simultaneously on real-world application scenarios and the FPGA platform, collecting performance data under different test conditions, and using regression analysis to build a calibration model. After each FPGA platform test, the test results are corrected according to the calibration model to make them closer to real-world performance, effectively solving the problem of discrepancies between FPGA performance and real-world performance.
[0021] The computational resource optimization and allocation module dynamically allocates FPGA platform computing resources based on the priority and computational complexity of waveform analysis tasks. Specifically, each performance analysis task is assigned a priority, determined by its importance and urgency to the test results. A task scheduling algorithm, such as a priority-based preemptive scheduling algorithm, is employed to monitor the FPGA platform's computing resource usage in real time. When a new task arrives, it is allocated based on priority and resource availability, prioritizing tasks with a significant impact on test results and high computational complexity. Simultaneously, computational tasks are decomposed and optimized, dividing large tasks into multiple smaller tasks for parallel execution. This fully utilizes the FPGA's parallel computing capabilities, improves computational efficiency, and addresses the limitation of the FPGA platform's computing power.
[0022] Example 2 This embodiment discloses an SSD performance testing method. This method is implemented based on the testing system described in Embodiment 1. Figure 2 As shown, it includes the following steps: (1) Prepare a hardware simulation acceleration platform and deploy a data compression and storage module, a parallel computing module, a computing resource optimization and allocation module, and a data analysis and calibration module.
[0023] (2) On the hardware simulation acceleration platform, run specific hardware projects and firmware programs to simulate the operation of SSD hard disk. After the hard disk starts running, the corresponding firmware power-on and running information can be displayed through the serial port module.
[0024] (3) Run a virtual host based on a hardware emulation acceleration platform and connect the PCIe link of the SSD hard drive to the virtual host.
[0025] (4) After the SSD is detected in the virtual host, it is formatted and then a performance test load is sent, including sequential read, sequential write, random read, and random write loads.
[0026] (5) While performing the test load in step (4), the data hierarchical compression storage module and parallel computing module are used to collect the performance data (bandwidth, IOPS, etc.) of the virtual host and perform targeted compression processing on the original waveform data.
[0027] (6) After the test is completed, the waveform data is analyzed in combination with the order and time of the performance test load distribution, and after data calibration, the final performance data is output.
[0028] This invention integrates additional data compression and storage modules, parallel computing modules, computing resource optimization and allocation modules, and data analysis and calibration modules on a hardware simulation acceleration platform. It employs efficient data compression algorithms, task scheduling algorithms, performance analysis and calibration algorithms, and supports single-port or dual-port performance testing. It addresses the core pain points in FPGA simulation testing, such as excessive storage space consumption, low performance analysis efficiency, and discrepancies between simulation and real performance, thereby improving the efficiency and accuracy of SSD performance testing.
[0029] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.
Claims
1. An SSD performance testing system, characterized in that: The data compression storage module, the parallel computing module, the computing resource optimization allocation module, and the data analysis and calibration module are deployed on a hardware simulation acceleration platform. The data compression storage module and the parallel computing module run simultaneously in a performance data collection stage, the parallel computing module monitors read-write performance data in a virtual host in real time, distinguishes non-key waveforms and key waveforms, the data compression storage module discards the non-key waveforms and stores the key waveforms after compression and classification. The data analysis and calibration module first analyzes the stored key waveforms, reads out the key waveforms and decompresses them, then analyzes the original waveforms obtained after decompression to obtain performance data, and then corrects the analysis results according to a calibration model to make them closer to the real performance. The computing resource optimization allocation module dynamically allocates computing resources of the FPGA platform according to priorities and computing complexities of waveform analysis tasks.
2. The SSD performance test system of claim 1, wherein: The data compression storage module classifies and stores the compressed data according to timestamps and test scenarios, establishes an index table, and records storage locations and related attributes of the data. In waveform analysis, the index table is used to quickly locate and read the compressed data, and then the original data is recovered after decompression.
3. The SSD performance test system of claim 1, wherein: The computing resource optimization allocation module dynamically allocates computing resources of the FPGA platform by assigning a priority to each performance analysis task, using a task scheduling algorithm, monitoring the use of computing resources of the FPGA platform in real time, assigning tasks according to priorities and resource conditions when new tasks arrive, and decomposing and optimizing the computing tasks to fully utilize the parallel computing capability of the FPGA.
4. The SSD performance test system of claim 1, wherein: The calibration model is obtained by establishing a mapping relationship between real performance and FPGA test performance, conducting comparative tests on real application scenarios and the FPGA platform, collecting performance data under different test conditions, and using regression analysis to establish the calibration model.
5. The SSD performance test system of claim 1, wherein: The data analysis and calibration module converts the original waveforms obtained after decompression into a txt format, and then calculates the performance data through a text processing script.
6. The SSD performance test system of claim 2, wherein: The data compression storage module uses a hardware compression engine to compress key waveforms, and the hardware compression engine uses a hierarchical data compression algorithm.
7. The SSD performance test system of claim 3, wherein: The priority is determined according to the importance and urgency of the test results.
8. The SSD performance testing system of claim 3, wherein: The task scheduling algorithm uses a priority-based preemptive scheduling algorithm.
9. The SSD performance testing system of claim 1, wherein: The non-key waveforms are waveforms in the initialization stage and the performance unstable stage, and the key waveforms are waveforms in the performance stable stage or specified stage. 10.A method for testing performance of an SSD, the method being implemented based on the system of claim 1, characterized in that: The method comprises the following steps: S01. On a hardware simulation acceleration platform, run hardware engineering and firmware programs simulating an SSD hard disk, and display firmware power-on and running information through a serial module after the SSD hard disk starts running; S02. Run a virtual host based on the hardware simulation acceleration platform, and connect a PCIe link of the SSD hard disk to the virtual host; S03. After identifying the SSD hard disk in the virtual host, perform a formatting operation, and then issue a performance test load. S04, execute test load, and the parallel computing module monitors the read-write performance data in the virtual host in real time, distinguishes non-key waveforms and key waveforms, the data compression storage module discards the non-key waveforms, and compresses and classifies the storage of the key waveforms; S05, after the test is completed, the waveform data is analyzed in combination with the sequence and time under the performance test load, and the final performance data is output after data calibration; The data analysis and calibration module analyzes the stored key waveforms, first reads out the key waveforms and decompresses them, then analyzes the original waveforms obtained by decompression to obtain performance data; The computing resource optimization allocation module dynamically allocates the computing resources of the FPGA platform according to the priority and computing complexity of the waveform analysis task; The test result correction module corrects the test result according to the calibration model, so that it is closer to the real performance.