GNN-guided layered H-tree low-skew clock tree synthesis method
By employing a GNN-guided hierarchical H-tree low-skew clock tree synthesis method, utilizing capacitance-constrained clustering and graph neural networks to optimize buffer locations, and combining a sparse grid integration algorithm, the problem of low resource utilization efficiency in existing clock tree synthesis methods under advanced processes is solved, achieving a low-power and high-efficiency clock network design.
Patent Information
- Application Number
- CN202511603546.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-04
- Publication Date
- 2026-02-06
AI Technical Summary
Existing clock tree synthesis methods struggle to effectively capture clock tree structure characteristics under advanced processes, neglecting the impact of capacitor balance on timing consistency, resulting in low resource utilization efficiency and failing to meet low-power design requirements.
A hierarchical H-tree low-skew clock tree synthesis method guided by GNN is adopted. By optimizing the buffer position and topology through capacitance-constrained clustering and graph neural network prediction, a global clock network is constructed by combining a sparse grid integration algorithm.
Significantly reduces RC latency, improves timing consistency, reduces clock skew, optimizes resource utilization, provides an efficient backbone connectivity architecture, and meets low-power design requirements.
Smart Images
Figure CN121480436A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit physical design automation technology, and in particular to a GNN-guided hierarchical H-tree low-skew clock tree synthesis method. Background Technology
[0002] Clock tree synthesis is a critical step in integrated circuit physical design. Layout heterogeneity and process fluctuations under advanced processes make clock skew control increasingly difficult, and clock network power consumption usually accounts for more than 50% of the total chip power consumption, which has a significant impact on design quality.
[0003] Current mainstream clock tree synthesis methods include H-trees, herringbone topology, and mesh topology. H-trees can theoretically achieve zero skew on geometrically symmetric paths, but the winding length increases significantly when the layout is unbalanced. Herringbone topology can reduce winding length, but the risk of electromigration at branch junctions is high. Mesh topology has the advantages of low skew and high robustness, but its high power consumption makes it difficult to meet low-power design requirements. At the algorithm level, delay-merging embedding algorithms are computationally complex and have weak obstacle avoidance capabilities, while the median method suffers severe skew deterioration under load imbalance.
[0004] In recent years, machine learning techniques have begun to be applied to clock tree synthesis. However, existing methods mostly employ fully connected neural networks, which struggle to effectively capture the structural characteristics of clock trees, resulting in limited prediction accuracy. More significantly, existing technologies generally neglect the impact of capacitor balance on timing consistency, lack adaptive handling capabilities for layout heterogeneity, and are unable to dynamically adjust the topology based on local load characteristics. This leads to low resource utilization efficiency and severely restricts the development of clock tree synthesis technology under advanced processes. Summary of the Invention
[0005] In view of this, the purpose of this invention is to provide a GNN-guided hierarchical H-tree low-skew clock tree synthesis method, which significantly improves the synthesis quality of clock trees through the synergistic optimization of capacitance-constrained clustering and graph neural network prediction.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a GNN-guided hierarchical H-tree low-skew clock tree synthesis method, comprising the following steps: Step S1: Perform fan-out-radius-capacitance three-constraint K-means clustering on all registers of the chip to generate optimized buffer leaf clusters; Step S2: Extract the spatial and electrical features of the buffer distribution to construct a multi-dimensional feature vector; Step S3: Input the feature vector into a graph GNN predictor to predict the clock performance index corresponding to the candidate K value; Step S4: Select the optimal K value based on the weighted cost function and perform secondary clustering on the buffers; Step S5: Dynamically generate an adaptive non-uniform branch H-tree based on the clustering results; Step S6: Construct a global clock network through a sparse grid integration algorithm.
[0007] In a preferred embodiment: In step S1; the objective function of the fan-out, radius, and capacitance three-constraint K-means clustering is:
[0008]
[0009]
[0010]
[0011]
[0012] in, For the total cost, For the cost of distance, To pay the price, For the cost of capacitors, , , These are the weighting coefficients for distance cost, fan-out cost, and capacitance cost. For register location, The location of the cluster center This represents the number of registers in the current cluster. For maximum fan-out constraint, To determine the penalty coefficient for violations, For register load capacitor, The target capacitance value is the ratio of the total capacitance to the number of clusters. These are the variance weighting coefficients. Let V be the variance of the intra-cluster capacitance.
[0013] In a preferred embodiment: the method for selecting the location of the buffer for the capacitor-weighted centroid is as follows:
[0014]
[0015] in, The location of the buffer at the capacitor-weighted centroid. For the first The x and y coordinates of each register location, For the first The load capacitance of each register This indicates the total number of all registers.
[0016] In a preferred embodiment: In step S1; initial stack number The selected dynamic decision-making mechanism is:
[0017]
[0018]
[0019] in, Total number of registers For maximum fan-out constraint, For point and points Manhattan distance between them For the reference point set, For point The set of points in the neighborhood, Cluster radius constraint;
[0020] The decision function is:
[0021]
[0022] in, The maximum density value of the region. For maximum fan-out constraint; when the maximum density value of the high-density region exceeds the maximum fan-out limit, the theoretical minimum number of stacks is selected as the initial number of stacks to ensure that the high-load region does not violate the fan-out constraint; otherwise, the theoretical maximum number of stacks is selected as the initial number of stacks to make the sparse distribution region meet the radius limit.
[0023] In a preferred embodiment, in step S2, the constructed feature vector includes:
[0024] Global statistical characteristics: Total number of buffers Standard deviation of position coordinates Minimum drive load Maximum drive load ;
[0025] Spatial distribution characteristics: 5×5 grid load capacitance density matrix Each element in the density matrix Represents the corresponding grid cell The formula for calculating the internal normalized load capacitance density is as follows:
[0026] in, For the first for the second line, number Column grid cells, The load capacitance of all buffers falling within this grid cell. The sum of The area of a single grid cell. The largest single load capacitance value among all buffers is used to normalize the density value.
[0027] In a preferred embodiment: In step S3; the architecture of the graph GNN includes:
[0028] Graph construction: Node set edge set The system is constructed based on spatial proximity and electrical coupling, where nodes include all buffers and key registers, and edges are established based on physical connections and electrical interactions.
[0029] Node characteristics: ,in( () represents the normalized position coordinates. For load capacitance, For timing criticality, For node type;
[0030] Edge features: ,in For Manhattan distance, For coupling capacitors, For shared path coefficients;
[0031] The network structure adopts a three-layer graph attention mechanism, containing a neuron configuration of 64-32-16. Each layer uses a multi-head attention mechanism for feature extraction. Residual connections and layer normalization are used to ensure training stability. Finally, the predicted values of clock skew, maximum latency and buffer number are output through global pooling layers and fully connected layers.
[0032] In a preferred embodiment: the graph neural network employs a three-layer message passing mechanism, each layer being carefully designed to effectively extract and pass feature information; node feature updates are performed using the following formula:
[0033] in, For the first Layer nodes Features , For the first The trainable weight matrix of the layer, It is a ReLU activation function. For nodes The set of neighboring nodes, The edge feature transformation function is implemented using a two-layer multilayer perceptron (MLP).
[0034] In a preferred embodiment: a binary chain structure is used in the light-load area, and the total wiring length cost is:
[0035]
[0036] in, Indicates the current region. The Manhattan distance between adjacent buffers. Indicates the current region The total wiring cost is the sum of the Manhattan distances of all adjacent buffers in the binary chain;
[0037] The heavy-load region adopts a standard quadtree structure, and the skew control target is represented as:
[0038]
[0039] in, Indicates the current region. This represents the maximum skewness of a quadtree node, which is the difference between the maximum and minimum delays from the root node to a leaf node. In a quadtree, from the root node to... Node clock latency, This represents the clock delay difference from the root node to different leaf nodes in the quadtree. The maximum clock skew is calculated by taking the two leaf nodes with the largest clock delay difference.
[0040] In a preferred embodiment: In step S6; the optimization objective of sparse mesh integration is based on the minimum Steiner tree theory, ensuring that the root nodes of all subtrees are... Minimize the total mesh wiring length while ensuring connectivity in the mesh graph:
[0041]
[0042] in Represents the set of edges in a sparse grid. Representing an edge The physical length.
[0043] In a preferred embodiment: the minimum Steiner tree problem is solved using an improved geometric algorithm, which treats the root node of the subtree as a terminal point that must be connected, and the grid intersection point as a candidate Steiner point; the improved geometric algorithm first constructs a complete graph between terminal points, and calculates the edge weights using Manhattan distance; then it generates a minimum spanning tree on the complete graph; then it replaces each edge in the minimum spanning tree with the shortest path in the grid graph; finally, it adjusts the position of the Steiner point through local optimization techniques to eliminate redundant connections and obtain a connection topology with the minimum total length.
[0044] Compared with the prior art, the present invention has the following beneficial effects:
[0045] (1) Compared with the traditional geometric center method, the capacitance weighted centroid method of the present invention optimizes the electrical drive characteristics by bringing the register with a larger load capacitance closer to the buffer position, which can effectively reduce RC delay, and at the same time significantly improve timing consistency and reduce clock skew through balanced capacitance distribution.
[0046] (2) The stack number selection method can achieve a balance between load constraints and physical constraints, preventing high-density areas from exceeding the buffer driving capacity and avoiding excessive wiring in sparse areas, laying the foundation for subsequent buffer deployment and clock tree generation, while minimizing the overall number of clusters to optimize resource utilization.
[0047] (3) While ensuring global connectivity, it effectively reduces the consumption of cabling resources and provides an efficient backbone connection architecture for the clock network. Attached Figure Description
[0048] Figure 1 This is a flowchart illustrating a preferred embodiment of the present invention;
[0049] Figure 2 This is a partial topology diagram of the clock tree according to a preferred embodiment of the present invention. Detailed Implementation
[0050] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0051] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0052] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0053] A GNN-guided method for synthesizing hierarchical H-tree low-skew clock trees, referenced Figure 1-2 The process includes the following steps: Step S1: Perform fan-out-radius-capacitance three-constraint K-means clustering on all registers of the chip to generate optimized buffer leaf clusters; Step S2: Extract the spatial and electrical features of the buffer distribution and construct a multi-dimensional feature vector; Step S3: Input the feature vector into a graph GNN predictor to predict the clock performance index corresponding to the candidate K value; Step S4: Select the optimal K value based on the weighted cost function and perform secondary clustering on the buffers; Step S5: Dynamically generate an adaptive non-uniform branch H-tree based on the clustering results; Step S6: Construct a global clock network through a sparse grid integration algorithm.
[0054] The technical solution adopted in this invention includes the following innovative points:
[0055] 1. Three-constraint clustering method for capacitance balance
[0056] This invention innovatively introduces capacitance balance constraints into the traditional fan-out and physical radius constraints, forming a three-constraint clustering optimization framework. The method first performs feature analysis on all registers of the chip, extracting the position coordinates and load capacitance parameters of each register. The clustering process employs an improved K-means algorithm, whose objective function comprehensively considers three dimensions: geometric distance, fan-out constraint, and capacitance balance.
[0057]
[0058]
[0059]
[0060]
[0061] in, For the total cost, Distance cost, used to measure the geometric distance from intra-cluster registers to cluster centers. To mitigate fan-out costs, ensure that the number of registers in each cluster does not exceed the buffer drive capacity. The capacitance cost includes the deviation between the total cluster capacitance and the target capacitance, as well as the variance of the intra-cluster capacitance. , , These are the weighting coefficients for distance cost, fan-out cost, and capacitance cost. For register location, The location of the cluster center This represents the number of registers in the current cluster. For maximum fan-out constraint, To determine the penalty coefficient for violations, For register load capacitor, The target capacitance value is the ratio of the total capacitance to the number of clusters. These are the variance weighting coefficients. Let V be the variance of the intra-cluster capacitance.
[0062] Regarding buffer location selection, this invention proposes an innovative capacitance-weighted centroid method, completely replacing the traditional geometric center calculation method. The core idea of this method is to determine the buffer location based on electrical importance rather than simply geometric position.
[0063]
[0064] in, For register coordinates, This corresponds to the load capacitor of the register.
[0065] An iterative refinement strategy is employed during the calculation. First, an initial solution is generated based on the traditional geometric center. Then, the position is progressively optimized using capacitance weighting. Electrical performance is re-evaluated after each iteration until the position change is less than a preset threshold. This method ensures that the large-capacitor register is closer to the buffer location, effectively reducing RC delay and improving electrical symmetry.
[0066] The initial number of clusters is determined using an intelligent dynamic decision-making mechanism that comprehensively considers register distribution density and various constraints. The decision-making process is based on statistical analysis theory to ensure the rationality and effectiveness of the number of clusters.
[0067] The theoretical minimum number of clusters is determined by the fan-out constraint:
[0068]
[0069] The theoretical maximum number of clusters is determined by the physical radius constraint:
[0070]
[0071] The decision function is:
[0072]
[0073] in, Total number of registers For maximum fan-out constraint, For point and points Manhattan distance between them For the reference point set, For point The set of points in the neighborhood, For cluster radius constraints, The maximum density value of the region. For maximum fan-out constraint. When the maximum density value of the high-density region exceeds the maximum fan-out limit, the theoretical minimum number of stacks is selected as the initial number of stacks to ensure that the high-load region does not violate the fan-out constraint; otherwise, the theoretical maximum number of stacks is selected as the initial number of stacks to ensure that the sparsely distributed region meets the radius limit.
[0074] 2. Design of GNN (Graph Neural Network) Predictor
[0075] This invention employs a graph neural network architecture to replace the traditional fully connected neural network, fully utilizing the topological characteristics of the clock tree. The graph construction process includes two key steps: node definition and edge establishment, ensuring accurate capture of the complex relationships between elements in the clock tree.
[0076] Node set Including all buffers and key registers, the feature vector of each node is defined as follows:
[0077]
[0078] in( () represents the normalized position coordinates. To normalize the load capacitance value, As a time-series key indicator, This multidimensional feature representation, used to identify node types, comprehensively describes the characteristics and state of each node.
[0079] edge set Based on spatial proximity and electrical coupling, the feature vector of each edge contains four important parameters:
[0080]
[0081] in To normalize the Manhattan distance, The coupling capacitance coefficient is... To share path weights, these parameters collectively define the strength and quality of the interactions between nodes.
[0082] The graph neural network employs a three-layer message passing mechanism, and the node feature update formula for each layer is as follows:
[0083] in, For the first Layer nodes Features , For the first The trainable weight matrix of the layer, It is a ReLU activation function. For nodes The set of neighboring nodes, The edge feature transformation function is implemented using a two-layer multilayer perceptron (MLP).
[0084] After multi-layer graph convolution, the information of the entire graph is integrated through a combination of global max pooling and global average pooling operations.
[0085] The final output layer predicts three key performance indicators: clock skew, maximum clock delay, and buffer number ratio. Clock skew and maximum delay are calculated using linear activation functions, while the buffer number ratio is normalized using a sigmoid activation function to ensure that the output results conform to physical meaning and actual constraints.
[0086] 3. Adaptive Non-uniform H-tree Architecture Generation
[0087] Based on the prediction results of graph neural networks, this invention proposes an adaptive non-uniform H-tree architecture that dynamically selects the optimal topology according to local load characteristics. First, load density analysis is performed on the regions after secondary clustering:
[0088]
[0089] in, For the region The number of effective buffers within, For the area, For indicator functions, when node The value is 1 when it is a buffer, and 0 otherwise. This calculation method can accurately reflect the load intensity of the area.
[0090] Calculate global load density statistics to establish a classification benchmark:
[0091]
[0092]
[0093] in, This represents the average load density. This represents the standard deviation of the load density across all regions; a larger value indicates a more dispersed density distribution. For the total number of regions, For the region Load density.
[0094] With average load density As a classification threshold, the region intelligence is divided into light-load region and heavy-load region.
[0095] For the lightly loaded areas identified by classification, the system adopts a binary chain topology, and the formula for the total cabling length cost is:
[0096]
[0097] in, Indicates the current region. The Manhattan distance between adjacent buffers.
[0098] The sorting process uses the nearest neighbor algorithm to ensure the total path length is minimized. Then, corner optimization is performed to reduce the number of turning points through local adjustments, thereby improving the routing quality.
[0099] For heavily loaded regions, a standard quadtree structure is used, with the construction process performed hierarchically: the first level constructs four main branches, placing a buffer at the geometric center of each branch. The second level recursively performs the same operation on each sub-region until a termination condition is met. Each level undergoes rigorous timing verification to ensure symmetrical routing and load balancing. The skew control objective is expressed as:
[0100]
[0101] in, Indicates the current region. In a quadtree Node clock latency.
[0102] After the basic topology is generated, the system performs local optimization operations. First, timing-driven fine-tuning is performed, optimizing buffer positions using gradient descent. Then, load balancing adjustments are made to ensure that load differences between branches are kept within acceptable limits. Finally, design rule checks are executed to verify that the results meet process requirements. The entire generation process employs an iterative optimization strategy until all metrics reach preset targets. This phased approach ensures the stability and reliability of the generated architecture.
[0103] 4. Sparse Mesh Global Integration Algorithm
[0104] To efficiently connect non-uniform subtrees and achieve global low-skew synchronization, this invention proposes a sparse grid integration algorithm based on Steiner's minimum tree.
[0105] First, a virtual global routing mesh is defined at the top level of the chip. After the mesh is generated, all subtree root nodes are mapped to the nearest mesh point to establish an initial connectivity graph. Next, the weight coefficients of each edge are calculated, taking into account geometric distance, timing requirements, and routing resources. An improved A* search algorithm is used to find initial connectivity paths, employing a multi-objective optimization strategy in the search process.
[0106]
[0107] in, For nodes Total estimated cost, From the starting point to the node The actual cost, For the node Heuristic cost estimation to the root node of the target subtree. These are the time-series weighting coefficients. This is the power consumption weighting factor. The time-dependent cost function is calculated based on path length and load capacitance. This is the power consumption-related cost function.
[0108] The algorithm maintains a priority queue, expanding the node with the lowest cost each time. During expansion, geometric paths, timing constraints, and power limitations are considered simultaneously to ensure that the found path achieves optimal performance across multiple dimensions. After the search is complete, the system generates an initial Steiner tree containing all necessary connection points and relay nodes. Timing analysis is then performed to verify whether the global skew constraint is satisfied. The connection topology is improved through multiple rounds of optimization using simulated annealing. First, topology transformations are performed, including edge swaps, node movements, and path redistribution. The transformation magnitude gradually decreases with the number of iterations, achieving a smooth transition from global search to local optimization.
Claims
1. A GNN-guided method for synthesizing hierarchical H-tree low-skew clock trees, characterized in that, Includes the following steps: Step S1: Perform fan-out-radius-capacitance three-constraint K-means clustering on all registers of the chip to generate optimized buffer leaf clusters; Step S2: Extract the spatial and electrical features of the buffer distribution and construct a multidimensional feature vector; Step S3: Input the feature vector into the graph GNN predictor to predict the clock performance index corresponding to the candidate K value; Step S4: Select the optimal K value based on the weighted cost function and perform secondary clustering on the buffer; Step S5: Dynamically generate an adaptive non-uniform branch H-tree based on the clustering results; Step S6: Construct a global clock network using a sparse grid integration algorithm.
2. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that: In step S1, the objective function of the fan-out, radius, and capacitance three-constraint K-means clustering is: in, For the total cost, For the cost of distance, To pay the price, For the cost of capacitors, , , These are the weighting coefficients for distance cost, fan-out cost, and capacitance cost. For register location, The location of the cluster center This represents the number of registers in the current cluster. For maximum fan-out constraint, To determine the penalty coefficient for violations, For register load capacitor, The target capacitance value is the ratio of the total capacitance to the number of clusters. These are the variance weighting coefficients. Let V be the variance of the intra-cluster capacitance.
3. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 2, characterized in that: The method for selecting the location of the buffer for the capacitor-weighted centroid is as follows: in, The location of the buffer at the capacitor-weighted centroid. For the first The x and y coordinates of each register location, For the first The load capacitance of each register This indicates the total number of all registers.
4. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that: In step S1; initial heap number The selected dynamic decision-making mechanism is: in, Total number of registers For maximum fan-out constraint, For point and points Manhattan distance between them For the reference point set, For point The set of points in the neighborhood, Cluster radius constraint; The decision function is: in, The maximum density value of the region. For maximum fan-out constraint; when the maximum density value of the high-density region exceeds the maximum fan-out limit, the theoretical minimum number of stacks is selected as the initial number of stacks to ensure that the high-load region does not violate the fan-out constraint; otherwise, the theoretical maximum number of stacks is selected as the initial number of stacks to make the sparse distribution region meet the radius limit.
5. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that, In step S2; The constructed feature vectors include: Global statistical characteristics: Total number of buffers Standard deviation of position coordinates Minimum drive load Maximum drive load ; Spatial distribution characteristics: 5×5 grid load capacitance density matrix Each element in the density matrix Represents the corresponding grid cell The formula for calculating the internal normalized load capacitance density is as follows: in, For the first for the second line, number Column grid cells, The load capacitance of all buffers falling within this grid cell. The sum of The area of a single grid cell. The largest single load capacitance value among all buffers is used to normalize the density value.
6. The GNN-guided hierarchical H-tree low-skew clock tree synthesis method according to claim 1, characterized in that: In step S3; the architecture of the graph GNN includes: Graph construction: Node set edge set The system is constructed based on spatial proximity and electrical coupling, where nodes include all buffers and key registers, and edges are established based on physical connections and electrical interactions. Node characteristics: ,in( () represents the normalized position coordinates. For load capacitance, For timing criticality, For node type; Edge features: ,in For Manhattan distance, For coupling capacitors, For shared path coefficients; The network structure adopts a three-layer graph attention mechanism, containing a neuron configuration of 64-32-16. Each layer uses a multi-head attention mechanism for feature extraction. Residual connections and layer normalization are used to ensure training stability. Finally, the predicted values of clock skew, maximum latency and buffer number are output through global pooling layers and fully connected layers.
7. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that: Graph neural networks employ a three-layer message passing mechanism, with each layer carefully designed to effectively extract and pass feature information. The node feature update uses the following formula: in, For the first Layer nodes Features , For the first The trainable weight matrix of the layer, It is a ReLU activation function. For nodes The set of neighboring nodes, The edge feature transformation function is implemented using a two-layer multilayer perceptron (MLP).
8. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that: In lightly loaded areas, a binary chain structure is used, reducing the total wiring length cost: in, Indicates the current region. The Manhattan distance between adjacent buffers. Indicates the current region The total wiring cost is the sum of the Manhattan distances of all adjacent buffers in the binary chain; The heavy-load region adopts a standard quadtree structure, and the skew control target is represented as: in, Indicates the current region. This represents the maximum skewness of a quadtree node, which is the difference between the maximum and minimum delays from the root node to a leaf node. In a quadtree, from the root node to... Node clock latency, This represents the clock delay difference from the root node to different leaf nodes in the quadtree. The maximum clock skew is calculated by taking the two leaf nodes with the largest clock delay difference.
9. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 1, characterized in that: In step S6; The optimization objective of sparse mesh integration is based on the minimum Steiner tree theory, ensuring that the root nodes of all subtrees are guaranteed. Minimize the total mesh wiring length while ensuring connectivity in the mesh graph: in Represents the set of edges in a sparse grid. Representing an edge The physical length.
10. The method for synthesizing a GNN-guided hierarchical H-tree low-skew clock tree according to claim 9, characterized in that: The solution to the minimum Steiner tree problem employs an improved geometric algorithm, treating the root node of the subtree as a terminal point that must be connected, and the grid intersection as a candidate Steiner point. This improved geometric algorithm first constructs a complete graph between terminal points, using Manhattan distance to calculate edge weights; then, it generates a minimum spanning tree on the complete graph; next, it replaces each edge in the minimum spanning tree with the shortest path in the grid graph; finally, it adjusts the Steiner point positions through local optimization techniques to eliminate redundant connections and obtain a connection topology with the minimum total length.