Method and device for positioning failure address of memory
By using the automatic failure address conversion module, the failure address of the SRAM can be directly output by utilizing the start address, end address of the memory and the pattern type of the test vector. This solves the problem of not being able to directly locate the failure address in the existing technology and improves the testing efficiency.
Patent Information
- Application Number
- CN202511577223.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-06
AI Technical Summary
Existing technologies can only obtain the failure cycle number after SRAM functional testing, but cannot directly output the failure address. Secondary analysis is required to locate the failure address, making the location process cumbersome.
A method and apparatus for locating memory failure addresses are provided. The failure address is automatically converted into a failure address by an automatic failure address conversion module, which uses the memory's start address, end address, test vector pattern type, and test result file.
This allows for the direct output of failure addresses after functional testing, simplifying the failure address location process, avoiding the hassle of secondary analysis, and improving testing efficiency.
Smart Images
Figure CN121483350A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of conductor integrated circuit manufacturing, and in particular to a method for locating memory failure addresses. This invention also relates to an apparatus for locating memory failure addresses. Background Technology
[0002] With the development of integrated circuit technology, chip functions are becoming increasingly powerful, and the requirements for testing are also becoming more stringent. In SRAM functional testing, test vectors come in different types, such as Scan, March_6N, and DataRetention. The V93K test platform can quickly generate the corresponding logic test vectors, offering advantages such as ease of use, strong test program portability, and short development cycles.
[0003] like Figure 1 As shown, the first type of test vector is Scan. Figure 1 The diagram shows four operation vectors, denoted as operation 0, operation 1, operation 2, and operation 3, respectively; each of the four operation vectors operates on a memory cell from a start address to an end address. Figure 1 In this example, the starting address is Address0, the ending address is Addressn, and there are a total of n+1 addresses. Operation 0 performs a write operation (W0) on the memory cells at each address; operation 1 performs a read operation (R0) on the memory cells at each address; operation 2 performs a write operation (W1) on the memory cells at each address; and operation 3 performs a read operation (R1) on the memory cells at each address. In other embodiments, the test can also be performed cyclically according to the settings of operations 0 to 2.
[0004] like Figure 2 As shown, the second type of test vector is March_6N. Figure 2 The diagram shows four operation vectors, denoted as operation 0, operation 1, operation 2, and operation 3. Operation 0 operates on the memory cells at each address with W0; operation 1 operates on the memory cells at each address with R0W1, where R0W1 represents reading 0 and writing 1, i.e., reading 0 followed by writing 1; operation 2 operates on the memory cells at each address with R1W0, where R1W0 represents reading 1 and writing 0, i.e., reading 1 followed by writing 0; operation 3 operates on the memory cells at each address with R0. In other embodiments, operation 1 and operation 2 can be iterated multiple times between operation 0 and operation 3.
[0005] like Figure 3The third type of test vector is Data Rention, as shown in FIG. 1C. Figure 3 The m operation vectors are shown in FIG. 1A, as shown by arrows in the frame lines 0, 1, 2, 3, and operation m. Operation 0 is also indicated by a label 101a, operation 1 is also indicated by a label 101b, and operation m is also indicated by a label 101c. The operation vectors are generated by a test vector generator 100. Figure 3 As shown in FIG. 1B, the address of operation 0 changes from Address0 to Addressn, and the address of adjacent operation 1 changes from Addressn to Address0.
[0006] As shown in FIG. 1C, the third type of test vector is Data Rention. Figure 4 As shown in FIG. 1C, the third type of test vector is Data Rention. Figure 3 As shown in FIG. 1C, the third type of test vector is Data Rention.
[0007] Operation 1 follows operation 0, and each operation in the operation vector of operation 1 is an R0 operation, and the value of cycle number increases with the decrease of the address.
[0008] Operation m is an R0 / R1 operation, where R0 / R1 represents R0 or R1, and the specific value is determined according to m.
[0009] After the functional test is completed, the fail cycle number b is output, and it can be seen that the fail cycle number b corresponds to a size of 2n and a corresponding address of Address1. In the existing method, after the functional test is completed, only the value of the fail cycle number b can be obtained, and the fail address Address1 cannot be output. In order to obtain the fail address Address1, secondary analysis is required, and the intermediate positioning of the electrical address in such a failure analysis is troublesome.
[0010] As can be seen from the above, the existing method can only obtain the pass / fail result and the cycle number of the fail vector in actual testing, and subsequent analysis of the output fail cycle number (Fail cycle number) is required to obtain the fail electrical address. As shown in FIG. 1D, the existing method can only obtain the pass / fail result and the cycle number of the fail vector in actual testing, and subsequent analysis of the output fail cycle number (Fail cycle number) is required to obtain the fail electrical address. Figure 3As shown, n+1 electrical Address needs to be operated, such as W0 / R0 / W1 / R1 operation according to the address from small to large or from large to small, all address cycle once is recorded as an operation, Figure 3 As shown, the logic test pattern is generated from operation 0 to operation m, and the cycle number is increased from 0, operation 0 to operation m is executed, and it is assumed that fail occurs at cycle number b, the existing algorithm can only output fail cycle number b, and secondary analysis is required to correspond to fail electrical address 1. In such failure analysis, it is troublesome to locate the electrical address, therefore, how to directly output the fail electrical address becomes extremely important. Figure 4 SUMMARY
[0011] The technical problem to be solved by the present application is to provide a method for locating a memory failure address, which directly outputs the failure address.
[0012] To solve the above technical problem, the method for locating a memory failure address provided by the present application comprises:
[0013] Step one, performing functional test on the memory according to the selected test vector and outputting a test result file, wherein the test result file includes one or more failure cycle number.
[0014] Step two, providing a failure address automatic conversion module, inputting the start address and end address of the memory, the pattern type of the test vector and the test result file into the failure address automatic conversion module, and obtaining the failure address corresponding to each failure cycle number according to the address corresponding relationship in the cycle number of the pattern of the test vector.
[0015] Step three, outputting the failure address.
[0016] Further improvement is that the memory includes SRAM.
[0017] Further improvement is that the test vector includes a plurality of operation vectors.
[0018] Each of the operation vectors continuously operates on each memory cell from the start address to the end address or from the end address to the start address.
[0019] Further improvement is that the operation vector includes a write 0 vector, a read 0 vector, a write 1 vector and a read 1 vector.
[0020] The function test is performed in a cycle of the write-0 vector, the read-0 vector, the write-1 vector and the read-1 vector.
[0021] Further improvement is that the operation vectors include a write-0 vector, a read-0 plus write-1 vector, a read-1 plus write-1 vector and a read-0 vector, the first operation vector uses the write-0 vector and the last operation vector uses the read-0 vector, and between the first operation vector and the last operation vector, the read-0 plus write-1 vector and the read-1 plus write-1 vector are performed in a cycle.
[0022] Further improvement is that in the test vector, each operation corresponds to a cycle number, and the cycle number increases in sequence according to the order of the operations.
[0023] Further improvement is that the test result file includes a failure cycle number log text recording the failure cycle number.
[0024] To solve the above technical problems, the device for locating the failure address of the memory provided by the application includes: a failure address automatic conversion module, which is used to obtain the failure address corresponding to each failure cycle number according to the start address and the end address of the memory, the pattern type of the test vector and the test result file, and according to the cycle number and address correspondence in the pattern of the test vector. The interface of the failure address automatic conversion module includes:
[0025] A first input box is used to input the start address of the memory.
[0026] A second input box is used to input the end address of the memory device.
[0027] A third selection box is used to select the pattern type of the test vector.
[0028] A file selection button is used to input the test result file, and the test result file is obtained by performing a function test on the memory according to the selected test vector, and the test result file includes more than one failure cycle number.
[0029] A running button is used to control the conversion of each failure cycle number to the failure address, and the failure address automatic conversion module obtains the failure address corresponding to each failure cycle number according to the cycle number and address correspondence in the pattern of the test vector.
[0030] An output button is used to control the output of the failure address.
[0031] Further improvement is that the memory includes an SRAM.
[0032] Further improvement is that the test vector comprises a plurality of operation vectors.
[0033] Each of the operation vectors continuously operates on the memory cells of the memory from the start address to the end address or from the end address to the start address.
[0034] Further improvement is that the operation vectors comprise a write 0 vector, a read 0 vector, a write 1 vector and a read 1 vector.
[0035] The function test is performed in cycles according to the write 0 vector, the read 0 vector, the write 1 vector and the read 1 vector.
[0036] Further improvement is that the operation vectors comprise a write 0 vector, a read 0 plus write 1 vector, a read 1 plus write 1 vector and a read 0 vector, the first operation vector uses the write 0 vector and the last operation vector uses the read 0 vector, and between the first operation vector and the last operation vector, the read 0 plus write 1 vector and the read 1 plus write 1 vector are performed in cycles.
[0037] Further improvement is that in the test vector, each operation corresponds to a cycle number, and the cycle numbers are sequentially increased according to the order of the operations.
[0038] Further improvement is that in the test result file, the text storing each of the failure cycle numbers is a failure cycle number log text.
[0039] The present application is provided with a failure address automatic conversion module, which can automatically obtain the cycle number and address correspondence in the pattern of the test vector and can directly output the failure address corresponding to each failure cycle number according to the cycle number and address correspondence in the pattern of the test vector by inputting the start address and end address of the memory, the pattern type of the test vector and the test result file after the function test is finished, thus eliminating the trouble caused by the need for secondary analysis to correspond to the failure address in the prior art. Therefore, the present application can directly output the failure address without secondary analysis on the basis of the failure cycle number obtained in the function test, which is simple and convenient. BRIEF DESCRIPTION OF DRAWINGS
[0040] The present application will be further described in detail below in combination with the drawings and specific embodiments:
[0041] Figure 1 is a schematic diagram of the first test vector in the function test of the prior SRAM;
[0042] Figure 2is a schematic diagram of the second test vector in the functional test of the existing SRAM;
[0043] Figure 3 is a schematic diagram of the third test vector in the functional test of the existing SRAM;
[0044] Figure 4 is Figure 3 is a logic test pattern formed by expanding the third test vector in the functional test of the existing SRAM shown in the figure;
[0045] Figure 5 is a flow chart of the method for locating the failure address of the memory according to the embodiment of the present application;
[0046] Figure 6 is an interface diagram of the failure address automatic conversion module in the device for locating the failure address of the memory according to the embodiment of the present application;
[0047] Figure 7A is an interface diagram of the failure address automatic conversion module when the pattern type of the test vector is input during the conversion of the failure cycle number obtained by the functional test using the first test vector according to the method for locating the failure address of the memory;
[0048] Figure 7B is a failure address file obtained by converting the failure cycle number obtained by the functional test using the first test vector according to the method for locating the failure address of the memory;
[0049] Figure 8A is a failure cycle number log text obtained by the functional test using the second test vector according to the method for locating the failure address of the memory;
[0050] Figure 8B is an interface diagram of the failure address automatic conversion module when the pattern type of the test vector is input during the conversion of the failure cycle number obtained by the functional test using the second test vector according to the method for locating the failure address of the memory;
[0051] Figure 8C is a failure address file obtained by converting the failure cycle number obtained by the functional test using the second test vector according to the method for locating the failure address of the memory;
[0052] Figure 9A is a failure cycle number log text obtained by the functional test using the third test vector according to the method for locating the failure address of the memory;
[0053] Figure 9Bis the interface diagram of the fail address automatic conversion module when the pattern type input of the test vector is carried out in the conversion process of the fail cycle number obtained by the function test using the third test vector in the method for positioning the memory fail address of the embodiment of the present application;
[0054] Figure 9C is the fail address file obtained by the conversion of the fail cycle number obtained by the function test using the third test vector in the method for positioning the memory fail address of the embodiment of the present application. DETAILED DESCRIPTION
[0055] The embodiment of the present application can realize the direct conversion of Fail cycle number b into fail bit electrical address. The function test is executed according to the existing test method, and the Fail cycle number is output to the text log. As shown in the figure, the Start Address and the Stop Address corresponding to the input test are selected, the corresponding PatternType is selected, the Fail cycle number log text is imported by clicking the "file selection" button, then the "run" button is clicked, the Fail cycle number information in the text is converted into the corresponding FailAddress, and finally the "result export" button is clicked to output the converted result. Figure 6
[0056] In the embodiment of the present application, firstly, the function test is run to obtain the Fail cycle number.
[0057] Then, the Start Address and the Stop Address are input, the Pattern Type is selected, the Fail cycle number log file is imported, and the Fail cycle number is converted into the Fail Address by running the tool;
[0058] Then, the Fail Address result is output log.
[0059] The output Fail Address values in the above-mentioned Figure 7B 、 Figure 8C and Figure 9C are consistent with the electrical address calculated by the result analysis in each example of the SRAM chip measured by using the Scan pattern of the V93K test machine, which proves that the tool is reliable and the output result is correct.
[0060] The application is described in detail above with specific examples, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should be considered as within the scope of the application.
Claims
1. A method for locating a memory failure address, characterized in that, include: Step 1: Perform functional tests on the memory according to the selected test vector and output the test result file. The test result file includes one or more failure cycle numbers. Step 2: Provide an automatic failure address conversion module. Input the start address and end address of the memory, the pattern type of the test vector, and the test result file into the automatic failure address conversion module. The automatic failure address conversion module obtains the failure address corresponding to each failure loop number according to the correspondence between the loop number and the address in the pattern of the test vector. Step 3: Output the failed address.
2. The method for locating the memory failure address as described in claim 1, characterized in that: The memory includes SRAM.
3. The method for locating the memory failure address as described in claim 2, characterized in that: The test vector includes multiple operation vectors; Each of the operation vectors operates consecutively on the memory cells of each of the memories from the start address to the end address or from the end address to the start address.
4. The method for locating the memory failure address as described in claim 3, characterized in that: The operation vectors include a write 0 vector, a read 0 vector, a write 1 vector, and a read 1 vector; The functional test is performed in a loop according to the write 0 vector, the read 0 vector, the write 1 vector, and the read 1 vector.
5. The method for locating the memory failure address as described in claim 3, characterized in that: The operation vectors include a write 0 vector, a read 0 plus write 1 vector, a read 1 plus write 1 vector, and a read 0 vector. The first operation vector uses the write 0 vector, and the last operation vector uses the read 0 vector. The read 0 plus write 1 vector and the read 1 plus write 1 vector are performed cyclically between the first operation vector and the last operation vector.
6. The method for locating the memory failure address as described in claim 3, characterized in that: In the test vector, each operation corresponds to a loop count number, and the loop count number increases sequentially according to the order in which the operations are performed.
7. The method for locating the memory failure address as described in claim 1, characterized in that: The test result file includes a failure cycle number log text that records the failure cycle number.
8. A device for locating a memory failure address, characterized in that, include: The automatic failure address conversion module is used to obtain the failure address corresponding to each failure cycle number based on the start address, end address, pattern type of the test vector, and test result file of the memory, and according to the correspondence between the cycle number and address in the pattern of the test vector. The interface of the automatic address conversion module includes: The first input box is used to input the starting address of the memory; The second input box is used to input the end address of the storage device; The third selection box is used to select the pattern type of the test vector; The file selection button is used to input the test result file; the test result file is obtained by performing functional tests on the memory according to the selected test vector, and the test result file includes one or more failure cycle numbers; A run button is used to control the conversion of each failure cycle number to the failure address. The failure address automatic conversion module obtains the failure address corresponding to each failure cycle number according to the correspondence between the cycle number and the address in the pattern of the test vector. An output button is used to control the output of the failed address.
9. The apparatus for locating the fault address of a memory as described in claim 8, characterized in that: The memory includes SRAM.
10. The apparatus for locating the failure address of a memory as described in claim 8, characterized in that: The test vector includes multiple operation vectors; Each of the operation vectors operates consecutively on the memory cells of each of the memories from the start address to the end address or from the end address to the start address.
11. The apparatus for locating the fault address of a memory as described in claim 10, characterized in that: The operation vectors include a write 0 vector, a read 0 vector, a write 1 vector, and a read 1 vector; The functional test is performed in a loop according to the write 0 vector, the read 0 vector, the write 1 vector, and the read 1 vector.
12. The apparatus for locating the fault address of a memory as described in claim 10, characterized in that: The operation vectors include a write 0 vector, a read 0 plus write 1 vector, a read 1 plus write 1 vector, and a read 0 vector. The first operation vector uses the write 0 vector, and the last operation vector uses the read 0 vector. The read 0 plus write 1 vector and the read 1 plus write 1 vector are performed cyclically between the first operation vector and the last operation vector.
13. The apparatus for locating the failure address of a memory as described in claim 10, characterized in that: In the test vector, each operation corresponds to a loop count number, and the loop count number increases sequentially according to the order in which the operations are performed.
14. The apparatus for locating the failure address of a memory as described in claim 8, characterized in that: The text storing the failure cycle number in the test result file is the failure cycle number log text.