Method for detecting channel associated clock and routing equipment
By generating periodic trigger signals in the chassis router system and using the local reference clock domain for counting, the problem of interference with the in-line clock signal is solved, achieving high-precision and fast-response stability detection, reducing hardware costs, and improving system reliability.
Patent Information
- Application Number
- CN202511569751.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-29
- Publication Date
- 2026-02-06
AI Technical Summary
In a chassis router system, the clock signal associated with the circuit is prone to interference at the moment the board is powered on and when it is plugged in or unplugged, which can cause clock jitter and frequency drift, affecting the reliability of data transmission.
The service board receives the clock signal sent by the main control board, generates a periodic trigger signal, and uses the local reference clock domain to count and determine whether the clock signal is abnormal, thus achieving stability detection without additional hardware circuitry.
It achieves high-precision and fast-response stability detection of the in-path clock signal, reduces hardware costs, and improves system reliability.
Smart Images
Figure CN121485889A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of communication technology, and in particular to a method and routing device for detecting a clock along the path. Background Technology
[0002] In a chassis router system, the master controller and daughter cards communicate and are managed via a proprietary LVDS high-speed bus. The accompanying clock signal serves as the synchronization basis for high-speed proprietary bus data transmission, and its frequency and phase stability directly affect system performance. However, in practical applications, interference often occurs in the accompanying clock signal at the moment of power-on and during insertion / removal of the board, manifesting as large clock jitter and frequency drift. These problems can lead to bit errors or communication interruptions during data transmission, thereby reducing the overall reliability of the system. Summary of the Invention
[0003] To overcome the problems existing in related technologies, this specification provides a method and routing device for detecting in-circuit clocks.
[0004] According to a first aspect of the embodiments of this specification, a method for detecting an accompanying clock is provided, the method comprising: The service board receives the on-path clock signal sent by the main control board and generates a periodic trigger signal based on the on-path clock signal; The periodic trigger signal is sent to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. Determine whether there is any abnormality in the corresponding accompanying clock signal based on the obtained local reference clock counts for several cycles.
[0005] The step of generating a periodic trigger signal based on the accompanying clock signal includes: The received clock signal is counted by a clock signal counter, and a periodic trigger signal is generated based on the first count result.
[0006] Wherein, the step of making the local reference clock domain use the received adjacent periodic trigger signals as the statistical period includes: This enables the local reference clock domain to acquire the rising edge pulse of the adjacent periodic trigger signal after receiving it, and to use the time period of the rising edge pulse of the adjacent periodic trigger signal as the statistical period.
[0007] This includes obtaining local reference clock counts for several statistical periods, including: The local reference clock crystal oscillator of each statistical period is counted a second time by a local reference clock counter, and the local reference clock count of each statistical period is obtained based on the second count result.
[0008] The step of determining whether the corresponding accompanying clock signal is abnormal based on the acquired local reference clock counts over several cycles includes: Determine whether the count of each local reference clock falls within a preset range. If so, then the corresponding accompanying clock signal is confirmed to be normal; If it does not belong to the category, then the accompanying clock signal is determined to be abnormal.
[0009] As can be seen from the above embodiments, a statistical period is formed by adjacent periodic trigger signals, and the presence of abnormalities in the accompanying clock signal is determined by monitoring whether the local reference clock count within each statistical period falls within a preset range. This eliminates the need for additional dedicated hardware circuitry and can be achieved with only lightweight logic resources, greatly reducing hardware costs.
[0010] According to a second aspect of the embodiments of this specification, a routing device is provided, the routing device comprising: The receiving module is used by the service board to receive the accompanying clock signal sent by the main control board and generate periodic trigger signals according to the accompanying clock signal. The processing module is used to send the periodic trigger signal to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. The judgment module determines whether there is any abnormality in the corresponding accompanying clock signal based on the acquired local reference clock counts over several cycles.
[0011] Specifically, the receiving module is used to perform a first count on the received accompanying clock signal using an accompanying clock signal counter, and generate a periodic trigger signal based on the first count result.
[0012] The processing module is specifically configured to enable the local reference clock domain to acquire the rising edge pulse of the adjacent periodic trigger signal after receiving the adjacent periodic trigger signal, and to use the time period of the rising edge pulse of the adjacent periodic trigger signal as the statistical period.
[0013] Specifically, the processing module is used to perform a second count on the local reference clock crystal oscillator of each statistical period using a local reference clock counter, and obtain the local reference clock count for each statistical period based on the second count result.
[0014] Specifically, the judgment module is used to determine whether the count of each local reference clock belongs to a preset range value; If so, then the corresponding accompanying clock signal is confirmed to be normal; If it does not belong to the category, then the accompanying clock signal is determined to be abnormal.
[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0017] Figure 1 This is a logical schematic diagram illustrating a method for detecting an accompanying clock according to an exemplary embodiment of this specification.
[0018] Figure 2 This is a schematic diagram of a network architecture illustrated in this specification according to an exemplary embodiment. Detailed Implementation
[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.
[0020] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0021] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0022] Currently, to monitor and adjust the accompanying clock signal, a phase-locked loop (PLL) is required. The PLL compares the phase difference between the clock signal and a reference signal and uses a feedback mechanism to dynamically adjust the clock signal to maintain stability. However, this method requires a PLL circuit, has a long detection time, and high hardware costs. Therefore, it does not meet the requirements for some specific application scenarios.
[0023] The inventors discovered through research that if the accompanying clock is stable, its frequency remains relatively constant with a stable reference clock over a certain period of time. Any significant drift or jitter in frequency indicates instability in the accompanying clock.
[0024] Therefore, in order to solve the technical problems in the prior art, embodiments of this disclosure provide a method for detecting an accompanying clock, such as... Figure 1 As shown, the method includes: The S101 service board receives the on-path clock signal sent by the main control board and generates a periodic trigger signal based on the on-path clock signal. S102 sends the periodic trigger signal to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. S103 determines whether there is an abnormality in the corresponding accompanying clock signal based on the acquired local reference clock counts for several cycles.
[0025] like Figure 2 As shown, in this embodiment, the service board (service sub-card) receives the accompanying clock signal sent by the main control board. Under normal circumstances, the main control board and the service board can be linked through the backplane (in other embodiments, there may also be a scheme where the main control board and the service board are directly connected).
[0026] In this embodiment, an FPGA is provided on the service board. This embodiment uses the FPGA to implement the on-path clock signal counter. Specifically, after the service board receives the on-path clock signal from the main control board, the on-path clock signal drives the on-path clock signal counter to perform the first count and generate a periodic trigger signal (denoted as trigger).
[0027] The detection duration is determined by the bit width of cnt0 (e.g., a 5-bit counter corresponds to 32 cycles).
[0028] In this embodiment, the service board has an independent clock source (i.e., a local reference clock) to provide a time base for the service board. Its features include independence, high accuracy, and synchronization capability, and it can support protocols such as IEEE 1588 (PTP), NTP / SNTP, SyncE, and BITS / E1.
[0029] The FPGA also implements a local reference clock counter, and the FPGA synchronizes the periodic trigger signal to the local reference clock domain (REF_CLK) of the service daughter card and extracts the rising edge pulse (trigger_1p).
[0030] In this embodiment, a high-precision crystal oscillator (OSC) in the service board provides a reference clock for the entire board of chips. When the FPGA receives an adjacent trigger, the time it takes to receive the adjacent trigger is used as the statistical period. For example, the number of REF_CLK cycles between two trigger_1p events is counted.
[0031] In step S103, the main consideration is whether the counting result of the local reference clock counter matches the preset range value within the statistical period. Generally, when the accompanying clock is normal, the local reference clock frequency used for counting is made consistent with the accompanying clock frequency through frequency division inside the sub-card. Then, within the set time range, the count of cnt0 (counting duration of the accompanying clock signal counter) and cnt1 (local reference clock counter) should have a stable count value. If the actual cnt1 exceeds the expected range by 2-3 cycles, it is determined that the frequency deviation is too large.
[0032] In one example, suppose the preset range is set to 30-32. Suppose the local reference clock count for the Nth cycle is 31. It can be seen that 31 belongs to the preset range of 30-32. Therefore, the accompanying clock signal status corresponding to the local reference clock count for the Nth cycle is normal. As another example, suppose the local reference clock count for the (N+1)th cycle is 28. It can be seen that 28 exceeds the preset range of 30-32. Therefore, it can be determined that the accompanying clock signal status corresponding to the local reference clock for the (N+1)th cycle is abnormal.
[0033] In this embodiment, a third counter can also be set in the FPGA to realize stability verification. For example, the third counter (cnt3) accumulates the number of consecutive detections that meet the error range (8 times), and outputs a stability flag (detect_ok) after reaching the threshold. Error range: By setting the allowable range of cnt1 (e.g., 30~32), a tolerance of ±6.25% instantaneous deviation is achieved. Combined with the cumulative verification mechanism, single or a few periodic anomalies caused by noise or transient jitter are ignored, improving the anti-interference capability; at the same time, it ensures that the clock remains stable for a period of time (8 measurement cycles), improving the reliability of the detection results.
[0034] As can be seen from the above embodiments, this disclosure achieves high-precision and fast-response external clock stability detection without the need for complex circuitry through a dual-clock domain collaborative counting and dynamic error judgment mechanism. This can be widely applied in fields such as communications and embedded systems. Specifically, a statistical period is formed by adjacent periodic trigger signals, and the presence of anomalies in the accompanying clock signal is determined by monitoring whether the local reference clock count within each statistical period falls within a preset range. This eliminates the need for additional hardware circuitry and requires only lightweight logic resources, significantly reducing hardware costs.
[0035] Based on the above method embodiments, this disclosure also provides a routing device, the routing device comprising: The receiving module is used by the service board to receive the accompanying clock signal sent by the main control board and generate periodic trigger signals according to the accompanying clock signal. The processing module is used to send the periodic trigger signal to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. The judgment module is used to determine whether there is any abnormality in the corresponding accompanying clock signal based on the acquired local reference clock counts for several cycles.
[0036] Specifically, the receiving module is used to perform a first count on the received accompanying clock signal using an accompanying clock signal counter, and generate a periodic trigger signal based on the first count result.
[0037] Specifically, the processing module is used to enable the local reference clock domain to acquire the rising edge pulse of the adjacent periodic trigger signal after receiving the adjacent periodic trigger signal, and to use the time period of the rising edge pulse of the adjacent periodic trigger signal as the statistical period.
[0038] Specifically, the processing module is used to perform a second count on the local reference clock crystal oscillator of each statistical period using a local reference clock counter, and obtain the local reference clock count for each statistical period based on the second count result.
[0039] Specifically, the judgment module is used to determine whether the count of each local reference clock belongs to a preset range value; If so, then the corresponding accompanying clock signal is confirmed to be normal; If it does not belong to the category, then the accompanying clock signal is determined to be abnormal.
[0040] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0041] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.
[0042] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.
[0043] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.
[0044] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.
Claims
1. A method for detecting an on-path clock, characterized in that, The method includes: The service board receives the on-path clock signal sent by the main control board and generates a periodic trigger signal based on the on-path clock signal; The periodic trigger signal is sent to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. Determine whether there is any abnormality in the corresponding accompanying clock signal based on the obtained local reference clock counts for several cycles.
2. The method according to claim 1, characterized in that, The generation of periodic trigger signals based on the accompanying clock signal includes: The received clock signal is counted by a clock signal counter, and a periodic trigger signal is generated based on the first count result.
3. The method according to claim 1, characterized in that, The step of making the local reference clock domain use the received adjacent periodic trigger signals as the statistical period includes: This enables the local reference clock domain to acquire the rising edge pulse of the adjacent periodic trigger signal after receiving it, and to use the time period of the rising edge pulse of the adjacent periodic trigger signal as the statistical period.
4. The method according to claim 1, characterized in that, Obtain local reference clock counts for several statistical periods, including: The local reference clock oscillator for each statistical period is counted a second time by a local reference clock counter, and the local reference clock count for each statistical period is obtained based on the second count result.
5. The method according to claim 1, characterized in that, Based on the acquired local reference clock counts over several cycles, determine whether the corresponding accompanying clock signal is abnormal, including: Determine whether the count of each local reference clock falls within a preset range. If so, then the corresponding accompanying clock signal is confirmed to be normal; If it does not belong to the category, then the accompanying clock signal is determined to be abnormal.
6. A routing device, characterized in that, The routing device includes: The receiving module is used by the service board to receive the accompanying clock signal sent by the main control board and generate periodic trigger signals according to the accompanying clock signal. The processing module is used to send the periodic trigger signal to the local reference clock domain so that the local reference clock domain uses the received adjacent periodic trigger signals as the statistical period and obtains the local reference clock count for several statistical periods. The judgment module determines whether there is any abnormality in the corresponding accompanying clock signal based on the acquired local reference clock counts over several cycles.
7. The routing device according to claim 6, characterized in that, The receiving module is specifically used to perform a first count on the received along-path clock signal using an along-path clock signal counter, and generate a periodic trigger signal based on the first count result.
8. The routing device according to claim 6, characterized in that, The processing module is specifically configured to enable the local reference clock domain to acquire the rising edge pulse of the adjacent periodic trigger signal after receiving the adjacent periodic trigger signal, and to use the time period of the rising edge pulse of the adjacent periodic trigger signal as the statistical period.
9. The routing device according to claim 6, characterized in that, The processing module is specifically used to perform a second count on the local reference clock crystal oscillator of each statistical period using a local reference clock counter, and obtain the local reference clock count for each statistical period based on the second count result.
10. The routing device according to claim 6, characterized in that, The judgment module is specifically used to determine whether the count of each local reference clock belongs to a preset range value; If so, then the corresponding accompanying clock signal is confirmed to be normal; If it does not belong to the category, then the accompanying clock signal is determined to be abnormal.