Frequency detection circuit, frequency detection method and image sensor

Abstract

The invention provides a frequency detection circuit, a frequency detection method and an image sensor, and the circuit comprises a frequency conversion module which receives a clock signal, and converts the clock frequency of the clock signal into an analog electric signal, so as to carry out the detection of the clock frequency; wherein the frequency conversion module comprises a resistance acquisition unit, and the resistance acquisition unit receives a clock signal and converts the clock frequency of the clock signal into a clock resistance signal so as to acquire an analog electric signal. According to the frequency detection circuit, the frequency detection method and the image sensor provided by the invention, the problem that the reference time needs to be provided by an additional crystal oscillator in the existing frequency detection scheme is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, in particular to a frequency detection circuit and method, and an image sensor. BACKGROUND

[0002] In a CMOS image sensor, a clock signal is an indispensable important component, but abnormal clock frequency can seriously affect the working state of the image sensor; therefore, in an image sensor with high safety and stability, a clock frequency detection circuit needs to be integrated. The traditional method is: the clock signal to be detected is connected as input to the counter, and the counting result of the counter in a fixed time is counted as output, the faster the clock frequency, the more the counter counts; however, the generation of the fixed time of the counter needs an additional crystal oscillator to provide, resulting in high circuit design overhead. Based on this, a frequency detection circuit independent of an additional crystal oscillator is provided, which is an urgent technical problem to be solved by those skilled in the art.

[0003] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a frequency detection circuit and method, and an image sensor, to solve the problem that the existing frequency detection scheme needs an additional crystal oscillator to provide a reference time.

[0005] To achieve the above object and other related objects, the present application provides a frequency detection circuit, which comprises:

[0006] A frequency conversion module receives a clock signal and converts the clock frequency of the clock signal into an analog electrical signal for clock frequency detection; wherein the frequency conversion module comprises a resistance acquisition unit, which receives the clock signal and converts the clock frequency of the clock signal into a clock resistance signal to obtain the analog electrical signal.

[0007] Optionally, the resistance acquisition unit includes a first transmission gate, a second transmission gate, a first MOSFET, a second MOSFET, a first capacitor, and a second capacitor. The input terminal of the first transmission gate is connected to the input terminal of the second transmission gate and serves as the access terminal of the resistance acquisition unit. The output terminal of the first transmission gate is connected to the first terminal of the first MOSFET and connected to a reference ground via the first capacitor. The first control terminal of the first transmission gate is connected to the control terminal of the second MOSFET and receives the clock signal. The second control terminal of the first transmission gate receives the inverted signal of the clock signal. The output terminal of the second transmission gate is connected to the first terminal of the second MOSFET and connected to a reference ground via the second capacitor. The first control terminal of the second transmission gate receives the inverted signal of the clock signal. The second control terminal of the second transmission gate is connected to the control terminal of the first MOSFET and receives the clock signal. The second terminals of the first MOSFET and the second MOSFET are connected to a reference ground.

[0008] Optionally, the frequency conversion module includes:

[0009] A voltage amplification unit is connected to the input terminal of the resistance acquisition unit, receives a first voltage signal, and amplifies the first voltage signal to obtain a second voltage signal;

[0010] A current generation unit, connected to the voltage amplification unit, generates a clock current signal based on the second voltage signal and the clock resistor signal and outputs it as the analog electrical signal.

[0011] Alternatively, the frequency conversion module may further include a Miller compensation unit connected between the resistance acquisition unit and the voltage amplification unit.

[0012] Optionally, the voltage amplification unit includes a first operational amplifier, a third MOSFET, and a fourth MOSFET. The first input terminal of the first operational amplifier is connected to a first voltage signal, and the second input terminal of the first operational amplifier is connected to the access terminal of the resistance acquisition unit. The output terminal of the first operational amplifier is connected to the control terminal of the third MOSFET and also to the access terminal of the resistance acquisition unit. The first terminal of the third MOSFET is connected to the second terminal of the fourth MOSFET, and the second terminal of the third MOSFET is connected to a power supply voltage signal. The control terminal of the fourth MOSFET is connected to a first bias signal, and the first terminal of the fourth MOSFET is connected to the access terminal of the resistance acquisition unit. When the frequency conversion module further includes a Miller compensation unit, the output terminal of the first operational amplifier is connected to the access terminal of the resistance acquisition unit via the Miller compensation unit.

[0013] The current generation unit includes a fifth MOSFET and a sixth MOSFET. The control terminal of the fifth MOSFET is connected to the output terminal of the first operational amplifier. The first terminal of the fifth MOSFET is connected to the second terminal of the sixth MOSFET. The second terminal of the fifth MOSFET is connected to the power supply voltage signal. The control terminal of the sixth MOSFET is connected to the first bias signal. The first terminal of the sixth MOSFET serves as the output terminal of the current generation unit.

[0014] Optionally, the frequency conversion module further includes:

[0015] A voltage generation unit, connected to the current generation unit, is used to convert the clock current signal into a clock voltage signal and replace the clock current signal as the analog electrical signal output.

[0016] Optionally, the voltage generation unit is implemented using a first resistor.

[0017] Optionally, the positions of the first resistor and the resistance acquisition unit are interchanged, wherein the current generation unit generates a fixed current signal based on the second voltage signal and the first resistance signal, and generates the clock voltage signal through the resistance acquisition unit.

[0018] Optionally, the frequency detection circuit further includes:

[0019] The signal quantization module, connected to the frequency conversion module, quantizes the analog electrical signal into a digital signal without using an additional clock signal.

[0020] Optionally, when the analog electrical signal includes a clock current signal, the signal quantization module includes:

[0021] The charging and discharging unit is connected to the frequency conversion module. It performs a charging operation based on the difference between a first current signal and a second current signal in a first time period and a discharging operation based on the second current signal in a second time period to obtain a capacitor voltage signal. The second current signal is the sum of the clock current signal and the third current signal.

[0022] The comparison output unit is connected to the charging and discharging unit. It obtains an output signal by comparing the capacitor voltage signal and the reference voltage signal, and quantizes the clock current signal based on the duty cycle of the output signal.

[0023] Optionally, the charging and discharging unit includes:

[0024] The first current section is used to generate the first current signal for charging operation;

[0025] The clock current section is connected to the frequency conversion module and is used to transmit the clock current signal for discharge operation;

[0026] The third current section is used to generate the third current signal for discharge operation;

[0027] The charge / discharge control section is connected to the first current section, the clock current section, and the third current section, respectively, and is used to simultaneously start the charging operation and the discharging operation in a first time period under the control of the output signal, and to turn off the charging operation and continue the discharging operation in a second time period.

[0028] Optionally, the first current section includes a seventh MOSFET and an eighth MOSFET. The control terminal of the seventh MOSFET is connected to a first control voltage signal, the first terminal of the seventh MOSFET is connected to the second terminal of the eighth MOSFET, the second terminal of the seventh MOSFET is connected to a power supply voltage signal, the control terminal of the eighth MOSFET is connected to a first bias voltage signal, and the first terminal of the eighth MOSFET serves as the current supply terminal of the first current section.

[0029] And / or, the clock current section includes a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, and a twelfth MOSFET. The control terminal of the ninth MOSFET is connected to the control terminal of the tenth MOSFET and connected to a second bias signal. The first terminal of the ninth MOSFET is connected to the output terminal of the frequency conversion module. The second terminal of the ninth MOSFET is connected to the first terminal of the eleventh MOSFET. The first terminal of the tenth MOSFET serves as the current supply terminal of the clock current section. The second terminal of the tenth MOSFET is connected to the first terminal of the twelfth MOSFET. The control terminal of the eleventh MOSFET is connected to the control terminal of the twelfth MOSFET and connected to the first terminal of the ninth MOSFET. The second terminals of the eleventh MOSFET and the twelfth MOSFET are connected to a reference ground.

[0030] And / or, the third current section includes a thirteenth MOSFET and a fourteenth MOSFET, the control terminal of the thirteenth MOSFET is connected to a second bias signal, the first terminal of the thirteenth MOSFET serves as the current supply terminal of the third current section, the second terminal of the thirteenth MOSFET is connected to the first terminal of the fourteenth MOSFET, the control terminal of the fourteenth MOSFET is connected to a second control signal, and the second terminal of the fourteenth MOSFET is connected to a reference ground;

[0031] And / or, the charge / discharge control section includes a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, and a third capacitor. The control terminal of the fifteenth MOSFET is connected to the output signal. The first terminal of the fifteenth MOSFET is connected to the first terminal of the sixteenth MOSFET. The second terminal of the fifteenth MOSFET is connected to the second terminal of the seventeenth MOSFET and connected to the supply terminal of the first current section. The control terminal of the sixteenth MOSFET is connected to its first terminal. The second terminal of the sixteenth MOSFET is connected to reference ground. The control terminal of the seventeenth MOSFET is connected to the inverted signal of the output signal. The first terminal of the seventeenth MOSFET is connected to the first terminal of the third capacitor and connected to the clock current section and the supply terminal of the third current section. The first terminal of the third capacitor serves as the output terminal of the charge / discharge unit, and the second terminal of the third capacitor is connected to reference ground.

[0032] Optionally, the charging and discharging unit further includes a voltage control providing section for providing a first voltage control signal to the first current section and a second voltage control signal to the third current section.

[0033] Optionally, the voltage control supply section includes a second operational amplifier, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a twenty-second MOSFET, a twenty-third MOSFET, and a second resistor. The first input terminal of the second operational amplifier is connected to a third voltage signal, the second input terminal of the second operational amplifier is connected to the first terminal of the second resistor, the output terminal of the second operational amplifier is connected to the control terminals of the eighteenth and nineteenth MOSFETs, the output terminal of the second operational amplifier is also connected to the first terminal of the second resistor and serves as the first output terminal of the voltage control supply section, the first terminal of the eighteenth MOSFET is connected to the second terminal of the twentyth MOSFET, the second terminal of the eighteenth MOSFET is connected to a power supply voltage signal, and the first terminal of the nineteenth MOSFET is connected to the twenty-first MOSFET. The second terminal of the S-transistor, the second terminal of the nineteenth MOSFET is connected to the power supply voltage signal, the control terminal of the twentieth MOSFET is connected to the control terminal of the eleventh MOSFET and connected to the first bias signal, the first terminal of the twentieth MOSFET is connected to the first terminal of the second resistor, the first terminal of the eleventh MOSFET is connected to the first terminal of the twelfth MOSFET and the control terminal of the thirteenth MOSFET and serves as the second output terminal of the voltage control supply section, the control terminal of the twelfth MOSFET is connected to the second bias signal, the second terminal of the twelfth MOSFET is connected to the first terminal of the thirteenth MOSFET, and the second terminal of the thirteenth MOSFET and the second terminal of the second resistor are connected to reference ground; or, the voltage control supply section further includes a Miller capacitor connected between the output terminal of the second operational amplifier and the first terminal of the second resistor.

[0034] Optionally, the comparison output unit includes a comparator, an inverter, and a D flip-flop. The first input terminal of the comparator is connected to a reference voltage signal, the second input terminal of the comparator is connected to the output terminal of the charging / discharging unit, the output terminal of the comparator is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the data terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock signal, and the output terminal of the D flip-flop serves as the output terminal of the comparison output unit.

[0035] Optionally, when a clock voltage signal is used to replace the clock current signal as the analog electrical signal, the signal quantization module further includes an input conversion unit connected between the frequency conversion module and the charging / discharging unit, for converting the clock voltage signal into the clock current signal.

[0036] Optionally, the input conversion unit includes:

[0037] The amplifier section is connected to the frequency conversion module and is used to amplify the clock voltage signal to obtain a fourth voltage signal;

[0038] The voltage-to-current conversion section, connected to the amplifier section, is used to convert the fourth voltage signal into the clock current signal;

[0039] Alternatively, the input conversion unit may further include a Miller compensation section connected between the amplifier section and the voltage-to-current conversion section.

[0040] Optionally, the amplifier section includes two operational amplifiers connected in a unity-gain negative feedback configuration; and / or, the voltage-to-current conversion section includes a 24th MOSFET, a 25th MOSFET, a 26th MOSFET, a 27th MOSFET, and a third resistor. The control terminal of the 24th MOSFET is connected to the control terminal of the 25th MOSFET and connected to the fourth voltage signal. The first terminal of the 24th MOSFET is connected to the second terminal of the 26th MOSFET, and the second terminal of the 24th MOSFET is connected to the power supply voltage signal. The first terminal of the 25th MOSFET is connected to the second terminal of the 27th MOSFET, and the second terminal of the 25th MOSFET is connected to the power supply voltage signal. The control terminal of the 26th MOSFET is connected to the control terminal of the 27th MOSFET and connected to the first bias signal. The first terminal of the 26th MOSFET is connected to the first terminal of the third resistor. The first terminal of the 27th MOSFET serves as the output terminal of the input conversion unit. The first terminal of the third resistor is connected to the output terminal of the amplifier section, and the second terminal of the third resistor is connected to reference ground. Wherein, when the input conversion unit includes a Miller compensation section, the first terminal of the third resistor is connected to the output terminal of the amplifier section via the Miller compensation section.

[0041] Optionally, the signal quantization module is implemented using a flash memory analog-to-digital converter, a successive approximation analog-to-digital converter, or a pipelined analog-to-digital converter.

[0042] The present invention also provides a frequency detection method, the frequency detection method comprising:

[0043] Convert the clock frequency of the clock signal into an analog electrical signal;

[0044] The analog electrical signal is quantized into a digital signal for clock frequency detection without using an additional clock signal.

[0045] The present invention also provides an image sensor, including a frequency detection circuit as described in any of the above embodiments.

[0046] As described above, the frequency detection circuit, frequency detection method, and image sensor of the present invention convert the clock frequency of the clock signal into a current signal or voltage signal in the analog domain before quantization, eliminating the need for an additional crystal oscillator to provide the main frequency, saving chip area, facilitating circuit integration, and reducing design costs. Attached Figure Description

[0047] Figure 1 The diagram shown is a schematic representation of the frequency detection circuit of this invention.

[0048] Figure 2 The diagram shown is a circuit diagram of the frequency conversion module of the present invention.

[0049] Figure 3 The diagram shown is a circuit schematic of the resistance acquisition unit of the present invention.

[0050] Figure 4 This is another circuit diagram of the frequency conversion module of the present invention.

[0051] Figure 5 The diagram shown is another circuit schematic of the frequency conversion module of the present invention.

[0052] Figure 6 The diagram shown is a circuit schematic of the signal quantization module of the present invention.

[0053] Figure 7 The diagram shown is a circuit diagram of the voltage control provision part of the present invention.

[0054] Figure 8 This is another circuit diagram of the signal quantization module of the present invention.

[0055] Figure 9 The diagram shown is another circuit schematic of the signal quantization module of the present invention.

[0056] Component designation explanation

[0057] 10. Frequency Detection Circuit

[0058] 100 Frequency Conversion Module

[0059] 110 Resistance Acquisition Unit

[0060] 120Voltage Amplification Unit

[0061] 130 Current Generating Unit

[0062] 140 Miller compensation units

[0063] 150 Voltage Generation Unit

[0064] 200 signal quantization module

[0065] 210 charge / discharge unit

[0066] 211 First Current Section

[0067] 212 Clock Current Section

[0068] 213 Third Current Section

[0069] 214 Charge and Discharge Control Section

[0070] 215 Pressure Control Supply Section

[0071] 220 Comparison Output Unit

[0072] 230 Input Conversion Unit

[0073] 231 Amplifier Section

[0074] 232 Voltage-to-current conversion section

[0075] 233 Miller compensation portion

[0076] 240 resistor string

[0077] 250 comparator array

[0078] 260 decoder Detailed Implementation

[0079] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0081] like Figure 1 As shown, this embodiment provides a frequency detection circuit 10, including a frequency conversion module 100, and further including a signal quantization module 200.

[0082] The frequency conversion module 100 receives the clock signal clk and converts the clock frequency fclk of the clock signal into an analog electrical signal for clock frequency detection. The analog electrical signal includes a current signal or a voltage signal. However, both current signals and voltage signals are related to the clock frequency. Therefore, the current signal is referred to as the clock current signal and the voltage signal is referred to as the clock voltage signal to avoid confusion with other current signals or other voltage signals mentioned below.

[0083] For analog electrical signals, including clock and current signals:

[0084] In one implementation, such as Figure 2 As shown, the frequency conversion module 100 includes a resistance acquisition unit 110, and further includes a voltage amplification unit 120 and a current generation unit 130, and even further includes a Miller compensation unit 140.

[0085] The resistance acquisition unit 110 receives the clock signal clk and converts the clock frequency fclk into a clock resistance signal Rclk to obtain the clock current signal (i.e., an analog electrical signal). In one example, such as Figure 3As shown, the resistance acquisition unit 110 includes a first transmission gate TG1, a second transmission gate TG2, a first MOSFET M1, a second MOSFET M2, a first capacitor C1, and a second capacitor C2. The input terminal of the first transmission gate TG1 is connected to the input terminal of the second transmission gate TG2 and serves as the access terminal of the resistance acquisition unit 110. The output terminal of the first transmission gate TG1 is connected to the first terminal of the first MOSFET M1 and connected to reference ground via the first capacitor C1. The first control terminal of the first transmission gate TG1 is connected to the control terminal of the second MOSFET M2 and receives the clock signal clk. The second control terminal of the first transmission gate TG1 receives the inverted signal clkb of the clock signal. The output terminal of the second transmission gate TG2 is connected to the first terminal of the second MOSFET M2 and connected to reference ground via the second capacitor C2. The first control terminal of the second transmission gate TG2 receives the inverted signal clkb of the clock signal. The second control terminal of the second transmission gate TG2 is connected to the control terminal of the first MOSFET M1 and receives the clock signal clk. The second terminals of the first MOSFET M1 and the second MOSFET M2 are connected to reference ground. Based on the amount of charge transferred per unit time, the clock resistance signal satisfies Formula 3. Where Rclk is the value of the clock resistor signal, fclk is the clock frequency of the clock signal, C1 is the value of the first capacitor, and C2 is the value of the second capacitor.

[0086] The voltage amplification unit 120 is connected to the input terminal of the resistance acquisition unit 110, receives the first voltage signal V1, and amplifies the first voltage signal V1 to obtain the second voltage signal V2. In one example, such as... Figure 2 As shown, the voltage amplification unit 120 includes a first operational amplifier AMP1, a third MOSFET M3, and a fourth MOSFET M4. The first input terminal of the first operational amplifier AMP1 is connected to a first voltage signal V1, and the second input terminal of the first operational amplifier AMP1 is connected to the access terminal of the resistor acquisition unit 110. The output terminal of the first operational amplifier AMP1 is connected to the control terminal of the third MOSFET M3 and also to the access terminal of the resistor acquisition unit 110. The first terminal of the third MOSFET M3 is connected to the second terminal of the fourth MOSFET M4, and the second terminal of the third MOSFET M3 is connected to the power supply voltage signal AVDD. The control terminal of the fourth MOSFET M4 is connected to a first bias signal Vb1, and the first terminal of the fourth MOSFET M4 is connected to the access terminal of the resistor acquisition unit 110. In the above example, the first operational amplifier AMP1 is a two-stage operational amplifier configured as a unity-gain negative feedback system. The closed-loop system gain of this two-stage operational amplifier satisfies Formula 1: V2 is the value of the second voltage signal, V1 is the value of the first voltage signal, A0 is the amplification factor of the two-stage operational amplifier, and β is the feedback coefficient. Since the voltage at the output terminal is completely fed back to the input terminal, β is 1. Furthermore, since the amplification factor A0 of the two-stage operational amplifier is very large, we can approximate formula two: In practical applications, in order to obtain an accurate voltage signal, the reference voltage signal provided by the bandgap reference circuit can be used as the first voltage signal V1.

[0087] The current generation unit 130 is connected to the voltage amplification unit 120, and generates a clock current signal Iclk based on the second voltage signal V2 and the clock resistance signal Rclk, which is then output as an analog electrical signal. In one example, such as Figure 2 As shown, the current generation unit 130 includes a fifth MOSFET M5 and a sixth MOSFET M6. The control terminal of the fifth MOSFET M5 is connected to the output terminal of the first operational amplifier AMP1, the first terminal of the fifth MOSFET M5 is connected to the second terminal of the sixth MOSFET M6, the second terminal of the fifth MOSFET M5 is connected to the power supply voltage signal AVDD, the control terminal of the sixth MOSFET M6 is connected to the first bias signal Vb1, and the first terminal of the sixth MOSFET M6 serves as the output terminal of the current generation unit 130. In the above example, the fifth MOSFET M5 and the sixth MOSFET M6, together with the third MOSFET M3 and the fourth MOSFET M4 in the voltage amplification unit 120, form a common-source, common-gate current mirror to achieve high mirror accuracy. Of course, other current mirror structures are also feasible; for example, the common-gate transistor can be removed, leaving only the common-source transistor, sacrificing accuracy for area savings. The aspect ratio of the third MOSFET M3 is the same as that of the fifth MOSFET M5. Therefore, the current mirror ratio of this common-source, common-gate current mirror is 1:1, meaning the output clock current signal is equal to the current flowing through the resistor acquisition unit 110. Based on Ohm's law, we obtain Formula 4: Iclk is the value of the clock current signal, and IRclk is the value of the current flowing through the resistor acquisition unit 110. Combining formulas two and three, we can obtain formula five: Thus, the conversion from frequency to current is completed. As can be seen from the above formula, the clock current signal Iclk is directly proportional to the clock frequency fclk of the clock signal.

[0088] Miller compensation unit 140 is connected between resistor acquisition unit 110 and voltage amplification unit 120 to compensate the frequency characteristics of the first operational amplifier AMP1 in voltage amplification unit 120. In this case, the output terminal of the first operational amplifier AMP1 in voltage amplification unit 120 is connected to the input terminal of resistor acquisition unit 110 via Miller compensation unit 140. In one example, Miller compensation unit 140 includes a Miller capacitor (not shown in the figure). Of course, in other examples, Miller compensation unit 140 also includes a compensation resistor (not shown in the figure). In this case, the Miller capacitor and the compensation resistor are connected in series between resistor acquisition unit 110 and voltage amplification unit 120.

[0089] For analog electrical signals, including clock voltage signals:

[0090] In one implementation, such as Figure 4 As shown, the frequency conversion module 100 includes not only the units described above, but also a voltage generation unit 150.

[0091] Voltage generation unit 150 is connected to current generation unit 130 and is used to convert clock current signal Iclk into clock voltage signal Vclk, and use clock voltage signal Vclk to replace clock current signal Iclk as analog electrical signal output. In one example, such as Figure 4 As shown, the voltage generation unit 150 is implemented using a first resistor R1. For example, the first end of the first resistor R1 is connected to the output terminal of the current generation unit 130 and serves as the output terminal of the voltage generation unit 150, while the second end of the first resistor R1 is connected to the reference ground. The clock current signal Iclk is converted into a clock voltage signal Vclk through the first resistor R1, satisfying formula six: Vclk=Iclk·R1=V1·R1·fclk·(C1+C2), where Vclk is the value of the clock voltage signal and R1 is the value of the first resistor. In this way, the conversion from frequency to voltage is completed. It can be seen from the above formula that the clock voltage signal Vclk is directly proportional to the clock frequency fclk of the clock signal.

[0092] In another implementation, such as Figure 5 As shown, the positions of the first resistor R1 and the resistor acquisition unit 110 are interchanged. At this time, the current generation unit 130 generates a fixed current signal based on the second voltage signal V2 and the first resistor signal, and generates a clock voltage signal Vclk through the resistor acquisition unit 110; wherein, the clock voltage signal Vclk satisfies Formula 7: Thus, the conversion from frequency to voltage is completed. As can be seen from the above formula, the clock voltage signal Vclk is inversely proportional to the clock frequency fclk of the clock signal.

[0093] The signal quantization module 200 is connected to the frequency conversion module 100 and quantizes analog electrical signals into digital signals without using an additional clock signal.

[0094] For analog electrical signals, including clock and current signals:

[0095] In one implementation, such as Figure 6 As shown, the signal quantization module 200 includes a charge / discharge unit 210 and a comparison output unit 220.

[0096] The charging / discharging unit 210 is connected to the frequency conversion module 100. During a first time T1, it performs a charging operation based on the difference between a first current signal I1 and a second current signal I2, and during a second time T2, it performs a discharging operation based on the second current signal I2 to obtain the capacitor voltage signal Vcap. The second current signal I2 is the sum of the clock current signal Iclk and the third current signal I3. In one example, such as... Figure 6 and Figure 7 As shown, the charging and discharging unit 210 includes a first current section 211, a clock current section 212, a third current section 213, and a charging and discharging control section 214. Furthermore, it also includes a voltage control supply section 215.

[0097] The first current section 211 is used to generate a first current signal I1 for charging operation. Specifically, as shown... Figure 6 As shown, the first current section 211 includes a seventh MOSFET M7 and an eighth MOSFET M8. The control terminal of the seventh MOSFET M7 is connected to the first control voltage signal Vc1, the first terminal of the seventh MOSFET M7 is connected to the second terminal of the eighth MOSFET M8, the second terminal of the seventh MOSFET M7 is connected to the power supply voltage signal AVDD, the control terminal of the eighth MOSFET M8 is connected to the first bias voltage signal Vb1, and the first terminal of the eighth MOSFET M8 serves as the current supply terminal of the first current section 211.

[0098] The clock current section 212 is connected to the frequency conversion module 100 and is used to transmit the clock current signal Iclk for discharge operation. Specifically, as shown... Figure 6 As shown, the clock current section 212 includes a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12. The control terminal of the ninth MOSFET M9 is connected to the control terminal of the tenth MOSFET M10 and is also connected to the second bias signal Vb2. The first terminal of the ninth MOSFET M9 is connected to the output terminal of the frequency conversion module 100. The second terminal of the ninth MOSFET M9 is connected to the first terminal of the eleventh MOSFET M11. The first terminal of the tenth MOSFET M10 serves as the current supply terminal of the clock current section 212. The second terminal of the tenth MOSFET M10 is connected to the first terminal of the twelfth MOSFET M12. The control terminal of the eleventh MOSFET M11 is connected to the control terminal of the twelfth MOSFET M12 and is also connected to the first terminal of the ninth MOSFET M9. The second terminals of the eleventh MOSFET M11 and the twelfth MOSFET M12 are connected to the reference ground.

[0099] The third current section 213 is used to generate a third current signal I3 for discharge operation. Specifically, as shown... Figure 6As shown, the third current section 213 includes a thirteenth MOSFET M13 and a fourteenth MOSFET M14. The control terminal of the thirteenth MOSFET M13 is connected to the second bias signal Vb2. The first terminal of the thirteenth MOSFET M13 serves as the current supply terminal of the third current section 213. The second terminal of the thirteenth MOSFET M13 is connected to the first terminal of the fourteenth MOSFET M14. The control terminal of the fourteenth MOSFET M14 is connected to the second control signal Vc2. The second terminal of the fourteenth MOSFET M14 is connected to the reference ground.

[0100] The charge / discharge control section 214 is connected to the first current section 211, the clock current section 212, and the third current section 213, respectively. Under the control of the output signal OUT, it simultaneously initiates charging and discharging operations within a first time T1, performing a charging operation based on the difference between the first current signal I1 and the second current signal I2. Within a second time T2, it deactivates the charging operation and continues discharging based on the second current signal I2. Specifically, as shown... Figure 6 As shown, the charge / discharge control section 214 includes a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, and a third capacitor C3. The control terminal of the fifteenth MOSFET M15 is connected to the output signal OUT. The first terminal of the fifteenth MOSFET M15 is connected to the first terminal of the sixteenth MOSFET M16. The second terminal of the fifteenth MOSFET M15 is connected to the second terminal of the seventeenth MOSFET M17 and is connected to the supply terminal of the first current section 211. The control terminal of the sixteenth MOSFET M16 is connected to its first terminal. The second terminal of the sixteenth MOSFET M16 is connected to the reference ground. The control terminal of the seventeenth MOSFET M17 is connected to the inverted signal OUTb of the output signal. The first terminal of the seventeenth MOSFET M17 is connected to the first terminal of the third capacitor C3 and is connected to the supply terminals of the clock current section 212 and the third current section 213. The first terminal of the third capacitor C3 serves as the output terminal of the charge / discharge unit 210, and the second terminal of the third capacitor C3 is connected to the reference ground.

[0101] The voltage control supply section 215 is used to provide a first voltage control signal Vc1 to the first current section 211 and a second voltage control signal Vc2 to the third current section 213. Specifically, as shown... Figure 7As shown, the voltage control supply section 215 includes a second operational amplifier AMP2, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a twenty-third MOSFET M23, and a second resistor R2. Further, it also includes a Miller capacitor Cm, and even a compensation resistor (not shown in the figure). The first input terminal (e.g., the negative input terminal) of the second operational amplifier AMP2 is connected to the third voltage signal V3. The second input terminal (e.g., the positive input terminal) of the second operational amplifier AMP2 is connected to the first terminal of the second resistor R2. The output terminal of the second operational amplifier AMP2 is connected to the control terminals of the eighteenth MOSFET M18 and the nineteenth MOSFET M19. The output terminal of the second operational amplifier AMP2 is also connected to the first terminal of the second resistor R2 and serves as the first output terminal of the voltage control supply section 215. The first terminal of the eighteenth MOSFET M18 is connected to the second terminal of the twentieth MOSFET M20. Connect the power supply voltage signal AVDD. The first terminal of the nineteenth MOSFET M19 is connected to the second terminal of the twenty-first MOSFET M21. The second terminal of the nineteenth MOSFET M19 is connected to the power supply voltage signal AVDD. The control terminal of the twentieth MOSFET M20 is connected to the control terminal of the twenty-first MOSFET M21 and connected to the first bias signal Vb1. The first terminal of the twentieth MOSFET M20 is connected to the first terminal of the second resistor R2. The first terminal of the twenty-first MOSFET M21 is connected to the first terminal of the twenty-second MOSFET M22 and the control terminal of the twenty-third MOSFET M23, serving as the second output terminal of the control voltage supply section 215. The control terminal of the twenty-second MOSFET M22 is connected to the second bias signal Vb2. The second terminal of the twenty-second MOSFET M22 is connected to the first terminal of the twenty-third MOSFET M23. The twenty-third MOSFET M23 and the second terminal of the second resistor R2 are connected to the reference ground. A Miller capacitor Cm or a compensation resistor is connected in series with the Miller capacitor Cm between the output terminal of the second operational amplifier AMP2 and the first terminal of the second resistor R1. In practical applications, the second operational amplifier AMP2 is a two-stage operational amplifier connected in unity-gain negative feedback. In addition, in order to obtain an accurate voltage signal, the reference voltage signal provided by the bandgap reference circuit can be used as the third voltage signal V3.

[0102] The comparison output unit 220 is connected to the charge / discharge unit 210. It obtains the output signal OUT by comparing the capacitor voltage signal Vcap and the reference voltage signal Vref, and quantizes the clock current signal Iclk based on the duty cycle of the output signal OUT. In one example, the comparison output unit 220 includes a comparator CMP1, an inverter INV, and a D flip-flop DFF. The first input terminal (e.g., the negative input terminal) of the comparator CMP1 is connected to the reference voltage signal Vref; the second input terminal (e.g., the positive input terminal) of the comparator CMP1 is connected to the output terminal of the charge / discharge unit 210; the output terminal of the comparator CMP1 is connected to the input terminal of the inverter INV; the output terminal of the inverter INV is connected to the data terminal of the D flip-flop DFF; the clock terminal of the D flip-flop DFF is connected to the clock signal clk; and the output terminal of the D flip-flop DFF serves as the output terminal of the comparison output unit 220. It should be noted that the clock signal clk connected to the clock terminal of the D flip-flop DFF is the clock signal to be detected and does not need to be provided separately.

[0103] In the signal quantization module 200 described in the above embodiment, the third voltage signal V3 of the voltage control supply section 215 satisfies Formula 8: Thus, the current flowing through the branch containing the second resistor R2 satisfies Formula Nine: Where V3' is the node voltage at the first end of the second resistor R2, V3 is the value of the third voltage signal, IR2 is the current flowing through the branch containing the second resistor, and R2 is the value of the second resistor; furthermore, the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, and the twenty-first MOSFET M21 constitute a common-source common-gate current mirror. The width-to-length ratio of the eighteenth MOSFET M18 is the same as that of the nineteenth MOSFET M19, that is, the current mirror ratio of this common-source common-gate current mirror is 1:1. Therefore, the current flowing through the branch containing the nineteenth MOSFET M19 is equal to the current flowing through the branch containing the second resistor.

[0104] The seventh MOSFET M7 and the eighth MOSFET M8 in the first current section 211, together with the eighteenth MOSFET M18 and the twentieth MOSFET M20 in the voltage control section 215, form a common-source cascode current mirror. The width-to-length ratio of the seventh MOSFET M7 to the eighteenth MOSFET M18 satisfies M:1, that is, the current mirror ratio of this common-source cascode current mirror is M:1. Thus, the first current signal I1 satisfies Formula 10: In the clock current section 212, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 form a common-source cascode current mirror. The aspect ratio of the eleventh MOSFET M11 is the same as that of the twelfth MOSFET M12, meaning the current mirror ratio of this common-source cascode current mirror is 1:1, thus enabling the transmission of the clock current signal Iclk. In the third current section 213, the thirteenth MOSFET M13 and the fourteenth MOSFET M14, together with the twenty-second MOSFET M22 and the twenty-third MOSFET M23 in the voltage control section 215, form a common-source cascode current mirror. The aspect ratio of the fourteenth MOSFET M14 is N:1, meaning the current mirror ratio of this common-source cascode current mirror is N:1, thus the third current signal I3 satisfies Formula 11: Among them, the first current signal I1 is greater than the sum of the clock current signal Iclk and the third current signal I3, that is, I1>Iclk+I3, therefore, M>N.

[0105] In the charge / discharge control section 214, the fifteenth MOSFET M15 and the seventeenth MOSFET M17 are controlled by the output signal and its inverted signal, respectively. During the first time interval T1, the output signal OUT is high, and the inverted signal OUTb is low. The fifteenth MOSFET M15 is turned off and the seventeenth MOSFET M17 is turned on. The third capacitor C3 is charged based on the first current signal I1, and the third capacitor C3 is discharged based on the second current signal (i.e., the sum of the clock current signal Iclk and the third current signal I3). Since the charging current is greater than the discharging current, the capacitor voltage signal Vcap rises, that is, the voltage at the positive input terminal of the comparator CMP1 rises. When Vcap... When ap > Vref, the output of comparator CMP1 flips to a high level, and the output of D flip-flop DFF flips to a low level. During the second time T2, the output signal OUT is low, and the inverted signal OUTb is high. The fifteenth MOSFET M15 is turned on, and the seventeenth MOSFET M17 is turned off. Based on the second current signal (i.e., the sum of the clock current signal Iclk and the third current signal I3), the third capacitor C3 is discharged, and the capacitor voltage signal Vcap decreases, that is, the voltage at the positive input terminal of comparator CMP1 decreases. When Vcap < Vref, the output of comparator CMP1 flips to a low level, and the output of D flip-flop DFF flips to a high level. When the charge and discharge are balanced, we have Formula Twelve: Combining formulas five, ten, and eleven, we obtain formula thirteen: When the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, Formula Thirteen simplifies to Formula Fourteen: Finally, the clock frequency fclk of the clock signal is converted into the duty cycle Duty of the output signal. The value of the clock frequency fclk can be calculated by combining the known parameters. The entire detection process does not require an additional crystal oscillator to provide the main frequency. As can be seen from the above formula, the duty cycle Duty of the output signal is directly proportional to the clock frequency fclk of the clock signal.

[0106] For analog electrical signals, including clock voltage signals:

[0107] In one implementation, such as Figure 8 As shown, the signal quantization module 200 includes not only the units described above, but also an input conversion unit 230.

[0108] Input conversion unit 230 is connected between frequency conversion module 100 and charging / discharging unit 210, and is used to convert clock voltage signal Vclk into clock current signal Iclk. In one example, such as Figure 8 As shown, the input conversion unit 230 includes an amplifier section 231 and a voltage-to-current conversion section 232, and further includes a Miller compensation section 233.

[0109] Amplifier section 231 is connected to frequency conversion module 100 and is used to amplify the clock voltage signal Vclk to obtain the fourth voltage signal V4. Specifically, as shown... Figure 8 As shown, amplifier section 231 includes two operational amplifiers AMP3 connected in unity-gain negative feedback configuration. For example, the negative input of the two operational amplifiers AMP3 is connected to the clock voltage signal Vclk, and the positive input of the two operational amplifiers AMP3 is connected to its output and to the first terminal of the third resistor R3 in voltage-to-current conversion section 232.

[0110] The voltage-to-current conversion section 232 is connected to the amplifier section 231 and is used to convert the fourth voltage signal V4 into a clock current signal Iclk. Specifically, the voltage-to-current conversion section 232 includes a 24th MOSFET M24, a 25th MOSFET M25, a 26th MOSFET M26, a 27th MOSFET M27, and a third resistor R3. The control terminal of the 24th MOSFET M24 is connected to the control terminal of the 25th MOSFET M25 and is connected to a fourth voltage signal V4. The first terminal of the 24th MOSFET M24 is connected to the second terminal of the 26th MOSFET M26, and the second terminal of the 24th MOSFET M24 is connected to a power supply voltage signal AVDD. The first terminal of the 25th MOSFET M25 is connected to the second terminal of the 27th MOSFET M27, and the second terminal of the 25th MOSFET M25 is connected to the power supply voltage signal AVDD. The control terminal of the 26th MOSFET M26 is connected to the control terminal of the 27th MOSFET M27 and is connected to a first bias signal Vb1. The first terminal of the 26th MOSFET M26 is connected to the first terminal of the third resistor R3. The first terminal of the 27th MOSFET M27 serves as the output terminal of the input conversion unit 230. The first terminal of the third resistor R3 is connected to the output terminal of the amplifier section 231, and the second terminal of the third resistor R3 is connected to reference ground.

[0111] Miller compensation section 233 is connected between amplifier section 231 and voltage-to-current conversion section 232 to compensate for the frequency characteristics of amplifier section 231. In this case, the positive input terminals of the two-stage operational amplifier AMP3 in amplifier section 231 are no longer directly connected to their output terminals, but are connected via Miller compensation section 233. Similarly, the first terminal of the third resistor in voltage-to-current conversion section 232 is no longer directly connected to the output terminal of amplifier section 231, but is connected via Miller compensation section 233. In one example, Miller compensation section 233 includes a Miller capacitor (not shown in the figure). In other examples, Miller compensation section 233 also includes a compensation resistor (not shown in the figure). In this case, the Miller capacitor and compensation resistor are connected in series between amplifier section 231 and voltage-to-current conversion section 232.

[0112] In the above embodiment, the fourth voltage signal of amplifier section 231 satisfies formula fifteen: Where V4 is the value of the fourth voltage signal; in the voltage-to-current conversion section 232, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, and the twenty-seventh MOSFET M27 constitute a common-source, common-gate current mirror. The width-to-length ratio of the twenty-fourth MOSFET M24 is the same as that of the twenty-fifth MOSFET M25, that is, the current mirror ratio of this common-source, common-gate current mirror is 1:1. Therefore, the current flowing through the branch containing the third resistor R3 is equal to the current flowing through the branch containing the twenty-fifth MOSFET M25, satisfying Formula Sixteen: IR3 is the current flowing through the branch containing the third resistor; then, the clock current signal Iclk is quantized using the method described above. For the case where Vclk = V1·R1·fclk·(C1+C2), when the values ​​of the first resistor R1 and the third resistor R3 are equal and the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, formula fourteen can be obtained. In the case where the values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 are equal, and the first voltage signal V1 and the third voltage signal V3 are reference voltage signals, we obtain Formula Seventeen: Finally, the clock frequency fclk of the clock signal clk is converted into the duty cycle Duty of the output signal. The value of the clock frequency fclk can be calculated by combining the known parameters. The entire detection process does not require an additional crystal oscillator to provide the main frequency. As can be seen from Formula 14, the duty cycle Duty of the output signal is directly proportional to the clock frequency fclk of the clock signal. As can be seen from Formula 17, the duty cycle Duty of the output signal is inversely proportional to the clock frequency fclk of the clock signal.

[0113] In another embodiment, the signal quantization module 200 is implemented using a flash analog-to-digital converter (Flash ADC), a successive approximation analog-to-digital converter (SAR ADC), or a pipelined analog-to-digital converter (pipelined ADC). None of the above analog-to-digital converters require an additional crystal oscillator to provide the main frequency. Of course, other analog-to-digital conversion structures that do not use an additional crystal oscillator are also applicable to this embodiment. Figure 9 An n-bit flash memory analog-to-digital converter is shown, including a resistor string 240, a comparator array 250, and a decoder 260. The resistor string 240 includes 2n fourth resistors R4 connected in series between a reference voltage signal Vref and a reference ground, dividing the reference voltage signal Vref into 2n-1 voltage divider signals. The comparator array 250 includes 2n-1 comparators CMP2, with the positive input terminals connected to the 2n-1 voltage divider signals and the negative input terminals connected to the clock voltage signal Vclk. The output terminals are connected to the decoder 260. The decoder 260 converts the thermometer code output by the 2n-1 comparators CMP2 into binary code, realizing the quantization of the clock voltage signal Vclk. Here, n is a natural number greater than 1.

[0114] In practical applications, the first MOSFET M1, the second MOSFET M2, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the thirteenth MOSFET M13, the fourteenth MOSFET M14, the sixteenth MOSFET M16, the twenty-second MOSFET M22, and the twenty-third MOSFET M23 mentioned above are NMOS transistors, while the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, the fifteenth MOSFET M15, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, and the twenty-seventh MOSFET M27 are PMOS transistors. Among them, the control terminal is the gate, the first terminal is the drain, and the second terminal is the source.

[0115] Accordingly, this embodiment also provides a frequency detection method, including the following steps; wherein the frequency detection method is implemented using the frequency detection circuit 10 described above.

[0116] The clock frequency fclk of the clock signal is converted into an analog electrical signal. In one embodiment, the clock frequency fclk of the clock signal is converted into a clock current signal as an analog electrical signal output; in another embodiment, the clock frequency fclk of the clock signal is converted into a clock voltage signal as an analog electrical signal output; relevant details are described above and will not be repeated here.

[0117] To perform clock frequency detection, analog electrical signals are quantized into digital signals without using an additional clock signal. In one implementation, the clock current signal is quantized into a digital signal; in another implementation, the clock voltage signal is quantized into a digital signal; details are provided above and will not be repeated here.

[0118] The present invention also provides an image sensor, including a quantization circuit as described in any of the above embodiments. The quantization circuit can be disposed in the peripheral circuit area of ​​the image sensor. Furthermore, the image sensor can be applied in electronic devices, such as security monitoring devices, automotive electronics, mobile phone cameras, machine vision devices, etc.

[0119] In summary, the frequency detection circuit, frequency detection method, and image sensor of this invention convert the clock frequency of a clock signal into an analog domain current or voltage signal before quantization. This eliminates the need for an additional crystal oscillator to provide the main frequency, saves chip area, facilitates circuit integration, and reduces design costs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0120] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A frequency detection circuit, characterized in that, The frequency detection circuit includes: A frequency conversion module receives a clock signal and converts the clock frequency of the clock signal into an analog electrical signal for clock frequency detection; wherein, the frequency conversion module includes a resistance acquisition unit, which receives the clock signal and converts the clock frequency of the clock signal into a clock resistance signal to obtain the analog electrical signal.

2. The frequency detection circuit according to claim 1, characterized in that, The resistance acquisition unit includes a first transmission gate, a second transmission gate, a first MOSFET, a second MOSFET, a first capacitor, and a second capacitor. The input terminal of the first transmission gate is connected to the input terminal of the second transmission gate and serves as the access terminal of the resistance acquisition unit. The output terminal of the first transmission gate is connected to the first terminal of the first MOSFET and connected to reference ground via the first capacitor. The first control terminal of the first transmission gate is connected to the control terminal of the second MOSFET and receives the clock signal. The second control terminal of the first transmission gate receives the inverted signal of the clock signal. The output terminal of the second transmission gate is connected to the first terminal of the second MOSFET and connected to reference ground via the second capacitor. The first control terminal of the second transmission gate receives the inverted signal of the clock signal. The second control terminal of the second transmission gate is connected to the control terminal of the first MOSFET and receives the clock signal. The second terminals of the first MOSFET and the second MOSFET are connected to reference ground.

3. The frequency detection circuit according to claim 1, characterized in that, The frequency conversion module includes: A voltage amplification unit is connected to the input terminal of the resistance acquisition unit, receives a first voltage signal, and amplifies the first voltage signal to obtain a second voltage signal; A current generation unit, connected to the voltage amplification unit, generates a clock current signal based on the second voltage signal and the clock resistor signal and outputs it as the analog electrical signal. Alternatively, the frequency conversion module may further include a Miller compensation unit connected between the resistance acquisition unit and the voltage amplification unit.

4. The frequency detection circuit according to claim 3, characterized in that, The voltage amplification unit includes a first operational amplifier, a third MOSFET, and a fourth MOSFET. The first input terminal of the first operational amplifier is connected to a first voltage signal, and the second input terminal of the first operational amplifier is connected to the access terminal of the resistance acquisition unit. The output terminal of the first operational amplifier is connected to the control terminal of the third MOSFET and also to the access terminal of the resistance acquisition unit. The first terminal of the third MOSFET is connected to the second terminal of the fourth MOSFET, and the second terminal of the third MOSFET is connected to a power supply voltage signal. The control terminal of the fourth MOSFET is connected to a first bias signal, and the first terminal of the fourth MOSFET is connected to the access terminal of the resistance acquisition unit. When the frequency conversion module further includes a Miller compensation unit, the output terminal of the first operational amplifier is connected to the access terminal of the resistance acquisition unit via the Miller compensation unit. The current generation unit includes a fifth MOSFET and a sixth MOSFET. The control terminal of the fifth MOSFET is connected to the output terminal of the first operational amplifier. The first terminal of the fifth MOSFET is connected to the second terminal of the sixth MOSFET. The second terminal of the fifth MOSFET is connected to the power supply voltage signal. The control terminal of the sixth MOSFET is connected to the first bias signal. The first terminal of the sixth MOSFET serves as the output terminal of the current generation unit.

5. The frequency detection circuit according to claim 3, characterized in that, The frequency conversion module also includes: A voltage generation unit, connected to the current generation unit, is used to convert the clock current signal into a clock voltage signal and replace the clock current signal as the analog electrical signal output.

6. The frequency detection circuit according to claim 5, characterized in that, The voltage generation unit is implemented using a first resistor.

7. The frequency detection circuit according to claim 6, characterized in that, The positions of the first resistor and the resistance acquisition unit are interchanged, wherein the current generation unit generates a fixed current signal based on the second voltage signal and the first resistance signal, and generates the clock voltage signal through the resistance acquisition unit.

8. The frequency detection circuit according to any one of claims 1 to 7, characterized in that, The frequency detection circuit further includes: The signal quantization module, connected to the frequency conversion module, quantizes the analog electrical signal into a digital signal without using an additional clock signal.

9. The frequency detection circuit according to claim 8, characterized in that, When the analog electrical signal includes a clock current signal, the signal quantization module includes: A charging / discharging unit, connected to the frequency conversion module, performs a charging operation based on the difference between a first current signal and a second current signal within a first time period and a discharging operation based on the second current signal within a second time period to obtain a capacitor voltage signal, wherein the second current signal is the sum of the clock current signal and a third current signal; a comparison output unit, connected to the charging / discharging unit, obtains an output signal by comparing the capacitor voltage signal and a reference voltage signal, and quantizes the clock current signal based on the duty cycle of the output signal; And / or, the comparison output unit includes a comparator, an inverter, and a D flip-flop. The first input terminal of the comparator is connected to a reference voltage signal, the second input terminal of the comparator is connected to the output terminal of the charge / discharge unit, the output terminal of the comparator is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the data terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock signal, and the output terminal of the D flip-flop serves as the output terminal of the comparison output unit.

10. The frequency detection circuit according to claim 9, characterized in that, The charging / discharging unit includes: The first current section is used to generate the first current signal for charging operation; The clock current section is connected to the frequency conversion module and is used to transmit the clock current signal for discharge operation; The third current section is used to generate the third current signal for discharge operation; The charge / discharge control section is connected to the first current section, the clock current section, and the third current section, respectively, and is used to simultaneously start the charging operation and the discharging operation in a first time period under the control of the output signal, and to turn off the charging operation and continue the discharging operation in a second time period.

11. The frequency detection circuit according to claim 10, characterized in that, The first current section includes a seventh MOSFET and an eighth MOSFET. The control terminal of the seventh MOSFET is connected to a first control voltage signal. The first terminal of the seventh MOSFET is connected to the second terminal of the eighth MOSFET. The second terminal of the seventh MOSFET is connected to a power supply voltage signal. The control terminal of the eighth MOSFET is connected to a first bias voltage signal. The first terminal of the eighth MOSFET serves as the current supply terminal of the first current section. And / or, the clock current section includes a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, and a twelfth MOSFET. The control terminal of the ninth MOSFET is connected to the control terminal of the tenth MOSFET and connected to a second bias signal. The first terminal of the ninth MOSFET is connected to the output terminal of the frequency conversion module. The second terminal of the ninth MOSFET is connected to the first terminal of the eleventh MOSFET. The first terminal of the tenth MOSFET serves as the current supply terminal of the clock current section. The second terminal of the tenth MOSFET is connected to the first terminal of the twelfth MOSFET. The control terminal of the eleventh MOSFET is connected to the control terminal of the twelfth MOSFET and connected to the first terminal of the ninth MOSFET. The second terminals of the eleventh MOSFET and the twelfth MOSFET are connected to a reference ground. And / or, the third current section includes a thirteenth MOSFET and a fourteenth MOSFET, the control terminal of the thirteenth MOSFET is connected to a second bias signal, the first terminal of the thirteenth MOSFET serves as the current supply terminal of the third current section, the second terminal of the thirteenth MOSFET is connected to the first terminal of the fourteenth MOSFET, the control terminal of the fourteenth MOSFET is connected to a second control signal, and the second terminal of the fourteenth MOSFET is connected to a reference ground; And / or, the charge / discharge control section includes a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, and a third capacitor. The control terminal of the fifteenth MOSFET is connected to the output signal. The first terminal of the fifteenth MOSFET is connected to the first terminal of the sixteenth MOSFET. The second terminal of the fifteenth MOSFET is connected to the second terminal of the seventeenth MOSFET and connected to the supply terminal of the first current section. The control terminal of the sixteenth MOSFET is connected to its first terminal. The second terminal of the sixteenth MOSFET is connected to reference ground. The control terminal of the seventeenth MOSFET is connected to the inverted signal of the output signal. The first terminal of the seventeenth MOSFET is connected to the first terminal of the third capacitor and connected to the clock current section and the supply terminal of the third current section. The first terminal of the third capacitor serves as the output terminal of the charge / discharge unit, and the second terminal of the third capacitor is connected to reference ground.

12. The frequency detection circuit according to claim 10, characterized in that, The charging and discharging unit further includes a voltage control providing section for providing a first voltage control signal to the first current section and a second voltage control signal to the third current section.

13. The frequency detection circuit according to claim 12, characterized in that, The voltage control supply section includes a second operational amplifier, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, a twenty-second MOSFET, a twenty-third MOSFET, and a second resistor. The first input terminal of the second operational amplifier is connected to a third voltage signal, and the second input terminal of the second operational amplifier is connected to the first terminal of the second resistor. The output terminal of the second operational amplifier is connected to the control terminals of the eighteenth and nineteenth MOSFETs. The output terminal of the second operational amplifier is also connected to the first terminal of the second resistor and serves as the first output terminal of the voltage control supply section. The first terminal of the eighteenth MOSFET is connected to the second terminal of the twentyth MOSFET, and the second terminal of the eighteenth MOSFET is connected to a power supply voltage signal. The first terminal of the nineteenth MOSFET is connected to the twenty-first MOSFET. The second terminal of the nineteenth MOSFET is connected to the power supply voltage signal. The control terminal of the twentieth MOSFET is connected to the control terminal of the eleventh MOSFET and to the first bias signal. The first terminal of the twentieth MOSFET is connected to the first terminal of the second resistor. The first terminal of the eleventh MOSFET is connected to the first terminal of the twelfth MOSFET and the control terminal of the thirteenth MOSFET, serving as the second output terminal of the voltage control supply section. The control terminal of the twelfth MOSFET is connected to the second bias signal. The second terminal of the twelfth MOSFET is connected to the first terminal of the thirteenth MOSFET. The second terminal of the thirteenth MOSFET and the second terminal of the second resistor are connected to reference ground. Alternatively, the voltage control supply section further includes a Miller capacitor connected between the output terminal of the second operational amplifier and the first terminal of the second resistor.

14. The frequency detection circuit according to claim 9, characterized in that, When a clock voltage signal is used to replace the clock current signal as the analog electrical signal, the signal quantization module further includes an input conversion unit connected between the frequency conversion module and the charging / discharging unit, used to convert the clock voltage signal into the clock current signal.

15. The frequency detection circuit according to claim 14, characterized in that, The input conversion unit includes: The amplifier section is connected to the frequency conversion module and is used to amplify the clock voltage signal to obtain a fourth voltage signal; The voltage-to-current conversion section, connected to the amplifier section, is used to convert the fourth voltage signal into the clock current signal; Alternatively, the input conversion unit may further include a Miller compensation section connected between the amplifier section and the voltage-to-current conversion section.

16. The frequency detection circuit according to claim 15, characterized in that, The amplifier section includes a two-stage operational amplifier connected in a unity-gain negative feedback configuration; and / or, the voltage-to-current conversion section includes a 24th MOSFET, a 25th MOSFET, a 26th MOSFET, a 27th MOSFET, and a third resistor. The control terminal of the 24th MOSFET is connected to the control terminal of the 25th MOSFET and is connected to the fourth voltage signal. The first terminal of the 24th MOSFET is connected to the second terminal of the 26th MOSFET, and the second terminal of the 24th MOSFET is connected to the power supply voltage signal. The first terminal of the 25th MOSFET is connected to the second terminal of the 27th MOSFET, and the second terminal of the 25th MOSFET is connected to the power supply voltage signal. The control terminal of the 26th MOSFET is connected to the control terminal of the 27th MOSFET and is connected to the first bias signal. The first terminal of the 26th MOSFET is connected to the first terminal of the third resistor. The first terminal of the 27th MOSFET serves as the output terminal of the input conversion unit. The first terminal of the third resistor is connected to the output terminal of the amplifier section, and the second terminal of the third resistor is connected to reference ground. Wherein, when the input conversion unit includes a Miller compensation section, the first terminal of the third resistor is connected to the output terminal of the amplifier section via the Miller compensation section.

17. The frequency detection circuit according to claim 8, characterized in that, The signal quantization module is implemented using a flash-type analog-to-digital converter, a successive approximation analog-to-digital converter, or a pipelined analog-to-digital converter.

18. A frequency detection method, characterized in that, The frequency detection method includes: Convert the clock frequency of the clock signal into an analog electrical signal; The analog electrical signal is quantized into a digital signal for clock frequency detection without using an additional clock signal.

19. An image sensor, characterized in that, Includes the frequency detection circuit as described in any one of claims 1 to 17.

Images