Performance counting device and chip

Abstract

The invention relates to a performance counting device and a chip, and the performance counting device comprises a performance counting module which is used for receiving at least one instruction memory address from a program counter associated with the performance counting module, and according to the at least one instruction memory address and a pre-configured instruction memory address interval, counting the at least one instruction memory address; obtaining a statistical value of a performance signal of at least one instruction memory address in the instruction memory address interval; the storage module is used for storing the statistical value of the performance signal of the at least one instruction memory address of the performance statistical module; the write-in control module is used for writing the statistical value, obtained by the performance statistical module, of the performance signal of the at least one instruction memory address into the storage module; and the configuration module is used for configuring an instruction memory address interval of the performance statistics module. According to the method and the device, the configuration flexibility of performance statistics can be improved, performance statistics of a plurality of specified program segments can be realized at the same time on the basis, and parallel processing of the performance statistics and accurate positioning of the program segments are further realized.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a performance counting device and chip. Background Technology

[0002] One characteristic of processors is their support for multitasking, enabling them to process multiple programs or instruction streams simultaneously. When multiple programs run, their assembly instruction execution times can vary due to rich instruction sets, strong interdependencies, resource conflicts, or other factors. Analyzing processor program segment performance requires hardware capabilities to statistically analyze the performance of that segment during execution. During processor performance debugging, it's typically necessary to identify the instruction segments that consume the highest absolute or percentage of execution time for each thread or thread bundle during program execution. This helps pinpoint performance bottlenecks and allows for targeted instruction optimization to improve program execution performance.

[0003] In related technologies, performance counters (PFCs) are commonly used to statistically analyze program segment performance. This involves counting various events during program execution, such as the number of instructions, clock cycles, and cache misses. By configuring the relevant registers of the performance counter, the type of performance to be counted can be selected.

[0004] This approach offers limited configuration flexibility, allowing only a limited number of performance events to be counted. It also cannot simultaneously count multiple parallel programs, and the counters are only incremented when an event occurs, resulting in a single statistical interval and a lack of dynamic and precise capture of processor program segments. Furthermore, this technology cannot configure the source of program segment performance generation, nor can it precisely control the performance data generated by a specific module. When precise source tracing is required for specific performance data generated by a particular module, program, or time period, it cannot accurately pinpoint the source. Summary of the Invention

[0005] In view of this, the present disclosure provides a performance counting device and chip to help improve the configuration flexibility of performance statistics, thereby enabling simultaneous performance statistics of multiple specified program segments, and thus achieving parallel processing of performance statistics and precise location of program segments.

[0006] According to one aspect of the embodiments of this disclosure, a performance counting device is provided, comprising:

[0007] A performance statistics module is used to receive at least one instruction memory address from the associated program counter, and to obtain statistical values ​​of the performance signals of the at least one instruction memory address located within the instruction memory address range based on the at least one instruction memory address and a pre-configured instruction memory address range.

[0008] A storage module is used to store statistical values ​​of performance signals for at least one instruction memory address of the performance statistics module;

[0009] A write control module, coupled to the performance statistics module and the storage module, is used to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the storage module;

[0010] A configuration module, coupled to the performance statistics module, is used to configure the instruction memory address range of the performance statistics module.

[0011] In one possible implementation, the performance statistics module includes:

[0012] An interval comparison submodule, coupled to the configuration module, is used to obtain the instruction memory address interval from the configuration module, receive the at least one instruction memory address from the program counter associated with the performance statistics module, and compare each received instruction memory address with the instruction memory address interval respectively.

[0013] At least one counter is coupled to the interval comparison submodule, and the at least one counter corresponds to at least one instruction memory address in the instruction memory address interval. When the instruction memory address received by the interval comparison submodule from the program counter is within the instruction memory address interval, the interval comparison submodule triggers the counter corresponding to the instruction memory address to perform performance signal counting and accumulation to obtain a statistical value of the performance signal associated with the instruction memory address.

[0014] At least one counting register is coupled one-to-one with the at least one counter, and each of the at least one counting registers is used to temporarily store statistical values ​​of performance signals associated with the instruction memory address obtained by the corresponding counter.

[0015] In one possible implementation, the configuration module is configured to configure the instruction memory address range of the performance statistics module as: including at least two consecutive instruction memory addresses, or including at least two instruction memory addresses with a spanning interval step.

[0016] In one possible implementation, the configuration module includes:

[0017] A counting mode register is used to configure the counting mode of the instruction memory address range. The counting mode is either a continuous range mode or a step mode. When the counting mode is the continuous range mode, the instruction memory address range includes at least two instruction memory addresses that are consecutive. When the counting mode is the step mode, the instruction memory address range includes at least two instruction memory addresses that span an interval step.

[0018] The start address register is used to configure the starting address of the instruction memory address range;

[0019] Termination address register, used to configure the termination address of the instruction memory address range;

[0020] An interval step register is used to configure the spanning interval step when the counting mode is the step mode.

[0021] In one possible implementation, the performance signal is a high-level signal triggered when the program segment whose performance is to be statistically analyzed enters the instruction memory address range.

[0022] In one possible implementation, the performance statistics module is at least one, and the program counter is at least one;

[0023] The performance counting device further includes:

[0024] A cross switch module, coupled to at least one of the performance statistics module and the configuration module, is used to establish an association between the performance statistics module and the program counter under the configuration of the configuration module;

[0025] The configuration module is also used to configure thread bundle identifiers and execution unit identifiers, and associate the program counter containing the configured thread bundle identifiers and execution unit identifiers with the performance statistics module.

[0026] In one possible implementation, the configuration module includes:

[0027] Thread beam identifier register, used to configure the thread beam identifier;

[0028] The execution unit identification number register is used to configure the execution unit identification number.

[0029] In one possible implementation, the configuration module is further configured to configure the number of storage slots in the storage module;

[0030] The write control module is further configured to, according to the configuration of the number of storage slots of the storage module by the configuration module, write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the current storage slot of the storage module, and after the storage slot write transfer condition is reached, write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the next storage slot.

[0031] The storage slot write transfer condition includes at least one of the following: the storage slot write duration reaches a preset duration threshold, or the amount of data written to the storage slot reaches a preset data amount threshold.

[0032] In one possible implementation, the configuration module includes:

[0033] The storage slot quantity register is used to configure the number of storage slots in the storage module.

[0034] In one possible implementation, the performance counting device further includes:

[0035] A readout control module, coupled to the storage module and the configuration module, is used to periodically read out and dump the performance data in the storage module to a data storage device other than the performance counting device according to the configured dump time interval.

[0036] The configuration module is also used to configure the dump time interval.

[0037] In one possible implementation, the configuration module includes:

[0038] A dump time interval register is used to configure the dump time interval.

[0039] In one possible implementation, the configuration module includes:

[0040] A switch control register is used to configure the switching of the performance statistics module.

[0041] According to another aspect of the present disclosure, a chip is provided, including the performance counting device as described in any of the preceding claims.

[0042] As can be seen from the above scheme, the performance counting device and chip of this disclosure associate the performance statistics module with the program counter. Since the program counter corresponds to a thread or thread bundle, this disclosure achieves targeted performance statistics for a specified thread or thread bundle. Furthermore, because the performance statistics module is pre-configured with an instruction memory address range, the statistical value of the performance signal of the obtained instruction memory address is located within the pre-configured instruction memory address range, thus achieving precise location of the statistically analyzed program segment (the instruction memory address within the instruction memory address range in the thread or thread bundle). The performance counting device of this disclosure can replace the performance counter in related technologies for program performance statistics. The performance counting device of this disclosure can also flexibly configure the instruction memory address range of the performance statistics module through a configuration module, thereby further improving the flexibility of performance statistics configuration and meeting the performance statistics needs of different application scenarios. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a first embodiment of a performance counting device according to an illustrative embodiment;

[0044] Figure 2 This is a schematic diagram of a second embodiment of a performance counting device, shown according to an illustrative embodiment;

[0045] Figure 3 This is a schematic diagram of the performance statistics module according to an illustrative embodiment;

[0046] Figure 4 This is a schematic diagram of a third embodiment of a performance counting device, shown according to an illustrative embodiment.

[0047] In the attached diagram, the component names represented by each number are as follows:

[0048] 100. Performance counting device,

[0049] 11. Performance statistics module,

[0050] 11_1, First Performance Statistics Module

[0051] 11_2, Second Performance Statistics Module,

[0052] 11_N, the Nth performance statistics module,

[0053] 111. Interval Comparison Submodule

[0054] 112_1, First Counter,

[0055] 112_2, Second Counter

[0056] 112_K, the Kth counter,

[0057] 113_1, First Count Register

[0058] 113_2, Second Count Register

[0059] 113_K, the Kth count register,

[0060] 12. Storage module,

[0061] 13. Write to the control module.

[0062] 14. Configuration module,

[0063] 15. Cross switch module,

[0064] 16. Read the control module.

[0065] 2. Program counter,

[0066] 2_1, First Program Counter,

[0067] 2_2, Second Program Counter,

[0068] 2_M, the Mth program counter,

[0069] 3. Data storage device. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0071] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0072] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0073] This disclosure provides a performance counting device and a chip including the performance counting device. Through precise hardware-level configuration and linkage logic, it enables flexible, concurrent, and traceable statistics on the performance of specific program segments of the processor. By configuring periodic performance data dumps, the instruction memory address of the program counter (PC) is used as performance data. The performance counting device is turned on and off by a controllable switch. It supports configuring one or more hardware performance statistics modules to count the performance of multiple program segments, solving the problems of insufficient configuration flexibility and weak performance data traceability in traditional performance statistics techniques, and achieving accurate statistics on the performance of processor program segments.

[0074] Figure 1 This is a schematic diagram of a first embodiment of a performance counting device, as shown in an illustrative embodiment. Figure 1 As shown in the illustrative embodiment, the performance counting device 100 of the first embodiment includes a performance statistics module 11, a storage module 12, a write control module 13, and a configuration module 14. The performance statistics module 11 receives at least one instruction memory address from its associated program counter 2, and obtains statistical values ​​of the performance signals of at least one instruction memory address located within the instruction memory address range, based on the at least one instruction memory address and a pre-configured instruction memory address range. The storage module 12 stores the statistical values ​​of the performance signals of the at least one instruction memory address obtained by the performance statistics module 11. The write control module 13 is coupled to the performance statistics module 11 and the storage module 12, and writes the statistical values ​​of the performance signals of the at least one instruction memory address obtained by the performance statistics module 11 into the storage module 12. The configuration module 14 is coupled to the performance statistics module 11 and configures the instruction memory address range of the performance statistics module 11.

[0075] The program counter is an important register in a processor (such as a central processing unit) used to store instruction memory addresses. An instruction memory address refers to the location of an instruction in memory. Instructions can be from the programs executed by the processor. In artificial intelligence (AI) computing devices, the computing program typically includes multiple threads or warps. Different threads or warps correspond to different program counters; that is, different program counters store the instruction memory addresses of different threads or warps.

[0076] The performance counting device 100 of this embodiment associates the performance statistics module 11 with the program counter 2. Since the program counter 2 corresponds to a thread or thread bundle, the performance counting device 100 of this embodiment achieves targeted performance statistics for a specified thread or thread bundle. Furthermore, because the performance statistics module 11 pre-configures an instruction memory address range, the statistical value of the obtained instruction memory address performance signal is located within the pre-configured instruction memory address range, thus achieving precise location of the statistically analyzed program segment (the instruction memory address within the instruction memory address range in the thread or thread bundle). The performance counting device 100 of this embodiment can replace the performance counter in related technologies.

[0077] In order to associate the performance statistics module 11 with the program counter 2, improve the flexibility of performance statistics configuration, and perform performance statistics on multiple specified program segments simultaneously, in the illustrative embodiment, there is at least one performance statistics module 11 and at least one program counter 2. The association between the performance statistics module 11 and the program counter 2 can be achieved through a cross switch module.

[0078] Figure 2 This is a schematic diagram illustrating a second embodiment of a performance counting device according to an illustrative embodiment. The performance counting device 100 of the second embodiment includes at least one performance statistics module (e.g., Figure 2 The first performance statistics module 11_1, the second performance statistics module 11_2, ..., the Nth performance statistics module 11_N shown can be associated with different program counters according to the configuration. Based on this, the number of program counters is at least one (e.g., Figure 2 The program counters shown are 1st program counter 2_1, 2nd program counter 2_2, ..., Mth program counter 2_M, where N and M can be the same or different. Depending on the configuration, at least one performance statistics module from 1st performance statistics module 11_1 to Nth performance statistics module 11_N can be associated with at least one program counter from 1st program counter 2_1 to Mth program counter 2_M in a first one-to-one relationship. For example... Figure 2 As shown, the performance counting device 100 in the second embodiment also includes a cross switch module 15. The cross switch module 15 is coupled to at least one performance statistics module (e.g., Figure 2The first performance statistics module 11_1 to the Nth performance statistics module 11_N and the configuration module 14 shown are used to establish a one-to-one association between the performance statistics modules and the program counter under the configuration of the configuration module 14. The configuration module 14 is also used to configure the thread bundle identifier (ID) and the execution unit identifier, and associate the program counter containing the configured thread bundle identifier and execution unit identifier with the performance statistics module. The thread bundle identifier is used to uniquely identify the thread bundle in the program, and the instruction whose performance is to be statistically analyzed can be identified through the thread bundle identifier. In the illustrative embodiment, the execution unit identifier is used to uniquely identify the execution unit that executes the thread bundle (instruction). By configuring the thread bundle identifier (ID) and the execution unit identifier, the specified thread bundle executed by the specified execution unit can be configured, so that the performance counting device of this embodiment can perform targeted performance statistics on the execution of the specified thread bundle (corresponding to the specified program segment) by the specified execution unit, which helps to improve the flexibility of performance statistics configuration. In the context of applications in artificial intelligence computing devices, the execution unit refers to the execution unit (EU) in an artificial intelligence chip that executes the instructions of a thread bundle.

[0079] Since hardware configuration can be implemented using registers, in this illustrative embodiment, the configuration module may include a thread bundle identifier register and an execution unit identifier register. The thread bundle identifier register is used to configure the thread bundle identifier, and the execution unit identifier register is used to configure the execution unit identifier. Based on this, the cross-switch module establishes a one-to-one association between the performance statistics module and the program counter according to the configuration values ​​of the thread bundle identifier register and the execution unit identifier register.

[0080] Figure 3 This is a schematic diagram of the performance statistics module according to an illustrative embodiment. Figure 3 The specific structure of the performance statistics module 11 shown is the specific structure of any performance statistics module involved in the embodiments of this disclosure, for example, it may be... Figure 1 The performance statistics module 11 shown in the figure Figure 2 The specific structure of any one of the first performance statistics module 11_1 to the Nth performance statistics module 11_N shown, and any performance statistics module mentioned in the following description. For example... Figure 3As shown, in an illustrative embodiment, the performance statistics module 11 includes an interval comparison submodule 111, a counter, and a counter register. The interval comparison submodule 111 is coupled to the configuration module 14 and is used to obtain an instruction memory address range from the configuration module 14, receive at least one instruction memory address from the program counter 2 associated with the performance statistics module 11, and compare each received instruction memory address with the instruction memory address range. There is at least one counter, for example... Figure 3 The diagram shows counters 112_1, 112_2, ..., Kth counter 112_K, where K is a positive integer. At least one counter (counter 112_1 to counter K 112_K) is coupled to the interval comparison submodule 111. Each counter (counter 112_1 to counter K 112_K) corresponds to at least one instruction memory address within the instruction memory address interval. When the instruction memory address received by the interval comparison submodule 111 from program counter 2 is within the instruction memory address interval, the interval comparison submodule 111 triggers the counter corresponding to the instruction memory address to accumulate performance signal counts, obtaining statistical values ​​of the performance signal associated with the instruction memory address. At least one count register is used, for example... Figure 3 The first count register 113_1, the second count register 113_2, ..., the Kth count register 113_K shown, at least one count register (the first count register 113_1 to the Kth count register 113_K) is coupled one-to-one to at least one counter (the first counter 112_1 to the Kth counter 112_K), for example... Figure 3 As shown, the first counter register 113_1 is coupled to the first counter 112_1, the second counter register 113_2 is coupled to the second counter 112_2, and so on, with the Kth counter register 113_K coupled to the Kth counter 112_K. Each of at least one counter register is used to temporarily store statistical values ​​of performance signals related to instruction memory addresses obtained from its corresponding coupled counter, for example... Figure 3As shown, the first counter register 113_1 is used to temporarily store the statistical values ​​of the performance signals related to the instruction memory address obtained by the first counter 112_1, the second counter register 113_2 is used to temporarily store the statistical values ​​of the performance signals related to the instruction memory address obtained by the second counter 112_2, and so on, the Kth counter register 113_K is used to temporarily store the statistical values ​​of the performance signals related to the instruction memory address obtained by the Kth counter 112_K. The write control module 13 is coupled to the counter registers in the performance statistics module 11 and is used to write the statistical values ​​of the performance signals related to the instruction memory address temporarily stored in the counter registers to the storage module. Specifically, the write control module 13 is coupled to the first counter register 113_1 to the Kth counter register 113_K and is used to write all the statistical values ​​of the performance signals related to the instruction memory address temporarily stored in the first counter register 113_1 to the Kth counter register 113_K to the storage module.

[0081] based on Figure 3 In the embodiment shown, each of the first counters 112_1 to the Kth counters 112_K is associated with a different instruction memory address. Therefore, the first counter registers 113_1 to the Kth counter registers 113_K temporarily store the statistical values ​​of the performance signals associated with the different instruction memory addresses associated with the first counters 112_1 to the Kth counters 112_K.

[0082] The performance counting device 100 of this disclosure can flexibly configure the instruction memory address range of the performance statistics module 11 through the configuration module 14, thereby further improving the flexibility of performance statistics configuration and meeting the performance statistics requirements of different application scenarios. In an illustrative embodiment, the configuration module 14 is used to configure the instruction memory address range of the performance statistics module 11 as follows: including at least two consecutive instruction memory addresses, or including at least two instruction memory addresses with a spanning interval step size.

[0083] In an illustrative embodiment, when the configuration module 14 configures the instruction memory address range of the performance statistics module 11 to include K consecutive instruction memory addresses, the statistical values ​​of the performance signals obtained by the first counter 112_1 to the Kth counter 112_K in the performance statistics module 11 are the statistical values ​​of the performance signals of the K consecutive instruction memory addresses.

[0084] In an illustrative embodiment, when the configuration module 14 configures the instruction memory address range of the performance statistics module 11 to include K instruction memory addresses with spanning interval steps, the statistical values ​​of the performance signals obtained by the first counter 112_1 to the Kth counter 112_K in the performance statistics module 11 are the statistical values ​​of the performance signals with spanning interval steps of the K instruction memory addresses.

[0085] It should be noted that the above example uses K instruction memory addresses. The performance statistics module 11 includes K counters, but the number of instruction memory addresses in the instruction memory address range configured for the performance statistics module 11 can be less than K. The K counters included in the performance statistics module 11 indicate that the maximum number of instruction memory addresses that the performance statistics module 11 can count is K, not that it can only count K instruction memory addresses. When the number of instruction memory addresses in the instruction memory address range configured for the performance statistics module 11 is less than K, the performance statistics module 11 only uses counters equivalent to the number of instruction memory addresses in the instruction memory address range to perform the corresponding performance signal statistics.

[0086] Based on the method of configuring hardware using registers, in the illustrative embodiment, the configuration module 14 may include a counting mode register, a start address register, an end address register, and an interval step register. The counting mode register is used to configure the counting mode of the instruction memory address range. The counting mode can be either a continuous range mode or a step mode. When the counting mode is continuous range mode, the instruction memory address range includes at least two consecutive instruction memory addresses. When the counting mode is step mode, the instruction memory address range includes at least two instruction memory addresses that span an interval step. The start address register is used to configure the start address of the instruction memory address range. The end address register is used to configure the end address of the instruction memory address range. The interval step register is used to configure the interval step when the counting mode is step mode.

[0087] In continuous range counting mode, the instruction memory address range can be determined by the values ​​of the start address register and the end address register. In this case, the instruction memory address range is a continuous interval of memory addresses. In step counting mode, the instruction memory address range is determined by the values ​​of the start address register, the end address register, and the step size register. In this case, the instruction memory address range is a discrete interval where the memory addresses are mutually discrete.

[0088] In the illustrative embodiment, the performance signal is a high-level signal triggered when the program segment whose performance is to be statistically analyzed enters the instruction memory address range. Using this method, the clock cycles consumed by a certain instruction (program segment) can be statistically analyzed (no performance signal is generated or it remains low when the program segment does not fall into the instruction memory address range; a high-level signal (i.e., performance signal) is generated when the program segment enters the instruction memory address range, triggered by the clock signal; the sum of the clock cycles maintained by the high-level signal (i.e., the statistical value) reflects the clock cycles consumed by the instruction (program segment)). This allows analysis of the time consumed by relevant instructions in the software. Based on corresponding filtering conditions, instructions with abnormal time consumption can be identified from the statistical results of all performance signals. Furthermore, by combining this with the corresponding thread bundle identifier and execution unit identifier, the instruction memory address of the abnormal instruction, the thread bundle containing the abnormal instruction, and the relevant execution unit executing the abnormal instruction can be located, thereby improving the accuracy of locating abnormal program segments (instructions).

[0089] To achieve a reasonable arrangement for the storage and dumping of statistical values ​​of performance signals of a large number of instruction memory addresses by the storage module 12, the storage module 12 uses storage slots to store the statistical values ​​of performance signals of instruction memory addresses in batches. The storage module 12 is divided into multiple storage slots according to the configuration. The statistical values ​​of performance signals of instruction memory addresses obtained at different times may be stored in different storage slots. In this way, when writing the statistical values ​​of performance signals of instruction memory addresses into a certain storage slot, the data in the storage slots where the statistical values ​​of performance signals of instruction memory addresses have already been written can be dumped to a data storage device other than the performance counting device 100, realizing uninterrupted cyclic storage of the storage module 12.

[0090] Based on this, in the illustrative embodiment, the configuration module 14 is further configured to configure the number of storage slots in the storage module 12. The write control module 13 is further configured to, according to the configuration of the number of storage slots in the storage module 12 by the configuration module 14, write the statistical value of the performance signal of at least one instruction memory address obtained by the performance statistics module 11 into the current storage slot of the storage module 12, and, after reaching (satisfying) the storage slot write transfer condition (reaching the storage slot write transfer condition can be understood as changing from a state where the storage slot write transfer condition is not met to a state where the storage slot write transfer condition is met), write the statistical value of the performance signal of at least one instruction memory address obtained by the performance statistics module 11 into the next storage slot. The storage slot write transfer condition includes at least one of the following: the write duration of the storage slot reaches a preset duration threshold, or the amount of data written to the storage slot reaches a preset data amount threshold.

[0091] Based on the method of configuring hardware using registers, in the illustrative embodiment, the configuration module 14 includes a memory slot quantity register. The memory slot quantity register is used to configure the number of memory slots in the memory module 12.

[0092] Figure 4 This is a schematic diagram of a third embodiment of a performance counting device, as shown in an illustrative embodiment. Figure 4 As shown, in order to control the data dumping in the storage module 12, in the illustrative embodiment, the performance counting device 100 of this disclosure further includes a readout control module 16. The readout control module 16 is coupled to the storage module 12 and the configuration module 14, and is used to periodically read out and dump the performance data (including statistical values ​​of performance signals for at least one instruction memory address) from the storage module 12 to a data storage device 3 outside the performance counting device 100 according to a configured dumping time interval. The configuration module 14 is also used to configure the dumping time interval.

[0093] Based on the method of configuring hardware using registers, in the illustrative embodiment, the configuration module 14 includes a dump time interval register. The dump time interval register is used to configure the dump time interval.

[0094] In practical applications, there are situations where performance counting is not performed, and there are also situations where only a small number of instruction memory address performance signals are statistically analyzed. Therefore, to save power, the configuration module 14 is also used to control the on / off state of each performance statistics module 11. When performance counting is not performed, all performance statistics modules 11 are turned off; when only a small number of instruction memory address performance signals are statistically analyzed, only a portion of the performance statistics modules 11 are turned on, thus achieving the goal of saving power.

[0095] Based on the method of configuring hardware using registers, in the illustrative embodiment, the configuration module 14 includes a switch control register. The switch control register is used to configure the switching of each performance statistics module 11.

[0096] In an illustrative embodiment, relevant configuration parameters can be written to the relevant registers in the configuration module 14 via software or a driver, and the performance counting device 100 can perform corresponding performance statistics based on the configuration parameters.

[0097] In a specific application scenario, the dump interval register can be named `Dump_interval_config`, used to configure the time interval for periodically dumping performance data from storage module 12 to external data storage device 3. The unit of the time interval is clock cycles. The bit width of the dump interval register can be set as needed; for example, it can be set to 14 bits. During configuration, the software or driver writes a 14-bit unsigned integer to the dump interval register, indicating how many clock cycles the performance data from storage module 12 will be dumped.

[0098] In a specific application scenario, the storage slot quantity register can be named Storage_slot_cnt, which is used to configure the number of storage slots in storage module 12. This distributes the limited resources of storage module 12 evenly among the storage slots to facilitate data dumping. The configuration value of the storage slot quantity register indicates the maximum number of dumped data blocks (storage slots) that can be cached. The bit width of the storage slot quantity register can be set as needed; for example, it can be set to 8 bits.

[0099] In a specific application scenario, the counting mode register can be named PC_dump_mode and used to configure the counting mode for the instruction memory address range. The bit width of the counting mode register can be set as needed; for example, the bit width can be set to 1.

[0100] In one application example, the counting mode register is configured to 0, indicating a continuous interval mode. In this mode, the instruction memory address interval of the performance statistics module 11 includes at least two consecutive instruction memory addresses. The start address register is configured with the start address of the instruction memory address interval, and the end address register is configured with the end address of the instruction memory address interval.

[0101] In one application example, the counting mode register is configured to 1, indicating step mode. In this mode, the instruction memory address range of the performance statistics module 11 includes at least two instruction memory addresses with a spanning interval step size. The start address register is configured with the start address of the instruction memory address range, the end address register is configured with the end address of the instruction memory address range, and the interval step size register is configured with the spanning interval step size between each instruction memory address in the instruction memory address range.

[0102] In a specific application scenario, the start address register can be named PC_min and used to configure the starting address of the instruction memory address range. The bit width of the start address register can be set as needed; for example, it can be set to 64 bits.

[0103] In a specific application scenario, the termination address register can be named PC_max, used to configure the termination address of the instruction memory address range. The bit width of the termination address register can be set as needed; for example, it can be set to 64 bits.

[0104] In a specific application scenario, the interval step register can be named PC_step and is used to configure the spanning interval step when the counting mode is in step mode. The value of the interval step register only takes effect when the value of the counting mode register is 1. The bit width of the interval step register can be set as needed; for example, the bit width can be set to 8.

[0105] In a specific application scenario, the switch control register can be named PFC_count_en, used to configure the switching of performance statistics module 11. The number of switch control registers depends on the number of performance statistics modules 11. For example, if the number of performance statistics modules 11 is N, then the number of switch control registers is N. Each switch control register is responsible for the switching of one performance statistics module 11. The bit width of the switch control register can be set to 1. When the value of the switch control register is 1, the corresponding performance statistics module 11 is started; when the value of the switch control register is 0, the corresponding performance statistics module 11 is turned off.

[0106] In a specific application scenario, the thread bundle identifier register can be named Warp_id and used to configure the thread bundle identifier. The number of thread bundle identifier registers depends on the number of performance statistics modules 11. For example, if the number of performance statistics modules 11 is N, then the number of thread bundle identifier registers is N, with each thread bundle identifier register corresponding one-to-one with each performance statistics module 11. The bit width of the thread bundle identifier register depends on the bit width of the thread bundle identifier.

[0107] In a specific application scenario, the execution unit identification number register can be named EU_id and used to configure the execution unit identification number. The number of execution unit identification number registers depends on the number of performance statistics modules 11. For example, if the number of performance statistics modules 11 is N, then the number of execution unit identification number registers is N, and each execution unit identification number register corresponds one-to-one with each performance statistics module 11. The bit width of the execution unit identification number register depends on the bit width of the execution unit identification number.

[0108] In the performance counting device 100, a crossbar switch module 15 is used to route the performance data of the multi-channel program counter 2 and distribute it to different performance statistics modules 11, thereby supporting concurrent statistics for the multi-channel program counter 2 (corresponding to multi-thread or multi-thread bundle). The write control module 13 writes the performance data of the corresponding configuration mode obtained by each performance statistics module 11 to the storage module 12, and the read control module 16 periodically reads the performance data in the storage module 12 and dumps it to the data storage device 3 outside the performance counting device 100 as the output of the performance statistics results.

[0109] The performance counting device 100 of this disclosure supports periodic dumps, and the time interval for each dump can be configured via a dump time interval register. The performance counting device 100 of this disclosure can also configure the number of storage slots in the storage module 12 via a storage slot quantity register. The performance counting device 100 can be configured with counting modes, including counting performance signals of consecutive instruction memory addresses from a configured start address to an end address, and counting performance signals of discrete instruction memory addresses spanning a specified interval step. When the value of the switch control register corresponding to a certain performance statistics module 11 is 1, the performance statistics module 11 counts; otherwise, it does not count. Flexible counting can be performed on specific program segments based on multiple execution unit identification numbers and thread bundle identification numbers configured by the configuration module 14.

[0110] Each performance statistics module 11 includes an interval comparison submodule 111, multiple counters, and a counting register for storing the counting results. The program counter 2, associated with the performance statistics module 11, inputs the instruction memory address to the performance statistics module 11 and counts based on performance signals. The interval comparison submodule 111 compares the instruction memory address input by the program counter 2 with the values ​​of the counting mode register, start address register, end address register, and interval step register configured by the configuration module 14. It determines whether the instruction memory address input by the program counter 2 falls within the instruction memory address interval determined by the values ​​of the counting mode register, start address register, end address register, and interval step register. When the instruction memory address input by the program counter 2 falls within the instruction memory address interval, the corresponding counter is triggered to start counting. This operation is performed for each instruction memory address input by the program counter 2. The counting results (statistical values) of each counter are temporarily stored in the corresponding counting register, awaiting writing to the storage module 12 by the write control module 13.

[0111] The performance counting device 100 of this disclosure mainly includes the following three working stages.

[0112] Phase 1: Configuration Phase (Initialization Phase).

[0113] The configuration information is written to the configuration module 14 through an external interface (such as a PCIe interface) using software or a driver (which may be software or a driver running on the central processing unit) to complete the parameter initialization of the performance counting device 100. Specific configuration actions are illustrated in the following example.

[0114] Write the dump interval to Dump_interval_config, which represents the number of processor clock cycles required to trigger a performance data dump; write the number of storage slots to Storage_slot_cnt, for example, writing 0x08, which means that storage module 12 can cache a maximum of 8 dump data blocks.

[0115] Write 0 or 1 to PC_dump_mode to specify the counting mode. If the specified counting mode is continuous range mode, write 0 to PC_dump_mode, and write the start address of the instruction memory address range to PC_min, for example, 0x0007FFF00001000, and write the end address of the instruction memory address range to PC_max, for example, 0x0007FFF00001FFF.

[0116] If the specified counting mode is step mode, write 1 to PC_dump_mode, write the starting address of the instruction memory address range to PC_min, and write the span interval step size to PC_step, such as 0x02. That is, select one instruction memory address every two instruction memory addresses, and the adjacent instruction memory addresses counted are separated by two instruction memory addresses that are not counted.

[0117] Each performance statistics module 11 corresponds to one thread bundle of one execution unit. The execution unit and thread bundle are determined by EU_id and Warp_id. The performance statistics module 11 includes K counters, which can support simultaneous counting of up to K instruction memory addresses. The instruction memory address corresponding to each counter is [PC_min + step]. k,PC_min+step (k+1)), where k∈0,1,…,K-1.

[0118] Writing at least one thread bundle identifier to Warp_id, for example, writing 0x000A, indicates that thread bundle identifier 10 is being analyzed. Writing an execution unit identifier to EU_id, for example, writing 0x0003, indicates that the instruction performance of execution unit 3 is being analyzed. Warp_id and EU_id together indicate the performance of execution unit 3 when executing thread bundle identifier 10.

[0119] Write 1 to PFC_count_en to start counting; write 0 to PFC_count_en to end counting.

[0120] Phase Two: Hardware Concurrency Statistics Phase (Execution Count Statistics Phase).

[0121] After the performance counting device 100 is initialized, it enters the real-time statistics stage. The hardware modules (cross switch module 15, performance statistics module 11, and interval comparison submodule 111) work automatically according to the configuration of the relevant registers in the configuration module 14.

[0122] The program counters 2 of multiple thread bundles within the processor input instruction memory addresses to the performance counting device 100 in real time. The cross-switch module 15 filters out the instruction memory addresses of the corresponding program counters 2 according to the configuration of Warp_id and EU_ID, and sends only the instruction memory addresses of program counters 2 that meet the conditions of Warp_id and EU_ID to the corresponding performance statistics module 11, so as to achieve accurate positioning and statistics for the specified Warp_id and EU_ID.

[0123] The interval comparison submodule 111 within the performance statistics module 11 compares the instruction memory address received from the crossbar switch module 15 with the instruction memory address range configured by PC_dump_mode, PC_min, PC_max, and PC_step in the configuration module 14.

[0124] In continuous interval mode (PC_dump_mode=0): if the received current instruction memory address is an address within the range of [PC_min, PC_max], the counter corresponding to the current instruction memory address is immediately triggered to start counting (e.g., the number of instruction executions, the number of clock cycles, etc.), and the counting of the counter corresponding to the current instruction memory address stops when the next instruction memory address is received.

[0125] In step-size mode (PC_dump_mode=1): If the received current instruction memory address falls within any discrete interval of PC_min, PC_min+PC_step, PC_min+2×PC_step…PC_min+(PC_count_times-1)×PC_step, the counter corresponding to the current instruction memory address is triggered to count, and the counting of the counter corresponding to the current instruction memory address stops when the next instruction memory address is received. Here, PC_count_times is the number of jumps, determined by PC_min, PC_max, and PC_step. (PC_count_times-1)×PC_step is within the range [PC_min, PC_max], while (PC_count_times)×PC_step is outside the range [PC_min, PC_max].

[0126] The K counters (1st counter 112_1 to Kth counter 112_K) within the performance statistics module 11 periodically package the K count results (statistical values ​​of performance signals for instruction memory addresses) and send them to the write control unit. In one embodiment, the write control unit polls, arbitrates, and processes the write requests from the N performance statistics modules 11 (1st counter 11_1 to Nth counter 11_N), and then writes the count results from each performance statistics module 11 into the storage area corresponding to each performance statistics module 11 in the storage module 12. When any performance statistics module 11 writes its count result to the storage module 12 again, it does not overwrite its previous count result in the corresponding storage area of ​​the storage module 12, but instead records the next count result after the storage location of its previous count result. The program counter 2 associated with the performance statistics module 11 counts and accumulates the performance signals of the corresponding program segment to obtain the statistical value of the performance signal, which can be post-processed by relevant software after being dumped to the external data storage device 3. In another embodiment, the write control module 13 first reads the counting result of the performance statistics module 11 and the counting result already stored in the storage module 12, adds them together, and then writes them to the storage module 12. This can save the internal storage space of the storage module 12.

[0127] Phase 3: Periodic Transfer Phase.

[0128] After configuration, if the performance statistics module 11 is enabled, the data in the storage module 12 will be automatically and periodically dumped to the external data storage device 3 via the read control module 16. The dumping from the storage module 12 to the external data storage device 3 will be automatically triggered according to the interval configured by `Dump_interval_config`. This process involves periodically dumping the performance data of N performance counting modules stored in the storage slots of the storage module 12 configured by `Storage_slot_cnt` to the external data storage device 3 and clearing the data in the storage slots to prevent counting errors caused by data overflow.

[0129] The performance counting device of this disclosure is flexible in configuration and highly adaptable, allowing for the configuration of multi-dimensional parameters and flexible adjustment according to different scenarios. When the instruction memory address received from the program counter enters the pre-configured instruction memory address range, the associated performance statistics module is triggered to perform statistical counting. The instruction memory address range can be configured as needed, and can be configured as a continuous range mode or a step mode as required. This allows for precise location of the instruction segment corresponding to the instruction memory address that has spent a relatively high absolute time or time percentage during program execution, thereby accurately locating the program performance bottleneck.

[0130] The performance counting device of this disclosure supports parallel statistics of multiple performance statistics modules, and can simultaneously count the program execution status of threads or thread bundles; and can configure the threads or thread bundles corresponding to each performance statistics module, so as to use fewer performance statistics modules to sample the program execution status of more threads or thread bundles through time-sharing multiplexing. For example, in a certain period of time, the performance statistics module is associated with a part of the program counter to sample the program execution status of a part of the threads or thread bundles, and in another period of time, the performance statistics module is associated with another part of the program counter to sample the program execution status of another part of the threads or thread bundles.

[0131] The counting results of each performance statistics module in the performance counting device of this disclosure are periodically written to the storage module. By configuring the write cycle to be less than the maximum count value of the counter, counter overflow can be avoided, thereby helping to achieve counter miniaturization. Furthermore, the data in the storage module is periodically dumped to an external data storage device according to the configuration. By configuring the dump cycle to be less than the time it takes for the storage module to be full, the storage module capacity can be miniaturized. This helps to reduce related hardware overhead and decrease the chip area occupied by the performance counting device of this disclosure.

[0132] In the illustrative embodiment, depending on the design, at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, cross switch module 15, interval comparison submodule 111, counter, count register, and read control module 16 can be implemented in a combination of multiple hardware, firmware, and software (i.e., program).

[0133] In hardware form, at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, crossbar switch module 15, interval comparison submodule 111, counter, count register, and readout control module 16 can be implemented as logic circuits on an integrated circuit. For example, the related functions of at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, crossbar switch module 15, interval comparison submodule 111, counter, count register, and readout control module 16 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The relevant functions of at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, cross switch module 15, interval comparison submodule 111, counter, count register, and read control module 16 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0134] In software or firmware form, the relevant functions of at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, crossbar switch module 15, interval comparison submodule 111, counter, count register, and readout control module 16 can be implemented as programming codes. For example, at least one of the performance statistics module 11, storage module 12, write control module 13, configuration module 14, crossbar switch module 15, interval comparison submodule 111, counter, count register, and readout control module 16 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. Electronic devices (such as CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute programming code from a non-transitory machine-readable storage medium to achieve at least one of the related functions of performance statistics module 11, storage module 12, write control module 13, configuration module 14, crossbar switch module 15, interval comparison submodule 111, counter, count register, and readout control module 16.

[0135] In the illustrative embodiments, the performance counting device of this disclosure is applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0136] In an illustrative embodiment, a chip is also provided that includes the performance counting device as described in any of the preceding embodiments.

[0137] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A performance counting device, characterized in that, include: A performance statistics module is used to receive at least one instruction memory address from the associated program counter, and to obtain statistical values ​​of the performance signals of the at least one instruction memory address located within the instruction memory address range based on the at least one instruction memory address and a pre-configured instruction memory address range. A storage module is used to store statistical values ​​of performance signals for at least one instruction memory address of the performance statistics module; A write control module, coupled to the performance statistics module and the storage module, is used to write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the storage module; A configuration module, coupled to the performance statistics module, is used to configure the instruction memory address range of the performance statistics module.

2. The performance counting device according to claim 1, characterized in that, The performance statistics module includes: An interval comparison submodule, coupled to the configuration module, is used to obtain the instruction memory address interval from the configuration module, receive the at least one instruction memory address from the program counter associated with the performance statistics module, and compare each received instruction memory address with the instruction memory address interval respectively. At least one counter is coupled to the interval comparison submodule, and the at least one counter corresponds to at least one instruction memory address in the instruction memory address interval. When the instruction memory address received by the interval comparison submodule from the program counter is within the instruction memory address interval, the interval comparison submodule triggers the counter corresponding to the instruction memory address to perform performance signal counting and accumulation to obtain a statistical value of the performance signal associated with the instruction memory address. At least one counting register is coupled one-to-one with the at least one counter, and each of the at least one counting registers is used to temporarily store statistical values ​​of performance signals associated with the instruction memory address obtained by the corresponding counter.

3. The performance counting device according to claim 1, characterized in that: The configuration module is configured to configure the instruction memory address range of the performance statistics module as follows: including at least two consecutive instruction memory addresses, or including at least two instruction memory addresses with a spanning interval step.

4. The performance counting device according to claim 3, characterized in that, The configuration module includes: A counting mode register is used to configure the counting mode of the instruction memory address range. The counting mode is either a continuous range mode or a step mode. When the counting mode is the continuous range mode, the instruction memory address range includes at least two instruction memory addresses that are consecutive. When the counting mode is the step mode, the instruction memory address range includes at least two instruction memory addresses that span an interval step. The start address register is used to configure the starting address of the instruction memory address range; Termination address register, used to configure the termination address of the instruction memory address range; An interval step register is used to configure the spanning interval step when the counting mode is the step mode.

5. The performance counting device according to claim 1, characterized in that: The performance signal is a high-level signal triggered when the program segment whose performance is to be statistically analyzed enters the instruction memory address range.

6. The performance counting device according to claim 1, characterized in that: The performance statistics module is at least one, and the program counter is at least one; The performance counting device further includes: A cross switch module, coupled to at least one of the performance statistics module and the configuration module, is used to establish an association between the performance statistics module and the program counter under the configuration of the configuration module; The configuration module is also used to configure thread bundle identifiers and execution unit identifiers, and associate the program counter containing the configured thread bundle identifiers and execution unit identifiers with the performance statistics module.

7. The performance counting device according to claim 6, characterized in that, The configuration module includes: Thread beam identifier register, used to configure the thread beam identifier; The execution unit identification number register is used to configure the execution unit identification number.

8. The performance counting device according to claim 1, characterized in that: The configuration module is also used to configure the number of storage slots in the storage module; The write control module is further configured to, according to the configuration of the number of storage slots of the storage module by the configuration module, write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the current storage slot of the storage module, and after the storage slot write transfer condition is reached, write the statistical value of the performance signal of the at least one instruction memory address obtained by the performance statistics module into the next storage slot. The write transfer conditions for the storage slot include at least one of the following: the write duration of the storage slot reaches a preset duration threshold, or the amount of data written to the storage slot reaches a preset data amount threshold.

9. The performance counting device according to claim 8, characterized in that, The configuration module includes: The storage slot quantity register is used to configure the number of storage slots in the storage module.

10. The performance counting device according to claim 1, characterized in that, The performance counting device further includes: A readout control module, coupled to the storage module and the configuration module, is used to periodically read out and dump the performance data in the storage module to a data storage device other than the performance counting device according to the configured dump time interval. The configuration module is also used to configure the dump time interval.

11. The performance counting device according to claim 10, characterized in that, The configuration module includes: A dump time interval register is used to configure the dump time interval.

12. The performance counting device according to claim 1, characterized in that, The configuration module includes: A switch control register is used to configure the switching of the performance statistics module.

13. A chip, characterized in that, Includes the performance counting device as described in any one of claims 1 to 12.

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