Layout violation repair guidance method and device, medium and product

Abstract

The invention relates to the field of integrated circuit design and photoetching manufacturing simulation, in particular to a layout violation repair guidance method, layout violation repair guidance equipment, a medium and a product. The layout violation repair guidance method comprises the following steps: inputting an initial layout and a physical design rule to be checked, dividing the initial layout into a plurality of layout blocks, and carrying out physical design rule checking on each layout block; if the design rule violation exists, analyzing graphic attributes around the violation to obtain the cause of the violation; and outputting violation repair guidance information according to the violation cause. And outputting violation repair guidance information of each layout block until all the layout blocks complete rule check. Wherein the graph attributes comprise fixed graphs, access paths of pins and ports, and a wiring network. The electronic equipment, the computer storage medium and the computer program product have the same beneficial effects as the layout violation repair guidance method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design and lithography manufacturing simulation, in particular to a layout violation repair guidance method, device, medium and product. BACKGROUND

[0002] In the field of integrated circuit design and lithography manufacturing simulation, as the feature size of integrated circuits continues to shrink, the process difficulty of integrated circuit manufacturing is increasingly high, and the process defects are also increasing; ultimately, in the integrated circuit lithography manufacturing process, the possibility of producing lithography bad points is also increasing; the lithography bad points will greatly reduce the manufacturing yield of the chip. Therefore, with the upgrading of the technology level of integrated circuit manufacturing process, that is, the gradual improvement of the manufacturing process node; based on the calculation of lithography mask optimization and the removal of lithography bad points becomes increasingly important.

[0003] Generally speaking, it is necessary to have the ability to detect and repair lithography bad points in the physical design and lithography simulation stage. Considering lithography bad points in the physical design stage is mainly to constrain the design through physical design rules, but physical design rules generally cannot avoid the appearance of lithography bad points in all cases. And if the rule is too tight, it will greatly increase the difficulty of design. In addition, as the physical design rules are updated with the shrinking of the technology node, as the technology node of integrated circuit continues to shrink, the size of the current device and the wire has reached the nanometer level, and the corresponding physical design rule is also increasingly complex. Therefore, it is difficult to completely solve the design rule violation through design tools automatically in the physical design stage, and engineers also have difficulty in solving these design rule violations by simply moving graphics.

[0004] Therefore, there is an urgent need for a solution that can detect the design violation of the current design layout in the physical design stage and provide a repair guidance method. SUMMARY

[0005] In order to solve the technical problem that it is difficult to completely solve the design rule violation in the physical design stage with the progress of the technology node of integrated circuit, the present application provides a layout violation repair guidance method, device, medium and product.

[0006] The technical problem solving scheme of the present application provides a layout violation repair guidance method, comprising the following steps: inputting an initial layout and at least one physical design rule to be checked; dividing the initial layout into a plurality of layout blocks, and performing physical design rule checking on each layout block; if there is a design rule violation, analyzing the graphic properties of the violation periphery to obtain the violation cause; according to the violation cause, output at least one violation repair guidance information; until all layout blocks are completed design rule checking, output the violation repair guidance information corresponding to each layout block; wherein the graphic properties include at least one of the following: fixed graphics, pin and port access path, wiring network.

[0007] Preferably, the layout blocks overlap each other.

[0008] Preferably, a design rule check is performed on each layout block based on a category of physical design rules, wherein the category of physical design rules comprises at least one of the following: a spacing rule, a width rule, a length rule, an interlayer association rule, and a via-related rule.

[0009] Preferably, the violation repair guidance information comprises violation condition information and repair suggestion information, wherein the violation condition information comprises at least one of the following: a category of the violation, a wiring layer to which the violation belongs, coordinates of the violation in the layout, a value required by a design rule corresponding to the violation, and an actual value causing the violation; and the repair suggestion information comprises at least one of the following: a cause of the violation and a specific repair suggestion.

[0010] Preferably, the cause of the violation is obtained by analyzing a graphic attribute of the violation periphery, comprising the following steps: if a fixed graphic exists in the periphery of the same layer as the violation, it is determined whether a size or a spacing of the fixed graphic conforms to a physical design rule, and if not, the cause of the violation is determined to be a layout planning error; if no fixed graphic exists in the periphery of the same layer as the violation, but a pin and / or a port exist in an upper layer and / or a lower layer of the violation, it is determined whether an access path of the pin and / or the port violates a physical design rule, and if so, the cause of the violation is determined to be a layout error; and if the cause of the violation is neither a layout planning error nor a layout error, the cause of the violation is determined to be a wiring error.

[0011] Preferably, when the cause of the violation is a layout planning error, the specific repair suggestion comprises at least one of the following: modifying a size of the fixed graphic, modifying a shape of the fixed graphic, and adjusting a position of the fixed graphic; when the cause of the violation is a layout error, the specific repair suggestion comprises at least one of the following: disabling a standard cell corresponding to the pin and / or the port causing the violation, and adjusting a position of the standard cell corresponding to the pin and / or the port causing the violation; and when the cause of the violation is a wiring error, a wiring network of the violation is analyzed, and the specific repair suggestion comprises at least one of the following: adding a wiring in the wiring network, modifying a size of an original wiring in the wiring network, deleting the original wiring in the wiring network, and replacing a via in the wiring network.

[0012] Preferably, if the wiring error involves multiple wiring networks, the determination of the specific repair suggestion comprises the following steps: selecting each wiring network as a candidate wiring network in turn, simulating modification of the candidate wiring network, verifying whether the modification can solve the wiring error and does not introduce other violations; if the verification passes, generating a specific repair suggestion for the candidate wiring network; if the verification fails, selecting the next associated wiring network as the candidate wiring network, and repeating the simulation modification and verification operations; if all wiring networks fail the verification, adding a no solution flag to the violation; after completing the analysis of all violations in a layout block, counting the total number of violations with the no solution flag in the layout block; if the total number exceeds a preset threshold, determining that the layout block is congested, and outputting a suggestion for adjusting the overall layout in the specific repair suggestion; wherein simulating modification of the candidate wiring network comprises modifying the size of the original wiring in the wiring network, deleting the original wiring in the wiring network, replacing the via in the wiring network, and moving the position of the via in the wiring network.

[0013] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the layout violation repair guidance method.

[0014] The application further provides a computer storage medium having computer program instructions stored thereon, wherein the computer program instructions are executed to implement the steps of the layout violation repair guidance method.

[0015] The application further provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the layout violation repair guidance method.

[0016] Compared with the prior art, the layout violation repair guidance method, device, medium, and product provided by the application have the following advantages: 1. The layout violation repair guidance method provided by the embodiment of the application overcomes the technical problem that it is difficult to completely solve design rule violations in the physical design stage as the integrated circuit technology node advances. Through the steps of the layout violation repair guidance method, design rule violations in a design layout can be comprehensively detected and analyzed according to given physical design rules, and accurate and effective repair suggestions can be provided, which is helpful for subsequent effective targeted repair of design rule violations.

[0017] Specifically, the initial layout is divided into multiple layout blocks, which guarantees the comprehensiveness of large-scale and complex layout analysis, and reduces the instantaneous requirement for hardware resources through block division.

[0018] And according to the graphic attribute analysis of the violation periphery to obtain the violation cause, the trigger source of the design rule violation is clear; Unlike the traditional design rule which only explains "where the violation occurs", the method further clearly points out "why the violation occurs", explains the cause of the violation from the root, effectively improves the repair success rate of the violation, and effectively reduces the trial and error cost and iteration time in the repair process.

[0019] Further, the violation repair guidance information is output according to the cause of the violation, specific repair directions and operation suggestions are provided, the dependence on artificial experience is reduced, and new violations caused by blind modification are effectively avoided.

[0020] In addition, the graphic attributes include fixed graphics, pin and port access paths, and wiring networks, systematical traceability of violation sources, establishment of hierarchical diagnostic logic from layout planning, layout to wiring, and prevention of violation recurrence from the source.

[0021] 2, The layout violation repair guidance method provided by the embodiment of the application divides the initial layout into a plurality of overlapping layout blocks, and through block overlap, it is ensured that the violation in the boundary area will not be missed.

[0022] 3, The layout violation repair guidance method provided by the embodiment of the application performs design rule checking on each layout block based on the types of physical design rules, and the types of physical design rules include: spacing rules, width rules, length rules, layer correlation rules, and via correlation rules. The classification checking mechanism can call the optimal checking algorithm according to the characteristics of different rule types, which significantly improves the checking efficiency. Especially in processing complex large-scale layout, it effectively avoids the problems of waste of system resources and low running efficiency caused by checking all rules at one time.

[0023] 4, The layout violation repair guidance method provided by the embodiment of the application, the violation repair guidance information includes violation condition information and repair suggestion information, which can quickly understand the essence of the violation and shorten the violation repair cycle; By outputting the type of violation, the wiring layer to which the violation belongs, the coordinates of the violation in the layout, the value required by the corresponding design rule of the violation and the actual value causing the violation, the type of violation and the location of the violation are clear, which can quickly locate the problem source and significantly reduce the violation investigation time. Further, the cause of the violation and the specific repair suggestion are output, the repair decision process is standardized, and the dependence on artificial is reduced.

[0024] 5、The layout violation repair guidance method provided by the embodiment of the present application can analyze the cause of violation layer by layer according to the graphic attribute, and establish a systematic diagnostic path from layout planning, unit layout to detailed routing. The layered and progressive violation root analysis method can accurately distinguish whether the violation is caused by early physical design defects or late specific routing, so that most violations can be solved in the first repair, which is different from the traditional repair-iteration checking cycle, and improves the success rate and overall efficiency of violation repair.

[0025] 6、The layout violation repair guidance method provided by the embodiment of the present application can convert the violation analysis into specific repair suggestions by establishing the mapping relationship between the violation cause and the repair operation, so that most violations can obtain the optimal repair path, which is different from the traditional iterative repair process, and improves the repair efficiency and success rate.

[0026] 7、The layout violation repair guidance method provided by the embodiment of the present application can ensure that the optimal repair scheme is found and no new violation is caused by trying to modify each related routing network one by one for complex violations involving multiple routing networks. When the repair of all routing networks fails, the violation is marked as unsolvable, and when the number of unsolvable marks in the layout area reaches a certain threshold, it is judged that there is a routing congestion problem in the area, and a suggestion of adjusting the overall layout is given. The time wasted on violations that cannot be solved locally is effectively avoided, the design resources are guided to the macro layout level that needs to be adjusted, and the processing efficiency of complex violations is significantly improved.

[0027] 8、The embodiment of the present application further provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the above layout violation repair guidance method.

[0028] It should be noted that the electronic device provided by the present application has the same beneficial effects as the above-mentioned layout violation repair guidance method, which will not be repeated here.

[0029] 9、The embodiment of the present application further provides a computer storage medium having computer program instructions stored thereon, wherein the computer program is executed to realize the steps of the above layout violation repair guidance method.

[0030] It should be noted that the computer readable storage medium provided by the present application has the same beneficial effects as the above-mentioned layout violation repair guidance method, which will not be repeated here.

[0031] 10、The embodiment of the present application further provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to realize the steps of the above layout violation repair guidance method.

[0032] It should be noted that the computer program product provided by the present application has the same beneficial effects as the above-mentioned layout violation repair guidance method, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0034] Figure 1 is a flowchart of steps S1 to S5 in a layout violation repair guidance method provided by an embodiment of the present application.

[0035] Figure 2 is a schematic diagram of dividing an initial layout into a plurality of layout blocks that overlap each other in a layout violation repair guidance method provided by an embodiment of the present application.

[0036] Figure 3 is a flowchart of judging violation causes in a layout violation repair guidance method provided by an embodiment of the present application.

[0037] Figure 4 is a flowchart of outputting specific repair suggestions according to violation causes in a layout violation repair method provided by an embodiment of the present application.

[0038] Figure 5 is a flowchart of steps S4a1-S4a6 in a layout violation repair method provided by an embodiment of the present application.

[0039] Figure 6 is a full flowchart of a layout violation repair method provided by an embodiment of the present application.

[0040] Figure 7 is a frame diagram of an electronic device provided by an embodiment of the present application.

[0041] Figure 8 is a frame diagram of a computer storage medium provided by an embodiment of the present application.

[0042] Figure 9 is a frame diagram of a computer program product provided by an embodiment of the present application.

[0043] BRIEF DESCRIPTION OF DRAWINGS 1. Electronic device; 11. Memory; 12. Processor; 2. Computer storage medium; 3. Computer program product; 100. Computer program; A, initial layout; A1, layout block; A2, layout block. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and should not be used to limit the present application.

[0045] In the embodiments provided by the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0046] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0047] In various embodiments of the present application, it should be understood that the size of the serial number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0048] The flowcharts and block diagrams in the drawings of the present application illustrate the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks can also occur in a different order from that indicated in the drawings. For example, two blocks indicated in succession can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0049] In the existing method of detecting and repairing design rule violations, the detection and repair of violations are often performed in the physical design stage. However, as the technology node of integrated circuits is continuously reduced, the physical design rules are updated, and the corresponding physical design rules are increasingly complex. At this time, it is difficult to completely solve the design rule violations in the physical design stage by using design tools automatically, and it is also difficult for engineers to solve these design rule violations by simply moving graphics.

[0050] In order to solve the technical problem that it is difficult to completely solve the design rule violations in the physical design stage as the technology node of integrated circuits advances, the present application provides a layout violation repair guidance method, device, medium and product.

[0051] First, please refer to Figure 1 The embodiment of the present application provides a layout violation repair guidance method, comprising the following steps: S1: inputting an initial layout and at least one physical design rule to be checked; S2: dividing the initial layout into a plurality of layout blocks, and performing physical design rule checking on each layout block; S3: if there is a design rule violation, analyzing the graphic properties around the violation to obtain the cause of the violation; S4: outputting at least one violation repair guidance suggestion according to the cause of the violation; S5: until all layout blocks are completed for design rule checking, outputting the violation repair guidance information corresponding to each layout block.

[0052] The embodiment of the present application provides a layout violation repair guidance method, which overcomes the technical problem that it is difficult to completely solve the design rule violations in the physical design stage as the technology node of integrated circuits advances. Through the steps of the layout violation repair guidance method, the design rule violations in the design layout can be detected and analyzed comprehensively according to the given physical design rules, and accurate and effective repair suggestions can be given, which is helpful for subsequent effective and targeted repair of design rule violations.

[0053] Specifically, the initial layout is divided into a plurality of layout blocks that overlap with each other, and through the block overlap, it is ensured that the violations in the boundary region will not be missed, and the comprehensiveness of large-scale and complex layout analysis is ensured, and the instantaneous requirement for hardware resources is reduced through block division.

[0054] The cause of the violation is obtained according to the graphic properties around the violation, and the trigger source of the design rule violation is determined. Unlike the traditional design rule which only indicates "where the violation occurs", the present method further analyzes and clearly indicates "why the violation occurs", explains the reason for the violation from the root source, effectively improves the repair success rate of the violation, and effectively reduces the trial and error cost and iteration time in the repair process.

[0055] Further, the violation repair guidance information is output according to the cause of the violation, clear and specific repair directions and operation suggestions are provided, the dependence on artificial experience is reduced, and new violations caused by blind modification are effectively avoided.

[0056] In addition, the graphic attributes include fixed graphics, access paths of pins and ports, and wiring networks. By analyzing the graphic attributes around the violation, systematic tracing of the root cause of the violation is realized; layered diagnostic logic from layout planning, layout to wiring is established to prevent recurrence of violations from the source.

[0057] The specific steps S1 to S5 of the layout violation repair guidance method will be described below.

[0058] First, in step S1, an initial layout and at least one physical design rule to be checked are input.

[0059] The initial layout is the layout output by the wiring tool based on physical design. At this time, the layout is in the physical design completion stage, and the standard cell layout and global wiring connection have been completed, but no design rule check and optimization has been performed. Understandably, although the initial layout meets the basic logical connection requirements, due to the limitations of automatic wiring tools and the complexity of the process, there may be undiscovered spacing, width violations and other physical defects. Therefore, it is necessary to perform a comprehensive physical design rule check on the initial layout.

[0060] In step S2, the initial layout is divided into multiple layout blocks, and a physical design rule check is performed on each layout block.

[0061] Understandably, dividing the initial layout into multiple layout blocks ensures the comprehensiveness of large-scale and complex layout analysis, and reduces the instantaneous requirement for hardware resources through block division.

[0062] In other embodiments, the layout blocks overlap each other.

[0063] Please refer to Figure 2 In a specific implementation, the initial layout A is divided into multiple layout blocks A1, A2, …; wherein the layout blocks overlap each other.

[0064] Specifically, the size of the overlapping area is related to the manufacturing process node; in some embodiments, the size of the overlapping area is divided into blocks based on the basic layout unit defined by the current manufacturing process as a reference scale.

[0065] In a specific embodiment, the initial layout is divided into square layout blocks with a side length of β*h, taking the standard cell height h as a reference scale, wherein two adjacent layout blocks are provided with an overlapping area with a width of 1*h, that is, there is a 1*h*β*h rectangular overlapping area between two adjacent layout blocks.

[0066] wherein the value of the parameter β is determined based on the manufacturing process node and the design size. In a specific embodiment, β∈[32, 64].

[0067] It can be understood that dividing the initial layout into a plurality of layout blocks and performing physical design rule checking on each layout block respectively can effectively reduce the data scale of a single execution during physical design rule checking and improve the checking speed. Further, the layout blocks overlap with each other, which can ensure that the checking of the boundaries of the layout blocks will not be missed when performing physical design rule checking on each layout block, avoiding the violation at the junction of the layout blocks from being ignored due to block checking. The comprehensiveness of large-scale and complex layout analysis is ensured, and the instantaneous requirement for hardware resources is reduced by dividing the initial layout.

[0068] In some embodiments, the design rule checking is performed on each layout block based on the types of physical design rules.

[0069] wherein the types of physical design rules can be divided into rule checking involving only a single pattern and rule checking among multiple patterns. Further, the rule checking of a single pattern includes width rule, area rule, and side length rule, etc.; and the rule checking among multiple patterns includes spacing rule, layer correlation rule, and via correlation rule, etc.

[0070] It can be understood that the design rule checking is performed on each layout block based on the types of physical design rules, which divides the complex full rule checking into single rule type checking according to width, spacing, etc. When a violation is found after the basic rule checking of a certain type is completed, the subsequent complex rule checking of the current layout block can be ended in advance, and the basic rule violation is repaired before further complex rule checking.

[0071] The design rule checking of the layout blocks according to the types of design rules can significantly improve the checking efficiency. Especially when dealing with complex large-scale layouts, it can effectively avoid the problems of waste of system resources and low running efficiency caused by checking all rules at once.

[0072] In step S3, if there is a design rule violation, the properties of the patterns around the violation are analyzed to obtain the cause of the violation.

[0073] wherein the pattern properties include at least one of the following: fixed patterns, access paths of pins and ports, and wiring networks.

[0074] Fixed pattern refers to patterns that cannot be modified by routing, including ports of each module, power and ground lines, routing guides, pins in standard cells, and obstructions, etc. These patterns are usually determined and placed in the layout stage of the floorplan.

[0075] Among them, the routing guide is a pre-defined geometric area or path used to guide the automated routing tool on how to connect a specific pin.

[0076] The access path of the pin and port refers to the geometric space that must be passed through or occupied in order to connect the metal routing to the specified pin or port. The analysis of the access path aims to determine whether there is enough routing resource to achieve a violation-free connection.

[0077] The routing network refers to a collection of patterns with the same electrical nodes connected by metal lines and vias in an integrated circuit layout.

[0078] Please refer to Figure 3 In some embodiments, the cause of the violation is obtained by analyzing the properties of the patterns around the violation, including the following steps: First, determine whether there are fixed patterns around the same layer of the violation. If there are, determine whether the size or spacing of the fixed patterns meets the physical design rules. If not, the cause of the violation is determined to be a floorplan error.

[0079] For example, if a violation of the width rule type is detected, it may be considered that the size or position of the fixed pattern connected by the routing is unreasonable, resulting in a violation of the physical design rules. For example, if a violation of the spacing rule type is detected, it may be considered that the distance between several fixed patterns is too close.

[0080] At this time, since the direct cause of the violation is a pattern element determined in the early stage of physical design and cannot be automatically corrected by subsequent processes, the cause of the violation is determined to be a floorplan error.

[0081] By preferentially determining whether the violation is a floorplan error, systematic defects caused by improper planning in the early stage of physical design can be eliminated from the root cause, avoiding ineffective local optimization in the subsequent layout and routing stage, and reducing the number of design iterations.

[0082] Further, if there are no fixed patterns around the same layer of the violation, but there are pins and / or ports on the upper and / or lower layers of the violation, determine whether the access path of the pin and / or port violates the physical design rules. If so, the cause of the violation is determined to be a layout error.

[0083] It should be noted that the pin and the port are also fixed patterns, but the judgment basis of the layout error is whether the access path of the pin and the port violates the rule, that is, whether the positional relationship between the pin and / or the port will cause a wiring error, rather than whether the size of the pin or port pattern itself violates the rule.

[0084] At this time, if the access path of the pin and / or the port itself violates the rule, it proves that there is a fundamental conflict in the relative position between the standard cells, which must be solved by adjusting the layout rather than local wiring.

[0085] In some embodiments, when there is no fixed pattern in the same layer periphery of the violation, but there is a pin and / or a port in the adjacent layer of the violation, it is considered whether the wiring pattern is not ready for pin access: whether the pins and / or ports in the adjacent layer of the violation can be accessed without violating the design rule, if not, the violation is determined as a layout error.

[0086] By further judging the access path of the pin and / or the port, it is determined whether the violation belongs to a layout error, effectively avoiding attributing the violation in the layout stage to the subsequent wiring stage, and ensuring the accuracy of the output of the subsequent violation repair guidance information.

[0087] Finally, when the cause of the violation is not a layout planning error or a layout error, the cause of the violation is determined as a wiring error.

[0088] At this time, since the layout planning error caused by the fixed pattern and the layout error caused by the access path of the pin and / or the port have been systematically excluded by the foregoing steps, the cause of the violation is attributed to the modifiable pattern generated by the wiring tool itself, that is, the current wiring network directly violates the physical design rule, and therefore it is determined as a wiring error.

[0089] According to the layer-by-layer analysis of the causes of the violation according to the pattern properties, a systematic diagnostic path from layout planning, cell layout to detailed wiring network is established. This hierarchical and progressive violation root analysis method can accurately distinguish whether the violation is caused by early physical design defects or late specific wiring; most violations can be solved in the first repair, which is different from the cycle of repair-iteration checking in the traditional method, and improves the success rate and overall efficiency of violation repair.

[0090] In step S4, at least one violation repair guidance suggestion is output according to the cause of the violation.

[0091] Please refer to Figure 4 When the cause of the violation is a layout planning error, the specific repair suggestions include at least one of the following: modifying the size of the fixed pattern, modifying the shape of the fixed pattern, adjusting the position of the fixed pattern.

[0092] Specifically, when the physical design rule involves a rule check of a single pattern, the specific repair suggestion is more inclined to adjust the fixed pattern itself, i.e., to modify the size or shape of the fixed pattern. When the physical design rule involves a rule check between multiple patterns, the specific repair suggestion is more inclined to adjust the position of the fixed pattern.

[0093] When the violation cause is a layout error, the specific repair suggestion includes at least one of the following: disabling the standard cell corresponding to the pin and / or port causing the violation, and adjusting the position of the standard cell corresponding to the pin and / or port causing the violation.

[0094] Specifically, there are two reasons for the violation of the pin and / or port access path: one is the conflict between the standard cell and the design rule, and the standard cell does not consider the planning of the routing path during design; at this time, only the standard cell corresponding to the pin and / or port causing the violation can be disabled. The second is that after some standard cells are placed together, the pins and / or ports at adjacent positions affect each other in position, causing normal routing to be impossible; at this time, the position between the two standard cells needs to be adjusted.

[0095] When the violation cause is a routing error, the specific repair suggestion includes at least one of the following: adding a routing in the routing network, modifying the size of the original routing in the routing network, deleting the original routing in the routing network, and replacing the via of the routing network.

[0096] In some embodiments, for a design rule violation involving only a single routing network, only how to adjust the current routing network needs to be considered. When the violation type is insufficient spacing or incomplete surrounding coverage, some routings that do not affect the connection relationship can be added to repair the violation. When the violation type is insufficient routing width or length exceeding the standard, the width, length, etc. of some routings can be modified, or some useless routings can be deleted. When the design rule violation is related to a via, such as insufficient spacing between the via and the adjacent routing, or the surrounding amount between via layers does not meet the requirements, the original via is replaced with a via that will not cause a design rule violation.

[0097] Please refer to Figure 5 In another embodiment of the present application, for a design rule violation involving multiple routing networks, the determination of the specific repair suggestion includes steps S4a1 to S4a6: S4a1: When the routing error involves multiple routing networks, each routing network is selected in turn as a candidate routing network, and modification of the candidate routing network is simulated; S4a2: Verify whether the modification in step S4a1 can solve the routing error and does not introduce other violations; S4a3: If the verification is passed, a specific repair suggestion for the candidate routing network is generated; S4a4: If the verification fails, the next associated routing network is selected as a candidate routing network, and the simulation modification and verification operations are repeated. S4a5: If all the routing networks involving routing violations in a layout block fail the verification, the violation is marked as no solution. S4a6: After analyzing all the violations in a layout block, the total number of violations with no solution mark in the layout block is counted. If the total number exceeds a preset threshold, it is determined that the layout block has routing congestion, and a suggestion for adjusting the overall layout layout is output in the specific repair suggestion.

[0098] The steps S4a1 to S4a6 will be described below.

[0099] First, in step S4a1, when the routing error involves multiple routing networks, each routing network is selected in turn as a candidate routing network, and the candidate routing network is simulated for modification.

[0100] Among them, simulating modification of the candidate routing network includes modifying the size of the original routing in the routing network, deleting the original routing in the routing network, replacing the via of the routing network, and moving the position of the via of the routing network.

[0101] In step S4a2, it is verified whether the modification in step S4a1 can solve the routing error without introducing other violations.

[0102] It can be understood that when the routing error involves multiple routing networks, the multiple routing networks involved will be analyzed separately. The simulation modification of the candidate routing network may obtain a modification suggestion to eliminate the routing error violation.

[0103] In step S4a3, if the verification passes, a specific repair suggestion for the candidate routing network is generated. At this time, the modification of the candidate routing network can eliminate the routing error, and the specific modification is stored as a specific repair suggestion, which is output as violation repair guidance information after analyzing all the routing networks involving routing violations in a layout block.

[0104] In step S4a4, if the verification fails, the next associated routing network is selected as a candidate routing network, and the S4a1-S4a2 operations are repeated.

[0105] In step S4a5, if all the routing networks involving routing violations in a layout block fail the verification, the violation is marked as no solution.

[0106] The no solution mark represents that the violation cannot be solved by any single, local routing modification under the local routing resources and layout constraints of the current layout. Its essence reveals that the violation is not an isolated routing error, but may be a manifestation of routing resource congestion.

[0107] In step S4a6, after analyzing all the violations in a layout block, the total number of violations with the no solution flag in the layout block is counted. If the total number exceeds a preset threshold, it is determined that the layout block has routing congestion, and a suggestion of adjusting the overall layout of the layout is output in the specific repair suggestion.

[0108] The preset threshold is a fixed value based on the manufacturing process node. In some specific embodiments, the preset threshold is generally ten times the number of routing layers that can be performed for the current process node. When the value is greater than 100, the preset threshold is 100.

[0109] It can be understood that when the number of no solution flags of the layout block is greater than the preset threshold, it indicates that the layout block has systematic congestion, rather than local congestion. At this time, whether the overall layout of the layout needs to be adjusted is considered by combining the bus length and congestion degree in the layout area.

[0110] By trying to modify each related routing network one by one, it is ensured that the optimal repair scheme is found and no new violation is caused. When the repair of all routing networks fails, the violation is added with the no solution flag, and when the number of no solution flags in the layout area reaches a certain threshold, it is determined that the area has routing congestion problem, and a suggestion of adjusting the overall layout of the layout is given. The time wasted on local violations that cannot be solved is effectively avoided, the design resources are guided to the macro layout level that needs to be adjusted, and the processing efficiency of complex violations is significantly improved.

[0111] Finally, in step S5, until all layout blocks complete the design rule check, the violation repair guidance information corresponding to each layout block is output.

[0112] In some embodiments, the violation repair guidance information includes violation condition information and repair suggestion information.

[0113] The violation condition information includes: the type of the violation, the routing layer to which the violation belongs, the coordinates of the violation in the layout, the value required by the design rule corresponding to the violation, and the actual value causing the violation.

[0114] The repair suggestion information includes the cause of the violation and the specific repair suggestion.

[0115] Outputting the violation repair guidance information in a standard format provides clear and structured problem positioning and repair basis, significantly improving the work efficiency from problem diagnosis to actual repair.

[0116] After performing steps S1-S5 on the initial layout, violation repair guidance information corresponding to each block of the initial layout will be output. Unlike traditional design rule checks that can only passively report the location and type of violations and cannot reveal the root cause of the problem, the layout violation repair guidance method provided in this embodiment of the invention transforms from traditional passive monitoring to proactive diagnosis and repair of violations. It explains the cause of violations from the root, effectively improving the success rate of violation repair and reducing the trial-and-error cost and iteration time in the repair process.

[0117] The layout violation repair guidance method provided in this embodiment of the invention solves the technical problem that, with the advancement of integrated circuit technology nodes, it is difficult to completely resolve design rule violations during the physical design stage.

[0118] Furthermore, in one specific embodiment, a chip of a specific specification is selected to verify the layout violation repair guidance method of the present invention. The core parameters of the chip are as follows: the chip area is 143991.00 μm2, it is designed using a 12nm process node, and it contains 62457 standard cells.

[0119] The verification process starts with the chip layout where the placement and routing tool has completed the initial routing, and compares the results along two paths: The first path is to use the layout violation repair guidance method provided in the embodiments of the present invention to first analyze the physical design rule violations of the initial layout, then modify the layout and repair the violations based on the analysis results, and finally continue to complete the subsequent routing based on the repaired layout.

[0120] The second approach: Using conventional methods, without performing any violation analysis or repair, we directly continue with the subsequent routing based on the initial layout.

[0121] The test results are shown in Table 1 below: Table 1. Comparison of photolithographic defect repair results using different routing tools

[0122] As shown in Table 1 above, after modifying the initial layout using the first path, the routing time was reduced by 51% compared to the second conventional path, and the proportion of design rule violations repaired was also significantly improved. Therefore, the layout violation repair guidance method provided in this embodiment of the invention is a practical and effective violation repair method, effectively improving the overall routing efficiency of the layout and the violation repair rate.

[0123] Please see Figure 7 The present invention also provides an electronic device 1, including a memory 11, a processor 12, and a computer program 100 stored on the memory 11. The processor 12 executes the computer program 100 to implement the steps of the above-described layout violation repair guidance method.

[0124] It is understood that when the electronic device 1 provided in the embodiments of the present invention is running, the layout violation repair guidance method described in the above embodiments can be implemented when the processor 12 executes the computer program 100. The electronic device 1 provided in the embodiments of the present invention has the same beneficial effects as the layout violation repair guidance method provided in the above embodiments.

[0125] In some embodiments, electronic device 1 is an electronic device applied in the field of integrated circuit design and photolithography manufacturing simulation, including but not limited to obtaining an initial layout, dividing the initial layout into multiple layout blocks, performing physical design rule checks on the layout blocks, determining the cause of violations, and outputting violation repair guidance information, etc., which will not be elaborated here. Theoretically, the method steps involved in the technical solution of this invention can all be implemented by electronic device 1, and the relevant parameters involved can also be adjusted by electronic device 1. Among them, the relevant parameters include but are not limited to preset command sets and preset option sets.

[0126] In some embodiments of the present invention, the processor 12 provided is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of this application.

[0127] In some embodiments, the method steps disclosed in this application may be executed by a hardware processor or by a combination of hardware and software modules in the processor 12.

[0128] Please see Figure 8 The present invention also provides a computer storage medium 2, on which a computer program 100 is stored, and the computer program 100 implements the steps of the above-described layout violation repair guidance method when executed by a processor.

[0129] Understandably, the computer storage medium 2 provided in the embodiments of the present invention stores a computer program 100, and the computer program 100 can be called by a processor to execute the layout violation repair guidance method described in the above embodiments.

[0130] It should be noted that the computer storage medium 2 provided in the embodiments of the present invention has the same beneficial effects as the layout violation repair guidance method provided in the above embodiments, and will not be described in detail here.

[0131] Specifically, the computer storage medium 2 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, disk, optical disk, etc.

[0132] In some embodiments, the computer storage medium 2 includes a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules.

[0133] Specifically, the computer storage medium 2 has storage space for computer programs 100 that perform any of the method steps in the above-described layout violation repair guidance method, and these programs can be read from or written to one or more computer program products.

[0134] In some embodiments, the computer program 100 is capable of compression in an appropriate form.

[0135] Please see Figure 9 The present invention also provides a computer program product 3, including a computer program 100, which implements the steps of the above-described layout violation repair guidance method when executed by a processor.

[0136] It is understood that the computer program product 3 provided in the embodiments of the present invention includes a computer program 100, and the computer program 100 can be called by a processor to execute the layout violation repair guidance method described in the above embodiments, which will not be repeated here.

[0137] The foregoing has provided a detailed description of the layout violation repair guidance method, equipment, medium, and product disclosed in the embodiments of the present invention. Specific examples have been used in this article to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention.

[0138] Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention. Any modifications, equivalent substitutions, and improvements made within the principles of this invention should be included within the protection scope of this invention.

Claims

1. A method for guiding the repair of map violations, characterized in that, Includes the following steps: Enter the initial layout and at least one physical design rule to be checked; The initial layout is divided into multiple layout blocks, and physical design rules are checked for each layout block. If a design rule violation exists, analyze the graphic attributes surrounding the violation to determine the cause of the violation; Based on the cause of the violation, output at least one violation repair guidance message; Until all layout blocks have completed design rule checks, output violation repair guidance information for each layout block; The graphic attributes include at least one of the following: fixed graphics, pin and port access paths, and wiring networks.

2. The method for guiding the repair of map violations as described in claim 1, characterized in that, The map blocks overlap with each other.

3. The method for guiding the repair of map violations as described in claim 1, characterized in that, Design rule checks are performed on each layout block based on the type of physical design rule. Among them, the types of physical design rules include at least one of the following: spacing rules, width rules, length rules, inter-layer association rules, and via-related rules.

4. The method for guiding the repair of map violations as described in claim 1, characterized in that, The violation repair guidance information includes violation details and repair suggestions. The violation information includes: the type of violation, the routing layer to which the violation belongs, the coordinates of the violation in the layout, the value required by the design rule corresponding to the violation, and the actual value that caused the violation; The repair suggestion information includes: the cause of the violation and specific repair suggestions.

5. The method for guiding the repair of map violations as described in claim 1, characterized in that, Analyze the graphic attributes surrounding the violation to determine the cause of the violation, including the following steps: If there are fixed graphics on the same floor as the violation, determine whether the size or spacing of the fixed graphics conforms to the physical design rules. If not, the cause of the violation is determined to be a layout planning error. If there are no fixed graphics on the same layer as the violation, but there are pins and / or ports on the upper and / or lower layers, then it is determined whether the access path of the pins and / or ports violates the physical design rules. If it does, the cause of the violation is determined to be a layout error. If the cause of the violation is not a layout planning error or a layout error, then the cause of the violation will be determined to be a wiring error.

6. The method for guiding the repair of map violations as described in claim 5, characterized in that, When the cause of the violation is a layout planning error, specific remedial suggestions include at least one of the following: modifying the size of the fixed graphic, modifying the shape of the fixed graphic, or adjusting the position of the fixed graphic. When the cause of the violation is a layout error, specific remedial recommendations include at least one of the following: disable the standard cell corresponding to the pin and / or port that caused the violation, or adjust the position of the standard cell corresponding to the pin and / or port that caused the violation. When the cause of the violation is a wiring error, analyze the wiring network of the violation. Specific repair suggestions include at least one of the following: add wiring to the wiring network, modify the size of the existing wiring in the wiring network, delete the existing wiring in the wiring network, or replace the wiring network vias.

7. The method for guiding the repair of map violations as described in claim 6, characterized in that, If the wiring error involves multiple wiring networks, the determination of the specific repair recommendations includes the following steps: Each routing network is selected sequentially as a candidate routing network, and the modification of the candidate routing network is simulated to verify whether the modification can resolve the routing error without introducing other violations. If the verification passes, specific repair recommendations for the candidate cabling network will be generated. If the verification fails, select the next associated cabling network as the candidate cabling network and repeat the above simulation modification and verification operations. If all cabling networks fail verification, then mark the violation as unsolvable. After analyzing all violations within a given map block, the total number of violations marked as unsolvable within that map block is counted. If the total number exceeds the preset threshold, it is determined that there is wiring congestion in the layout block, and the specific repair suggestion outputs a suggestion that the overall layout needs to be adjusted. The simulation of modifying candidate routing networks includes: modifying the size of existing routing in the routing network, deleting existing routing in the routing network, replacing routing network vias, and moving the position of routing network vias.

8. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout violation repair guidance method as described in any one of claims 1-7.

9. A computer storage medium, characterized in that: It stores computer program instructions, which, when executed, implement the layout violation repair guidance method as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, it implements the layout violation repair guidance method as described in any one of claims 1-7.

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