Airborne 1394 acquisition card and 1394 bus data acquisition method thereof

Abstract

The invention provides an airborne 1394 acquisition card and a 1394 bus data acquisition method thereof, relates to the technical field of avionics and data acquisition, and solves the problems that an existing 1394 acquisition card is large in size, poor in environmental adaptability, weak in data processing capacity and the like. In the system, an FPGA module provides a logic control algorithm for acquisition of 1394 bus data, and the logic control algorithm comprises receiving, filtering, pipeline caching, data caching, output control and output caching; in the external interface module, a parallel bus interface establishes parallel bus communication connection between the FPGA module and the main control board card, and the main control board card is configured with a 1394 acquisition card and receives 1394 bus data acquired by the 1394 acquisition card; and the 1394 bus interface establishes bus communication connection between the FPGA module and the airborne equipment, so that the FPGA module receives 1394 bus data input from the airborne equipment. According to the invention, 1394 bus data can be stably and reliably collected and recorded in an airborne environment.

Description

Technical Field

[0001] This invention relates to the field of avionics and data acquisition technology, specifically to an airborne 1394 data acquisition card and its 1394 bus data acquisition method. Background Technology

[0002] In modern avionics systems, high-speed and reliable data communication is crucial for ensuring flight safety and mission execution. As avionics systems become increasingly complex, higher demands are placed on the bandwidth, real-time performance, and reliability of bus communication. The IEEE 1394 bus, due to its high transmission rate, deterministic latency, and support for redundant topologies, has been widely used in airborne mission-critical systems, becoming a vital communication infrastructure for avionics networks. Against this backdrop, effective acquisition and recording of 1394 bus data is of great significance for system debugging, fault diagnosis, and post-event analysis.

[0003] To capture 1394 bus data, existing technologies typically employ dedicated 1394 data acquisition cards. These devices are mostly designed based on general-purpose computer platforms, connecting to industrial control hosts via standard expansion interfaces such as PCI to perform data reception, buffering, and storage functions. However, this approach has revealed several limitations in practical applications. It relies on a traditional plug-in card structure, resulting in a large physical size that struggles to meet the stringent space requirements of airborne environments. Furthermore, the use of mechanical connections such as gold fingers makes them prone to poor contact or even failure under conditions of strong vibration and high impact during flight, compromising reliability. Most existing data acquisition cards lack real-time filtering and time synchronization capabilities for bus data, leading to massive amounts of acquired data and redundant information, hindering efficient subsequent analysis.

[0004] For data processing, current 1394 acquisition devices typically only perform pass-through or simple buffering of raw data, lacking the ability to intelligently filter, classify, and precisely time-stamp data streams at the board level. This results in a large amount of invalid or duplicate data being recorded, not only consuming valuable storage resources but also increasing the burden on the host computer for later processing. Furthermore, due to the lack of an efficient collaboration mechanism with the system's main control unit, existing acquisition cards also suffer from deficiencies in configuration flexibility, timeliness of status feedback, and data upload efficiency, making it difficult to adapt to the dynamic adjustment requirements of complex avionics systems during the acquisition process.

[0005] Although the 1394 bus has been widely used in avionics, the data acquisition methods associated with it still suffer from problems such as large size, poor environmental adaptability, and weak data processing capabilities. In particular, they struggle to meet the comprehensive requirements of airborne platforms for miniaturized, highly reliable, and intelligent data acquisition. Therefore, a new 1394 acquisition solution is urgently needed that can integrate efficient data preprocessing and time synchronization mechanisms while ensuring high reliability, and improve overall acquisition efficiency through optimized system architecture, thereby better supporting the testing, verification, operation, and maintenance needs of avionics systems. Summary of the Invention

[0006] The purpose of this invention is to address the limitations of existing 1394 data acquisition cards, such as large size, poor environmental adaptability, and weak data processing capabilities. Therefore, an airborne 1394 data acquisition card and its 1394 bus data acquisition method are proposed. The acquisition card of this invention can communicate with the main control board via one parallel bus interface and has one 1394 bus data acquisition interface. It can filter and process 1394 bus data, and perform time stamping on the acquired data, thereby enabling stable and reliable acquisition and recording of 1394 bus data in an airborne environment.

[0007] The present invention employs the following technical solutions to achieve its objective: An airborne 1394 data acquisition card includes an FPGA module and an external interface module. The FPGA module provides logic control algorithms for acquiring 1394 bus data, including 1394 bus data reception, filtering, pipeline buffering, data buffering, output control, and output buffering. The external interface module includes a parallel bus interface and a 1394 bus interface. The parallel bus interface is used to establish a parallel bus communication connection between the FPGA module and a main control board. The main control board is used to configure the 1394 data acquisition card and receive the 1394 bus data it acquires. The 1394 bus interface is used to establish a bus communication connection between the FPGA module and airborne equipment, enabling the FPGA module to receive 1394 bus data input from the airborne equipment.

[0008] Specifically, between the 1394 bus interface and the FPGA module, starting from the FPGA module, a 1394 LLC, a 1394 PHY, and a transformer are sequentially connected. The 1394 LLC provides link-layer control functions between the FPGA module and the 1394 PHY, completing data frame encapsulation and parsing, protocol conversion between the transaction layer and the link layer, and coordinating bus arbitration, asynchronous and isochronous data transmission. The 1394 PHY implements the signal transmission and reception functions of the 1394 bus physical layer, converting digital logic signals from the 1394 LLC into differential analog signals conforming to the IEEE 1394 standard for transmission, and simultaneously receiving differential analog signals on the bus and converting them into digital signals to be transmitted back to the 1394 LLC. The transformer provides AC coupling and electrical isolation between the 1394 PHY and the external 1394 bus.

[0009] Specifically, the FPGA module is also connected to an FPGA configuration circuit via an SPI bus; the FPGA configuration circuit is composed of Nor Flash, and when the 1394 acquisition card is powered on, the FPGA configuration data is read from the Nor Flash and loaded into the FPGA module.

[0010] Furthermore, the FPGA module receives 1394 bus data via its built-in 1394 receiving module. This module receives 1394 bus data from the 1394 bus interface, performs clock conversion, and then buffers the data. The module also divides the filtering conditions corresponding to the 1394 bus data into a preset number of portions and stores the data in a corresponding number of buffers, allowing for parallel execution during filtering. Additionally, when storing the 1394 bus data in the buffer, the module adds a corresponding timestamp. It reserves a preset number of data bits in the first buffer space corresponding to this buffer for the timestamp information, writes the subsequent data frame content first, and then writes the timestamp information.

[0011] Furthermore, the FPGA module filters the 1394 bus data using its built-in filtering module. This filtering module determines the filtering conditions corresponding to the 1394 bus data and, based on the information FIFOs corresponding to each buffer space in the 1394 receiving module, determines whether there is a stored value. It then activates the corresponding state machine, retrieves values ​​from the data FIFOs of each buffer space, and retrieves values ​​from a preset filtering buffer, comparing and filtering the two values. The filtering conditions determined by the filtering module include: channel number, message ID, and a preset number of filtering comparison data from the filtering buffer.

[0012] Furthermore, the FPGA module's pipeline caching of 1394 bus data is performed by its built-in pipeline caching module. The pipeline caching module is used to put the filtered 1394 bus data into the RAM cache space according to the input signal indication of the filtering module. The pipeline caching module is also used to extract and lock the pipeline number to be stored when acquiring data frame content. After storing the channel number, timestamp, and data frame content corresponding to the latched 1394 bus data into the RAM cache space, it extracts the corresponding value of the 1394 bus data according to the BMC information from the main control board and stores it into the corresponding position in the data cache 0 of the data cache module in the FPGA module.

[0013] Furthermore, the FPGA module caches the 1394 bus data using its built-in data cache module. The data cache module extracts the pipe number corresponding to the 1394 bus data from the pipe cache module, extracts the initial cache position of the BMC information based on the pipe number, thereby obtaining the BMC information. Then, based on the BMC information, it extracts the 1394 bus data already stored in the corresponding position in data cache 0, refreshes the 1394 bus data in data cache 0 to its own built-in data cache 1 through a preset periodic signal, and updates the corresponding status information.

[0014] Furthermore, the FPGA module controls the output of 1394 bus data by its built-in output control module; the output control module is used to extract the corresponding 1394 bus data from the data cache 1 of the data cache module according to the conditions in the BMC information, and output it to the output cache module of the FPGA module.

[0015] Furthermore, the FPGA module's output buffer for 1394 bus data is handled by its built-in output buffer module. This output buffer module reads the 1394 bus data transmitted by the output control module and outputs it to the main control board via the parallel bus interface. The output buffer module has a preset depth output buffer area used to buffer the 1394 bus data transmitted by the output control module, and it uses a ping-pong operation method for data reading. The control state machine of the output buffer module uses a write signal as a state transition indicator signal, and a read signal to perform an operation in another state, thereby reading the 1394 bus data from the output buffer area.

[0016] This invention also provides a 1394 bus data acquisition method based on the aforementioned airborne 1394 acquisition card, the method comprising the following steps: S1. Receive 1394 bus data from airborne equipment, convert it to a clock, add the corresponding timestamp, and cache it in the first cache space; S2. According to the preset filtering conditions, retrieve the value from the first cache space and compare and filter it. Put the filtered 1394 bus data into the RAM cache space and determine the corresponding pipe number. S3. Based on the BMC information from the main control board, extract the corresponding value of the 1394 bus data and store it in the corresponding position of data cache 0. S4. Using a preset periodic signal, refresh the 1394 bus data in data buffer 0 to data buffer 1, and update the corresponding status information. S5. Extract the corresponding 1394 bus data from data buffer 1, store it in the output buffer area, and then send the acquired and processed 1394 bus data to the main control board using a ping-pong operation.

[0017] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows: The airborne 1394 data acquisition card of this invention has a compact structure and can be built into a dedicated chassis, significantly improving the overall system's vibration and shock resistance, and meeting the stringent requirements of airborne platforms for high reliability and environmental adaptability. Based on a programmable logic architecture, this acquisition card has the ability to filter and select 1394 bus data in real time at the board level. It can eliminate redundant or irrelevant information according to preset rules, greatly reducing the amount of invalid data and improving storage and transmission efficiency. Simultaneously, the data processing process can add a high-precision time stamp to each valid data entry, ensuring the accuracy of data timing relationships and providing a reliable basis for subsequent post-analysis, fault location, and system simulation.

[0018] By integrating a dedicated parallel bus interface and working efficiently with the main control board, the airborne 1394 data acquisition card of this invention can quickly complete initialization configuration after power-on and achieve low-latency, high-bandwidth data upload during operation. This tightly coupled internal communication mechanism avoids dependence on external host resources, enhances the system's independence and response speed, and is particularly suitable for field or embedded testing scenarios.

[0019] This invention balances miniaturization, modularity, and functional integrity, significantly reducing hardware size without sacrificing performance, facilitating deployment in space-constrained airborne environments. Furthermore, the co-design of hardware and software allows for flexible adjustment of the acquisition strategy, adapting to the varying data granularity and acquisition focus requirements of different mission phases. This invention not only improves the reliability and intelligence of 1394 bus data acquisition but also provides an efficient, stable, and easily integrated technical means for avionics system testing and verification, demonstrating promising engineering application prospects. Attached Figure Description

[0020] The present invention is further described in detail with reference to the following figures, which include 11 figures as follows: Figure 1 This is a schematic diagram of the composition structure of the airborne 1394 data acquisition card of the present invention; Figure 2 This is a block diagram of the system interconnection components of the acquisition card of the present invention; Figure 3 This is a schematic diagram of the overall functional flow of the data acquisition card of the present invention; Figure 4 This is a schematic block diagram of the 1394 receiving module in the acquisition card of the present invention; Figure 5 This is a schematic block diagram of the filtering module in the data acquisition card of the present invention; Figure 6 This is a schematic diagram of the state machine of the filtering module in the data acquisition card of the present invention; Figure 7 This is a schematic block diagram of the pipeline buffer module in the acquisition card of the present invention; Figure 8 This is a schematic block diagram of the data caching module in the acquisition card of the present invention; Figure 9 This is a schematic block diagram of the output control module in the acquisition card of the present invention; Figure 10 This is a schematic diagram of the control state machine principle of the output control module in the acquisition card of the present invention; Figure 11 This is a schematic diagram of the control state machine principle of the output buffer module in the acquisition card of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] Example 1 like Figure 1As shown, an airborne 1394 data acquisition card includes an FPGA module and an external interface module. The FPGA module provides logic control algorithms for acquiring 1394 bus data, including 1394 bus data reception, filtering, pipeline buffering, data buffering, output control, and output buffering. The external interface module includes a parallel bus interface and a 1394 bus interface. The parallel bus interface establishes a parallel bus communication connection between the FPGA module and the main control board, which configures the 1394 data acquisition card and receives the acquired 1394 bus data. The 1394 bus interface establishes a bus communication connection between the FPGA module and the airborne equipment, enabling the FPGA module to receive 1394 bus data input from the airborne equipment.

[0024] In this embodiment, as Figure 2 As shown, the 1394 acquisition card is built into the data acquisition and analysis chassis. After the chassis is powered on, the main control board completes the initialization configuration of the 1394 acquisition card through the internal parallel bus. After the configuration is completed, the 1394 acquisition card will filter and acquire the bus data connected to the board, and then upload the acquired data to the main control board through the internal parallel bus of the chassis. The main control board forwards the acquired data to the host computer through the network connection to complete the acquisition, storage, and subsequent analysis.

[0025] In this embodiment, the main body of the board containing the FPGA module is preferably 72mm×76mm, and the interface signal adapter board with external interfaces is 61mm×14mm in size.

[0026] In this embodiment, as Figure 1 As shown, between the 1394 bus interface and the FPGA module, starting from the FPGA module, there are also 1394 LLC, 1394 PHY and transformer connected in sequence. The 1394 LLC provides link layer control functions between the FPGA module and the 1394 PHY, completes the encapsulation and parsing of data frames, the protocol conversion between the transaction layer and the link layer, and coordinates bus arbitration, asynchronous and isochronous data transmission to support the FPGA module's efficient access and control of 1394 bus data.

[0027] The 1394 PHY implements the signal transmission and reception functions of the 1394 bus physical layer. It converts digital logic signals from the 1394 LLC into differential analog signals conforming to the IEEE 1394 standard for transmission, and simultaneously receives differential analog signals on the bus and converts them into digital signals to be transmitted back to the 1394 LLC, thus completing the physical connection and electrical isolation between nodes.

[0028] The transformer provides AC coupling and electrical isolation between the 1394 PHY and the external 1394 bus, suppresses common-mode interference, blocks DC components, and ensures signal integrity and immunity during long-distance transmission, thereby improving the communication reliability of the entire 1394 interface in complex airborne electromagnetic environments.

[0029] In this embodiment, the data acquisition and analysis chassis provides a +5V power supply to the acquisition card, which, after passing through a DC / DC power module, outputs 1.2V, 2.5V, and 3.3V power to the FPGA module and related components. The clock required for the 1394 PHY can be directly provided by a crystal oscillator. The clock required for parallel bus data sampling via the parallel bus interface is directly provided to the acquisition card by the main control board. The parallel bus interface communicates and interacts with the main control board; its interface can be implemented by the internal IP core of the main control board, without the need for additional components, effectively reducing the overall size of the acquisition card.

[0030] In this embodiment, when using the aforementioned airborne 1394 acquisition card, after the 1394 bus data is received, in order to reduce the filtering time, the data is synchronously cached into 10 first cache spaces for caching. At the same time, a corresponding number of filtering modules are configured, so that the overall filtering time can be compressed by 10 times. According to the filtering conditions in the BMC information issued by the main control board, the correct data frame information can be filtered out, and the corresponding channel number, timestamp, data frame content, etc. are stored in the RAM of the pipeline cache.

[0031] Subsequently, based on the BMC information sent by the main control board, the pipeline buffer places the stored 1394 bus data into data buffer 0, and retrieves the data from data buffer 0 into data buffer 1 according to a preset clock cycle. The output control then retrieves the value from data buffer 1 based on the BMC information, buffers it in the output buffer, and sends the retrieved 1394 bus data to the main control board in a ping-pong manner, thus realizing the data acquisition function of the acquisition card. The overall functional flow of the airborne 1394 acquisition card can be found in [link to relevant documentation]. Figure 3 The illustration.

[0032] Example 2 Based on Example 1, this example describes in detail the acquisition and processing process of 1394 bus data by its FPGA module, which corresponds to six parts: receiving, filtering, pipeline buffering, data buffering, output control, and output buffering.

[0033] In this embodiment, the FPGA module receives 1394 bus data through its built-in 1394 receiver module, as can be seen in [reference needed]. Figure 4The module diagram is shown below. After receiving 1394 bus data from the 1394 bus interface, the 1394 receiving module performs clock conversion via the dm_intf_rx module and then buffers the data in the l1394_pkt_chk module. Because there are many filtering conditions, to prevent all filtering conditions from being completed before the next frame of 1394 bus data arrives, this embodiment divides the filtering conditions corresponding to the 1394 bus data into 10 parts and stores the 1394 bus data in 10 buffers, thus allowing parallel execution when filtering begins.

[0034] In this embodiment, when storing 1394 bus data in the cache, a corresponding timestamp is added. After subsequent filtering, the entire frame data, including the data frame content and the timestamp, will enter the RAM cache space of the pipeline cache. When 1394 bus data is cached in the first cache space, the data frame content is written first, and when the end of the frame is detected, the timestamp information is written. The timestamp information needs to be placed in the first 8 data bits of the first cache space, and the data frame content is arranged sequentially afterward. Therefore, when writing the data frame content first, the data bits required for the timestamp information need to be reserved.

[0035] In this embodiment, the FPGA module filters the 1394 bus data using its built-in filtering module, which can be found in [reference needed]. Figure 5 The module diagram is shown below. Specific filtering conditions are shown in Table 1.

[0036] Table 1. Filtering Conditions Diagram

[0037] In this embodiment, the filtering module determines the filtering conditions corresponding to the 1394 bus data, and determines whether there is a stored value based on the information FIFO corresponding to each buffer space in the 1394 receiving module, and then starts the corresponding state machine, which can be referred to as [reference needed]. Figure 6 The diagram illustrates that values ​​are retrieved from the data FIFO of each cache space and from the preset filter cache, and the two values ​​are compared and filtered.

[0038] In this embodiment, the filtering conditions for each frame of 1394 bus data are eight: channel number, message ID, and six sets of filtering comparison data from the filtering cache, namely compare_data1 to compare_data6. The channel number occupies 16 bits, the message ID occupies 32 bits, and each of the six sets of filtering comparison data consists of five parameters, occupying 5 × 16 bits. Considering the efficiency of the filtering comparison data, the five parameters are concatenated into one data set, resulting in faster extraction of the corresponding set of filtering comparison data; this design occupies 80 bits at the maximum bit width.

[0039] In this embodiment, the FPGA module's pipe buffering of 1394 bus data is performed by its built-in pipe buffering module, which can be referred to as... Figure 7 The module diagram illustrates the process. The pipe buffer module, based on the input signal `flt_done_pos` from the filtering module, places the filtered 1394 bus data into the RAM buffer space. The pipe buffer module also extracts and locks the pipe number to be stored when acquiring the data frame content. After storing the channel number, timestamp, and data frame content corresponding to the latched 1394 bus data into the RAM buffer space, it extracts the corresponding value of the 1394 bus data based on the BMC information from the main control board and stores it into the corresponding position in the data buffer 0 (i.e., Data_Buffer_0 in the diagram) of the data buffer module in the FPGA module.

[0040] In this embodiment, the FPGA module's data caching of the 1394 bus data is performed by its built-in data caching module, which can be found in [reference]. Figure 8 The module diagram is shown below. The data cache module extracts the pipe number corresponding to the 1394 bus data from the pipe cache module, extracts the initial cache position of the BMC information based on the pipe number, and then obtains the BMC information. Based on the BMC information, it extracts the 1394 bus data already stored in the corresponding position in data cache 0, and refreshes the 1394 bus data in data cache 0 to its own built-in data cache 1 (i.e., Data_Buffer_1 in the figure) through a preset periodic signal, and updates the corresponding status information.

[0041] In this embodiment, the FPGA module's output control of 1394 bus data is performed by its built-in output control module, which can be referred to... Figure 9 The module diagram is shown below. Based on the conditions in the BMC information, the output control module extracts the corresponding 1394 bus data from the data buffer 1 of the data buffer module and outputs it to the output buffer module of the FPGA module.

[0042] In this embodiment, a set of parameter information is obtained for each pipe. Each set contains four types of parameters, as follows: parser_num (number of arguments); smallperiodoffset, (repeated transmission)length(2N) / interval (subtransmission is only sent once); pip_en (pipe enable), pip_buffer_offset; super_tx (hypertransfer flag), increase, out_buffer_offset.

[0043] Because there is a two-cycle delay in the buffered output of parameters, a certain period of waiting is required in the GET_PARMT state. A state transition can occur when the first parameter, i.e., the number of parameters, is obtained; therefore, the control state machine of the output control module can proceed according to... Figure 10 The settings are based on the principle of [the principle of setting up].

[0044] In this embodiment, the FPGA module's output buffer for 1394 bus data is handled by its built-in output buffer module. The output buffer module reads the 1394 bus data transmitted by the output control module and outputs it to the main control board via a parallel bus interface. The output buffer module has a preset depth output buffer area that buffers the 1394 bus data transmitted by the output control module and uses a ping-pong operation method for data reading. The control state machine of the output buffer module uses the write signal as a state transition indicator signal, and the read signal is used to operate in another state, thereby reading the 1394 bus data from the output buffer area.

[0045] The backplane bus bridge of the acquisition card reads data from the output buffer and sends it to the backplane bus, which then transmits it to the main control board via the parallel bus interface. In this embodiment, the depth of the output buffer is 512, and the read address is BUFF_OFFSET_OUT. In the ping-pong operation mode used when reading from the output buffer, the read enable signal can be directly set to 0, meaning consistent output but the bus operation will read the correct result.

[0046] The control state machine of the output buffer module itself can be found here. Figure 11 The diagram illustrates that syn1 is a small-cycle signal, and each cycle operation begins based on the small-cycle signal.

[0047] Example 3 Based on any of the above embodiments, this embodiment provides a 1394 bus data acquisition method, the hardware basis of which is the airborne 1394 acquisition card in embodiment 1 or 2; the method includes the following steps: S1. Receive 1394 bus data from airborne equipment, convert it to a clock, add the corresponding timestamp, and cache it in the first cache space; S2. According to the preset filtering conditions, retrieve the value from the first cache space and compare and filter it. Put the filtered 1394 bus data into the RAM cache space and determine the corresponding pipe number. S3. Based on the BMC information from the main control board, extract the corresponding value of the 1394 bus data and store it in the corresponding position of data cache 0. S4. Using a preset periodic signal, refresh the 1394 bus data in data buffer 0 to data buffer 1, and update the corresponding status information. S5. Extract the corresponding 1394 bus data from data buffer 1, store it in the output buffer area, and then send the acquired and processed 1394 bus data to the main control board using a ping-pong operation.

[0048] When the above steps are applied to the onboard 1394 data acquisition card, the resulting 1394 bus data acquisition system first receives 1394 bus data from the onboard device. After receiving the raw data stream, it performs clock domain conversion to match the operating clock of the internal processing logic. Subsequently, upon detecting the end of a complete data frame, a precise timestamp is appended to the frame, and the entire frame data, along with the timestamp, is written to the first-level buffer space. To ensure that the timestamp is correctly placed, a storage area for storing the timestamp must be reserved at the beginning of the buffer when writing the main content of the data frame.

[0049] The system filters data in the cache based on a pre-defined set of filtering conditions. These conditions include channel identifiers, message identifiers, and multiple sets of configurable comparison parameters to determine whether the current frame belongs to the target data that needs to be retained. To improve processing efficiency, the system employs a parallel mechanism, distributing the data to be filtered to multiple cache paths and simultaneously initiating multiple comparison operations. Once the filtering is complete, data frames that meet the requirements, along with their timestamps, are sent to a RAM-based pipeline cache area, during which the logical pipeline number to which the frame should belong is determined.

[0050] The system combines BMC control information from the main control board to parse the configuration parameters related to the current pipeline. Using these parameters, the system locates the corresponding position in data buffer 0 and accurately writes the filtered and pipeline-assigned 1394 bus data to that position. This process achieves dynamic binding between the acquired data and the upper-level control strategy, ensuring that subsequent processing can be invoked as needed.

[0051] Based on this, the system periodically migrates valid data written in data cache 0 to data cache 1 via a periodic trigger signal. This refresh operation not only completes the secondary temporary storage of data, but also synchronously updates the status flags related to the data, such as whether it is ready or has been read, thereby providing a reliable status basis for downstream output.

[0052] Finally, according to the output rules defined in the BMC information, the system selects 1394 bus data that meets the conditions from data buffer 1 and sends it to the output buffer. The output buffer adopts a ping-pong operation mechanism, alternating between writing and reading to ensure the continuity and real-time performance of the data stream. When the main control board initiates a read request through the parallel bus, the output buffer can stably provide the processed acquisition data, achieving efficient and low-latency data return. The entire process automatically completes the entire chain of processing from receiving, filtering, buffering to output without relying on external intervention, meeting the requirements of high reliability and high timeliness acquisition of 1394 bus data in airborne environments.

Claims

1. An on-board 1394 acquisition card, characterized in that: The 1394 bus interface and the FPGA module are connected with a 1394 LLC, a 1394 PHY and a transformer in sequence from the FPGA module; the 1394 LLC is used to provide link layer control function between the FPGA module and the 1394 PHY, complete encapsulation and analysis of data frames, protocol conversion between transaction layer and link layer, and coordinate bus arbitration, asynchronous and isochronous data transmission; the 1394 PHY is used to realize signal transceiving function of the 1394 bus physical layer, convert digital logic signals from the 1394 LLC into differential analog signals conforming to IEEE 1394 standard for transmission, simultaneously receive differential analog signals on the bus and convert them into digital signals and transmit them back to the 1394 LLC; the transformer is used to provide AC coupling and electrical isolation between the 1394 PHY and the external 1394 bus.

2. The airborne 1394 acquisition card of claim 1, wherein: The FPGA module is also connected with an FPGA configuration circuit through an SPI bus; the FPGA configuration circuit is composed of a Nor Flash, when the 1394 acquisition card is powered on, FPGA configuration data is read from the Nor Flash and loaded into the FPGA module.

3. The airborne 1394 acquisition card of claim 1, wherein: The FPGA module receives 1394 bus data by a built-in 1394 receiving module; the 1394 receiving module is used to receive 1394 bus data from the 1394 bus interface, perform clock conversion and then cache; the 1394 receiving module is also used to divide filter conditions corresponding to 1394 bus data into preset shares, put 1394 bus data into a corresponding number of caches of preset shares for storage, so as to perform parallel execution when starting filtering; the 1394 receiving module is also used to add corresponding time stamps when putting 1394 bus data into caches for storage, reserve a preset number of data bits in front of a first cache space corresponding to the cache for time stamp information, then write data frame contents after the data bits, and then write the time stamp information.

4. The airborne 1394 acquisition card of claim 1, wherein: ​ 5. The airborne 1394 acquisition card of claim 4, wherein: The filtering of the 1394 bus data by the FPGA module is performed by a filtering module built in the FPGA module; the filtering module is configured to determine a filtering condition corresponding to the 1394 bus data, and determine whether there is a storage value according to information FIFO corresponding to each cache space in the 1394 receiving module, and then start a corresponding state machine, take values from the data FIFO of each cache space, take values from a preset filtering cache, and compare and filter the two values. The filtering condition determined by the filtering module includes a channel number, a message ID, and a preset number of filtering comparison data from the filtering cache.

6. The airborne 1394 acquisition card of claim 5, wherein: The pipeline cache of the 1394 bus data by the FPGA module is performed by a pipeline cache module built in the FPGA module; the pipeline cache module is configured to put the filtered 1394 bus data into a RAM cache space according to an input signal of the filtering module; the pipeline cache module is also configured to extract and lock the pipeline number to be stored when the data frame content is obtained, and store the channel number, timestamp and data frame content of the latched 1394 bus data into the RAM cache space, and then extract the corresponding value of the 1394 bus data according to the BMC information from the main control board card, and store it into the corresponding position of the data cache 0 of the data cache module in the FPGA module.

7. The airborne 1394 acquisition card of claim 6, wherein: The data cache of the 1394 bus data by the FPGA module is performed by the data cache module built in the FPGA module; the data cache module is configured to extract the pipeline number corresponding to the storage of the 1394 bus data from the pipeline cache module, extract the initial cache position of the BMC information according to the pipeline number, thereby obtaining the BMC information, and then extract the 1394 bus data stored in the corresponding position of the data cache 0 according to the BMC information, refresh the 1394 bus data in the data cache 0 to the data cache 1 built in itself through a preset period signal, and update the corresponding state information.

8. The airborne 1394 acquisition card of claim 7, wherein: The output control of the 1394 bus data by the FPGA module is performed by an output control module built in the FPGA module; the output control module is configured to extract the corresponding 1394 bus data from the data cache 1 of the data cache module according to the condition in the BMC information, and output it to the output cache module of the FPGA module.

9. The airborne 1394 acquisition card of claim 8, wherein: The output cache of the 1394 bus data by the FPGA module is performed by the output cache module built in the FPGA module; the output cache module is configured to read the 1394 bus data transmitted by the output control module, and output it to the main control board card through the parallel bus interface; the output cache module has an output cache area with a preset depth, which is used to cache the 1394 bus data transmitted by the output control module, and adopts a ping-pong operation mode for data reading; the control state machine of the output cache module uses a write signal as a state jump indication signal, and a read signal is operated in another state, so as to read out the 1394 bus data in the output cache area.

10. A method for collecting 1394 bus data of an airborne 1394 capture card according to any one of claims 1 to 9, characterized in that, The method comprises the following steps: S1, receiving 1394 bus data from an on-board device, adding a corresponding timestamp after clock conversion, and caching in a first cache space; S2, according to the preset filtering condition, the value is taken from the first cache space and compared and filtered, and the filtered 1394 bus data is put into the RAM cache space, and the corresponding pipe number is determined; S3, according to the BMC information from the main control board, the corresponding value of the 1394 bus data is extracted and stored in the corresponding position of the data cache 0; S4, through the preset periodic signal, the 1394 bus data in the data cache 0 is refreshed to the data cache 1, and the corresponding state information is updated; S5, the corresponding 1394 bus data is extracted from the data cache 1 and stored in the output cache area, and the ping-pong operation mode is used to send the collected and processed 1394 bus data to the main control board.

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