Computing circuit in memory

Abstract

The invention provides a circuit for computing in a memory. The in-memory computing circuit includes a plurality of latches and a plurality of NOR gates. Each latch has a word line, a bit line, a complementary bit line, a first output terminal and a second output terminal. The bit line is coupled to a local bit line of one of a plurality of memory strings in the memory array. The complementary bit line is coupled to a local complementary bit line of a memory string in the memory array. The memory string includes a plurality of storage units. Each storage unit is composed of a storage unit pair. The second output provides a weight signal sensed by the latch from the pair of memory cells. Each NOR gate is provided with a first input end, a second input end and an output end. The first input is coupled to the second output of the latch. The second input end receives an input signal from the outside. The output end outputs the product of the weight signal and the input signal.

Description

Technical Field

[0001] This invention relates to an in-memory computing circuit. Background Technology

[0002] The development of AI has been booming recently. AI-related computations require considerable resources and energy. In order to accelerate AI-related computations, computing in memory (CIM) technology, which performs calculations directly within memory instead of reading data from memory and then performing calculations by circuits such as the arithmetic logic unit (ALU), has also attracted attention.

[0003] However, there is still room for improvement in in-memory computing using 3D flash memory. Therefore, how to further improve the computing speed and reduce energy consumption of in-memory computing using 3D flash memory is a key issue. Summary of the Invention

[0004] Based on the above description, according to an embodiment of the present invention, an in-memory computing circuit is provided. The in-memory computing circuit includes a plurality of latches and a plurality of NOR gates. Each of the plurality of latches has a word line, a bit line, a complementary bit line, a first output, and a second output. The bit line of each of the plurality of latches is coupled to a local bit line of a corresponding memory string in a plurality of memory strings in a memory array. The complementary bit line of each of the plurality of latches is coupled to a local complementary bit line of the corresponding memory string in the memory array. The corresponding memory string includes a plurality of memory cells. Each memory cell is composed of memory cell pairs. The second output provides a weight signal sensed by the latch from the memory cell pairs. Each of the plurality of NOR gates has a first input, a second input, and an output. The first input of each of the plurality of NOR gates is coupled to the second output of the corresponding latch among the plurality of latches. The second input of each of the plurality of NOR gates receives an input signal from an external source. The output of each of the plurality of NOR gates outputs the product of the weight signal and the input signal.

[0005] According to another embodiment of the present invention, an in-memory computing circuit is provided. The in-memory computing circuit includes a latch and a first logic circuit. The latch has word lines, bit lines, complementary bit lines, a first output, and a second output. The first logic circuit has a first input, a second input, and an output, wherein the output is coupled to the word lines of the latch, the first input receives a control signal, and the second input is coupled to a power supply voltage of the latch. The complementary bit lines of the latch are coupled to a reference voltage. During operation of the latch, the power supply voltage rises from a low level to a high level.

[0006] According to another embodiment of the present invention, an in-memory computing circuit is provided. The in-memory computing circuit includes a plurality of latches, a plurality of first logic circuits, and a plurality of second logic circuits. Each of the plurality of latches has a word line, a bit line, a complementary bit line, a first output, and a second output. The bit line of each of the plurality of latches is coupled to a local bit line of a corresponding memory string in a plurality of memory strings in a memory array. The corresponding memory string includes a plurality of memory cells. Each of the plurality of memory cells is composed of a single memory cell. The second output of each of the plurality of latches provides a weighted signal sensed by the latch from the memory cell. The complementary bit line of each of the plurality of latches is coupled to a reference voltage. Each of the plurality of first logic circuits has a first input, a second input, and an output. The output of each of the plurality of first logic circuits is coupled to the word line of a corresponding latch in the plurality of latches. The first input of each of the plurality of first logic circuits receives a control signal. The second input of each of the plurality of first logic circuits is coupled to the power supply voltage of the corresponding latch in the plurality of latches. Each of the plurality of second logic circuits has a first input terminal, a second input terminal, and an output terminal. The first input terminal of each of the plurality of second logic circuits is coupled to the second output terminal of a corresponding latch in the plurality of latches. The second input terminal of each of the plurality of second logic circuits receives an input signal from an external source. The output terminal of each of the plurality of second logic circuits outputs the product of the weighting signal and the input signal. Attached Figure Description

[0007] Figure 1 A schematic diagram illustrating the structure of a 3D AND-type NOR flash memory device according to an embodiment of the present invention is shown.

[0008] Figure 2 This is a schematic diagram of a computing circuit within a digital memory according to an embodiment of the present invention.

[0009] Figure 3 Draw Figure 1 An example of a latch is shown.

[0010] Figure 4 This is a method of waking up the latch according to an embodiment of the present invention.

[0011] Figure 5 This is an in-memory computation method according to an embodiment of the present invention.

[0012] Figure 6 yes Figure 1 A variation of the latch array.

[0013] Figure 7AThis is a schematic diagram of a simulation configuration according to an embodiment of the present invention. Figure 7B A waveform diagram illustrating the wake-up of the latch via the memory array is shown. Figure 7C This is a diagram illustrating the various bias voltages used in the above simulation.

[0014] Figure 8A The diagram illustrates the operation waveforms and simulation results of a latch wake-up device using power decoding according to an embodiment of the present invention. Figure 8B A waveform diagram illustrating the wake-up of the latch via the memory array is shown. Figure 8C This is a diagram illustrating the various bias voltages used in the above simulation.

[0015] Figures 9A to 9C The diagram illustrates the simulation results showing that the latch of the present invention can still operate normally even when there is a delay between the word line of the latch and the power supply voltage of the latch.

[0016] Figures 10A to 10C A simulation result diagram illustrating the energy consumption assessment of an embodiment of the present invention is shown.

[0017] Figures 11A to 11B This is a simulation result diagram illustrating various energy-saving methods of embodiments of the present invention.

[0018] Figure 12A and Figure 12B This is a schematic diagram of an integrated 3D memory device with in-memory computing function according to an embodiment of the present invention.

[0019] Figure 13 This is a schematic diagram of a computing circuit within a digital memory according to another embodiment of the present invention.

[0020] Figure 14 Draw Figure 13 The example of the logic circuit shown.

[0021] Figure 15 Draw Figure 13 The timing diagram of the power supply decoding operation of the logic circuit shown is shown.

[0022] Figure 16 This is a schematic diagram illustrating a variation of the latch according to another embodiment of the present invention.

[0023] Figure 17A and Figure 17B This is a 3D memory device illustrated according to other variations of embodiments of the present invention.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10: Stacked structure

[0026] 12, 14: Conductor pillars

[0027] 16: Isolation Structure

[0028] 18: Hollow Channel Column

[0029] 20: Gate layer

[0030] 100, 200: Computational circuitry within digital memory

[0031] 110, 210: Memory array

[0032] 110a, 110b, 210a: Stacked structure

[0033] 112: Storage unit pair

[0034] 112a: Low threshold voltage storage cell

[0035] 112b: High threshold voltage storage cell

[0036] 114, 214: Memory string

[0037] 120: Latch Array

[0038] 121, 222: Latch circuit

[0039] 121a, 221a, 321a: Latch

[0040] 121b, 221b, 321b: NOR gates

[0041] 122: NAND gate

[0042] 130: Adder Tree

[0043] 131: Adder

[0044] 212: Storage unit

[0045] 221c, 321c: Logic circuits

[0046] BL n BL n+1 Bit line

[0047] LBL n LBL n+1 LBL: Local Bit Line

[0048] , Complementary bit lines

[0049] , , Local complementary bit lines

[0050] SL nSL n+1 SL: Source line

[0051] LSL n LSL n+1 LSL: Local Source Line

[0052] , , Complementary source pole lines

[0053] , , Local complementary source-pole line

[0054] T1~T6, T22~T26: Transistors

[0055] WL1, WL2, WL (i) m WL (i) m+1 WL (i+1) m WL (i+1) m+1 Word lines of a memory array

[0056] L0_WL(0) ~LN_WL(N), WL: Word line of the latch

[0057] BL' n BL n+1 BL': Bit line of the latch

[0058] , Complementary bit lines of latches

[0059] OUT: Output signal

[0060] W_B: Weight signal

[0061] IN_B: Input signal

[0062] V REF Reference voltage

[0063] BLD, BLBD: Bit line driver for latch

[0064] BLT n BBLT n BLT n+1 BBLT n+1 Bit line selection transistor

[0065] BLT1, BLT2, BLT_A, BLT_B: Bit line select transistors

[0066] SLT: Source Line Select Transistor

[0067] Vdd: Power supply voltage of the latch

[0068] MEM: Block

[0069] BM: Bottom Metal Layer

[0070] TM1, TM2: Upper metal layer

[0071] PB: Page Buffer

[0072] SA: Sensing Amplifier

[0073] dCIM: Computational Circuits within Digital Memory

[0074] CTL: Control Signal

[0075] PWR, L0 PWR, L1 PWR, LN PWR: Power signals Detailed Implementation

[0076] Figure 1 A schematic diagram illustrating the structure of a 3D AND-type NOR flash memory device according to an embodiment of the present invention is shown. The 3D AND-type NOR flash memory device may include multiple... Figure 1 The stacked structure 10 is shown. This stacked structure 10 extends with multiple parallel gate layers 20, for example, in the vertical direction (Z direction). Each gate layer 20 and another adjacent gate layer 20 are separated and isolated by a dielectric material (not shown). It can be further coupled to a conductor layer as word lines (not shown).

[0077] The stacked structure 10 includes a hollow channel pillar 18 extending along the vertical direction Z. The outer surface of the hollow channel pillar is surrounded by a charge storage structure (not shown). The charge storage structure is located between the hollow channel pillar 18 and each parallel gate layer 20. The charge storage structure may include multiple layers, including a tunneling layer, a charge trapping layer, and a barrier layer. The tunneling layer may include silicon oxide or a silicon oxide / silicon nitride combination (e.g., oxide / nitride / oxide). The charge trapping layer may include silicon nitride, or other materials that can trap or store charge. The barrier layer may include silicon oxide, aluminum oxide, a high-k dielectric material, and / or a combination of these materials. Two conductive pillars 12, 14 extending along the vertical direction Z are formed within the hollow channel pillar 18, which can serve as the source and drain of the memory cell and are in contact with the hollow channel pillar 18. The two conductive pillars 12, 14 have an isolation structure 16 extending along the vertical direction Z, isolating the two conductive pillars 12, 14.

[0078] In at least one embodiment of the operating method, a voltage is applied to the conductor pillars (drain side) and (source side), since the conductor pillars (drain side) and (source side) are connected to the hollow channel pillar 18, electrons or charges can be transferred along the hollow channel pillar 18 and stored in a charge storage structure intersecting with a particular selected gate layer (word line) 20. Therefore, programming operations can be performed on a specific memory cell.

[0079] Figure 2 This is a schematic diagram of a computing circuit within a digital memory according to an embodiment of the present invention. Figure 2 As shown, the in-memory computing circuitry 100 includes a latch array 120 and multiple adder trees 130. In some cases, the memory device can also be part of the in-memory computing circuitry 100. Here, the memory device is, for example, composed of a memory array 110, which, as an example, is a 3D AND-type NOR flash memory array. Figure 2 Only the array portion consisting of memory cells is shown. The peripheral circuits of the other parts of the memory device, such as row decoders, column decoders, etc., are omitted here. Those skilled in the art can design other peripheral circuits according to the actual operation requirements of the memory device.

[0080] In this example, memory array 110 is a three-dimensional structure composed of multiple memory cells arranged together. Memory array 110, for example, includes multiple... Figure 1 The stacked structure 10 shown, Figure 2 The i-th stack structure 110a and the (i+1)-th stack structure 110b are shown as illustrative examples. Furthermore, each stack structure 110a and 110b contains multiple word lines (such as word lines WL). m WL m+1 (etc.). Furthermore, in each word line (such as WL) of each stacked structure 110a, 110b m+1 The ) contains multiple storage cell pairs 112 (e.g., 112a, 112b). Figure 2 Examples of the nth and (n+1)th memory cell pairs are given. Furthermore, each stack structure 110a, 110b may include multiple memory strings 114, each memory string 114 being formed by stacking multiple memory cell pairs 112. Each memory cell pair 112 (e.g., 112a, 112b) of a memory string 114 is coupled to the same word line (e.g., word line WL). (i) m+1 Here, each storage unit is treated as a storage unit for 112.

[0081] The (m+1)th word line WL of the i-th stacked structure 110a (i) m+1For example, memory cell pair 112 includes a low threshold voltage memory cell 112a and a high threshold voltage memory cell 112b. Both the low threshold voltage memory cell 112a and the high threshold voltage memory cell 112b are flash memory cells. The gates of both the low threshold voltage memory cell 112a and the high threshold voltage memory cell 112b are coupled to the word line WL. (i) m+1 The source of the low threshold voltage storage cell 112a is coupled to the local source line LSL. n The drain of the low threshold voltage storage cell 112a is coupled to the local bit line LBL. n Similarly, the source of the high threshold voltage storage cell 112b is coupled to the local complementary source line. The drain of the high threshold voltage storage cell 112b is coupled to the local complementary bit line. .

[0082] Each stacked structure comprises multiple memory cell pairs 112 stacked together. For example, the i-th stacked structure 110a includes multiple local source lines, multiple local bit lines, multiple local complementary source lines, and multiple local complementary bit lines, but... Figure 2 Only the local source line LSL is shown as an example. n LSL n+1 Local bit line LBL n LBL n+1 Local complementary source pole lines , Local complementary bit lines , Taking the nth memory cell pair of the i-th stack structure 110a as an example, the local source line LSL n Each local bit line LBL extends vertically and is connected to the first terminal (source / drain terminal) of each low threshold voltage memory cell 112a. n They extend vertically and are connected to the second terminal (source / drain terminal) of each low threshold voltage storage cell 112a.

[0083] Similarly, local complementary source lines Local complementary bit lines extend vertically and are connected to the first terminal (source / drain terminals) of each high threshold voltage memory cell 111b. They extend vertically and are connected to the second terminal (source / drain terminal) of each low threshold voltage storage cell 112a.

[0084] Similarly, taking the (n+1)th memory cell pair of the i-th stack structure 110a as an example, the local source line LSL n+1 Each local bit line LBL extends vertically and is connected to the first terminal (source / drain terminal) of each low threshold voltage memory cell 112a. n+1Each line extends vertically and connects to the second terminal (source / drain terminal) of each low threshold voltage memory cell 112a. Similarly, local complementary source lines... Local complementary bit lines extend vertically and are connected to the first terminal (source / drain terminals) of each high threshold voltage memory cell 112b. They extend vertically and are connected to the second terminal (source / drain terminal) of each low threshold voltage storage cell 112a.

[0085] Local source line LSL of each stack structure 110a, 110b n LSL n+1 Then they are further connected to the source line SL respectively. n SL n+1 Local bit line LBL n LBL n+1 Then they are further connected to the bit line BL respectively. n BL n+1 Local complementary source pole line , They are then further connected to complementary source lines. , Local complementary bit lines , Then they are further connected to complementary bit lines respectively. , .

[0086] This position line LBL n Local complementary bit lines They are also coupled to the bit line select transistor BLT. n BBLT n The local bit line LBL n+1 Local complementary bit lines They are also coupled to the bit line select transistor BLT. n+1 BBLT n+1 These bit lines select the BLT transistor. n BBLT n BLT n+1 BBLT n+1 You can choose which local bit line to be sensed.

[0087] like Figure 2 As shown, a latch array 120 is further provided for each stack structure. Figure 2 An example is shown: a latch array 120 used in a stacked structure 110a. For example... Figure 2In the example shown, latch array 120 is an array with N+1 word lines (i.e., L0_WL(0)~LN_WL(N)), each word line including (n+1) latches 121a. The number of these (n+1) latches 121a is substantially the same as the number of memory cell pairs 112 on each word line of memory array 110.

[0088] Figure 3 Draw Figure 2 An example of the latch circuit 121 shown. Figure 3 As shown, the latch circuit 121 includes a latch 121a and a NOR gate 121b. Here, as an example, the latch 121a is a circuit composed of six transistors T1 to T6, which is equivalent to an SRAM structure. Transistors T3 to T6 form two inverter circuits connected end-to-end. In this architecture, the latch 121a can have word lines WL (i.e., L0_WL(0) to LN_WL(N) mentioned above), bit lines BL', and complementary bit lines. By applying an appropriate voltage to the word line WL, the latch 121a can be selected, and data can be transmitted via the bit line BL' and the complementary bit line. To write to latch 121a.

[0089] In this example, the gates of transistors T1 and T2 (as through gates) are coupled together and serve as the word line WL of latch 121a. One end of transistor T1 is coupled to bit line BL', and the other end is coupled to one end (node ​​n0) of the inverter circuit formed by transistors T3 to T6. One end of transistor T2 is coupled to the complementary bit line. The other end is coupled to the other end of the inverter circuit described above (node ​​n1). In this example, node n0 is logic "1" and node n1 is logic "0". Furthermore, nodes n0 and n1 can serve as the first and second output terminals of latch 121a, respectively, while bit line BL' and complementary bit line... These can be considered as the first and second input terminals of latch 121a.

[0090] Specifically, transistors T1 to T6 have a control terminal, a first terminal, and a second terminal (two source and drain terminals). For example... Figure 3 The control terminal of transistor (first transistor) T1 is coupled to word line WL, the first terminal is coupled to bit line BL, and the second terminal is coupled to node (first node) n0. The control terminal of transistor (second transistor) T2 is coupled to word line WL, and the first terminal is coupled to complementary bit line. The control terminal of transistor T3 (the third transistor) is coupled to node n1, its first terminal is coupled to the power supply voltage PWR, and its second terminal is coupled to node n0. The control terminal of transistor T4 (the fourth transistor) is coupled to node n1, its first terminal is coupled to node n0, and its second terminal is coupled to ground. The control terminal of transistor T5 (the fifth transistor) is coupled to node n0, its first terminal is coupled to the power supply voltage PWR, and its second terminal is coupled to node n1. The control terminal of transistor T6 (the sixth transistor) is coupled to node n0, its first terminal is coupled to node n1, and its second terminal is coupled to ground. Transistors T3 and T5 are P-type transistors, such as PMOS transistors, while transistors T1, T2, T4, and T6 are N-type transistors, such as NMOS transistors.

[0091] In this example, one input of NOR gate 121b receives the weight signal W_B from node n1 (the second output), and the other input receives the external input IN_B. The output provides the output signal OUT. This output signal OUT is equivalent to the product of the input signal IN_B and the weight signal W_B. Furthermore, the truth table for each NOR gate 121b is shown in Table 1 below.

[0092] Table 1

[0093]

[0094] Back Figure 2 Taking the i-th stack structure 110a as an example, other stack structures have the same architecture. For the n-th pair of memory cells 112, the local bit line LBL of the memory array 110... n via bit line select transistor BLT n Bit lines BL' of each latch 121a coupled to word lines L0_WL(0) ~ LN_WL(N) of latch array 120 n Local complementary bit lines of memory array 110 BBLT via bit line selection transistor n The complementary bit lines of each latch 121a coupled to the word lines L0 WL(0) ~ LN WL(N) of the latch array 120 .

[0095] Similarly, for the (n+1)th pair of memory cells 112, the local bit line LBL of memory array 110 n+1 via bit line select transistor BLT n+1 Bit lines BL' of each latch 121a coupled to word lines L0_WL(0) ~ LN_WL(N) of latch array 120 n+1 Local complementary bit lines of memory array 110 BBLT via bit line selection transistor n+1 The complementary bit lines of each latch 121a coupled to the word lines L0_WL(0) ~ LN_WL(N) of the latch array 120 .

[0096] For the output of each latch 121a, it senses the weight value (i.e., weight signal W_B) stored in the memory cell 112 of the memory array 110 and provides it to the first input of the NOR gate 121b, while the second input of the NOR gate 121b receives the input signal IN_B from the outside. After performing a logical operation on the received weight signal W_B and the input signal IN_B, the NOR gate 121b performs a product operation on the weight signal W_B and the input signal IN_B, and then outputs the output signal OUT.

[0097] Furthermore, the number of adder trees 130 is the same as the number of latches 121a on each word line (e.g., L0_WL(0)) of latch array 120, which is the same as the number of memory cell pairs 112 on each word line of memory array 110. Each adder tree 130 includes multiple adders 131. In this example, the number of adders 131 is, for example, the number of word lines of latch array 120 minus 1. That is, if the number of word lines of latch array 120 is N+1, the number of adders 131 is N.

[0098] Each adder tree 130 receives the output signal OUT of the NOR gate 121b corresponding to each latch 121a in each row of the latch array 120, and performs an addition operation on the output signals OUT of each NOR gate 121b before outputting the sum. For example, the first adder 131 adds the output signals OUT of the first and second NOR gates 121b, and then the second adder 131 adds the sum of the first and second NOR gates 121b's output signals OUT to the output signal OUT of the third NOR gate 121b. In this way, all the output signals OUT of the NOR gates 121b are added together and a multiply-and-accumulate (MAC) output is performed.

[0099] Here, each NOR gate 121b in the latch array 120 performs a multiplication operation between the weight value and the input signal, while each adder tree adds the output signals of the corresponding NOR gate 121b, thereby performing in-memory calculations to obtain the MAC value.

[0100] In the digital memory computing circuit 100 of this embodiment, a pair of memory cells 112 is used to wake up latches 121 in the latch array 120. As described above, one side of the pair of memory cells 112 is a low threshold voltage memory cell 112a, and the other side is a high threshold voltage memory cell 112b. For example, when the low threshold voltage memory cell 112a is selected for sensing, its corresponding local bit line LBL... n The voltage level will be pulled high, and the complementary local bit line corresponding to the high threshold voltage storage cell 112b will be pulled high. The voltage level will remain low.

[0101] Therefore, according to an embodiment of the present invention, through the local bit line LBL n and local complementary bit lines The voltage difference between them can wake up latch 121 for sensing. That is, in the inverter circuit of latch 121a (such as...) Figure 3 A voltage difference exists between the two ends of n0 and n1, causing the state of latch 121a to change, thereby allowing the weight value stored in storage cell 112 to be quickly transmitted to latch 121.

[0102] Figure 4 This is a method for waking up the latches according to an embodiment of the present invention. Before computation in the digital memory, each latch 121 in the latch array 120 first senses each storage cell pair 112 in the memory array 110, and the sensed value is used as a weight signal (weight value) W_B. Figure 4 As shown, first, a word line is selected from the memory array 110, for example, word line WL is selected. (i) m+1 At that time, for the character line WL (i) m+1 A voltage (e.g., 6.8V) is applied to select a word line, while a voltage (e.g., 0V) is applied to deselect other word lines, making them unselected. Additionally, on the source line SL... n Complementary source pole lines Apply a voltage of 1V. Furthermore, in this WL... (i) m+1 Other memory cells on the time corresponding to 112 (such as the (n+1)th pair) on the source line SL n+1 Complementary source pole lines A voltage of 1V can also be applied.

[0103] At the same time, with the local bit line LBL n Local complementary bit lines Connected bit line select transistors (BLTs) n BBLT nAn appropriate voltage is also applied to the gate to turn it on, connecting it to the local bit line LBL. n+1 Local complementary bit lines Connected bit line select transistors (BLTs) n+1 BBLT n+1 The gate can also be turned on by applying an appropriate voltage. In addition, for example, word line L0_WL(0) can be selected for data transmission in latch array 120, while other word lines L0_WL(1) to L0_WL(N) are unselected.

[0104] At this time, under the bias state of the aforementioned memory cell 112, the low threshold voltage memory cell 112a will be turned on, and the high threshold voltage memory cell 112b will be turned off, thus forming a voltage drop from the source line SL. n via local source line LSL n Low threshold voltage storage cell 112a, local bit line LBL n With the selection transistor BLT n The current path is used to transfer the data stored in the low threshold voltage storage cell 112a to the latch 121. Furthermore, since the high threshold voltage storage cell 112b is not turned on, the local complementary bit line... The current in the path is relatively much smaller.

[0105] Thus, on the bit line BL' of the latch n and complementary bit lines There will be a voltage difference between them (or between nodes n0 and n1). This voltage difference will cause the latch 121 to switch states, thereby sensing the data stored in the low threshold voltage storage cell 112a, and this data will be directly transmitted to the NOR gate 121b.

[0106] The above operation can continue until all latches 121a in all latch arrays 120 have sensed data. Furthermore, for example, when selecting to sense data from latches 121a on word line L1_WL(1) of latch array 120, memory array 110 can select other word lines to sense different memory cell pairs 112. By selecting different word lines of memory array 110 and different combinations of word lines of latch array 120, different product operations of input signals and weight values ​​can be performed.

[0107] Figure 5 This is an in-memory computation method according to an embodiment of the present invention. After the memory array 110 wakes up the latch array 120, that is, after the latch array 120 reads the weight values ​​stored in the memory array 110 for the required memory cells, the bit line selection transistor (BLT) is activated. n BBLT n BLTn+1 BBLT n+1 An appropriate voltage is applied to the gate to turn off these bit line select transistors (BLTs). n BBLT n BLT n+1 BBLT n+1 At this point, the operation of the subsequent latch array 120 and adder tree 130 is independent of the memory array 110.

[0108] Furthermore, an unselected voltage is applied to each word line L0_WL(1) ~ LN_WL(N) in the latch array 120, making them all unselected. This initiates in-memory computation of the digital memory computation circuit 100. At this time, one input of the NOR gate 121b connected to each latch 121a in the latch array 120 receives the weight signal W_B, while the other input receives the input signal IN_B from the outside (i.e., input(0) ~ input(N)). Each NOR gate 121b can then quickly perform logical operations on the weight signal W_B and the input signal IN_B, resulting in an output signal OUT multiplied by the weight signal W_B and the input signal IN_B.

[0109] Subsequently, the output signals of the NOR gates 121b in the same row of the latch array 120 are further transmitted to the adder tree 130, where the adders 131 inside the tree perform addition operations on the output signals OUT of these NOR gates 121b to output the MAC value.

[0110] According to an embodiment of the present invention, the weight data stored in the memory array 110 can be reused for convolution operations simply by changing the MAC input (the input signal IN_B of the NOR gate 121b). Furthermore, according to an embodiment of the present invention, all circuits performing calculations within the digital memory (latch 121a, NOR gate 121b, and each adder 131 of the adder tree 130) are constructed using MOS transistors. This is because during calculations within the digital memory, the bit line selection transistor BLT in the memory array 110... n BBLT n Since all parameters are turned off, they are unrelated to memory array 110. Therefore, the performance of computation within the digital memory depends only on the layout, CMOS architecture, metal wiring, and adder tree architecture. Thus, once latch 121 senses the required weight values, multiplication and addition operations can be performed almost instantly, resulting in the output of the MAC value.

[0111] Figure 6 yes Figure 1This is a variation of the latch array. The aforementioned NOR gate 121b may operate at any time if the weight signal W_B changes. Therefore, if the memory array 110 wakes up each latch 121a of the latch array 120, each latch 121a may cause a level change in nodes n0 and n1 when sensing the data transmitted from the memory cell to 112 of the memory array 110.

[0112] Once the states of nodes n0 and n1 change, NOR gate 121b will be mistakenly activated and begin operating, thereby generating an output signal OUT. This output signal OUT will further cause each adder tree 130 to start operating. Therefore, it is preferable that each NOR gate 121b and each adder tree 130 should not operate when waking up each latch 121a of latch array 120, otherwise malfunctions will occur. Therefore, during the waking up of each latch 121a of latch array 120, it is necessary to fix the output of NOR gate 121b, thereby preventing abnormal operation of each adder tree 130 and reducing power consumption.

[0113] To achieve this goal, such as Figure 6 As shown, the embodiment of the present invention can further provide a NAND gate 122 to control the output of each NOR gate 121b. As an example, the NAND gate 122 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the update signal UPDATE, the second input terminal receives the global input signal GIN, and the output terminal outputs the local input signal. By sharing the input signal concept, during the wake-up of each latch 121a, if all the input signals IN_B of the NOR gate 121b are set to logic "1", then the output signal OUT of the NOR gate 121b will become logic "0". Thus, during the wake-up of each latch 121a, the output signal OUT of the NOR gate 121b can be prevented from changing, thereby preventing the adder tree 130 from operating accordingly.

[0114] In this situation, if no calculations are performed in the digital memory during the wake-up of each latch 121a, the update signal UPDATE of the input NAND gate 122 can be set to logic "0". Thus, regardless of the logic state of the global input signal GIN, the output of NAND gate 122 will output logic "1", causing the output signal OUT of NOR gate 121b to become logic "0". Table 2 below lists the truth table of NAND gate 122.

[0115] Table 2

[0116]

[0117] Next, the above will be explained. Figure 2The simulation results are used to demonstrate that the above architecture is feasible. Figure 7A This is a schematic diagram of a simulation configuration according to an embodiment of the present invention. Figure 7A Drawn Figure 2 The stacked structure 110a in the example uses two word lines WL1 and WL2. As described above, each memory cell pair 112 includes a low threshold voltage memory cell 112a and a high threshold voltage memory cell 112b. Furthermore, Figure 7A Only one example is shown with local bit line LBL and complementary local bit line. A latch 121a is coupled.

[0118] In addition, latch 121a also includes means for driving bit line BL' and complementary bit line respectively. Bit line drivers BLD and BLBD. In addition, memory array 110 also includes local source line LSL and complementary local source line. Source-line selected transistor (SLT) with coupling Figure 7A One on each side), through the source line selection transistor SLT, applied to the source line SL and the complementary source line. The voltage can be applied to the local source line LSL and complementary local source lines. Charge.

[0119] In this simulation, word line WL1 is selected, and word line WL2 is not selected. Therefore, a voltage of 7V is applied to word line WL1 to enable word line WL1, and a voltage of 0V is applied to word line WL2 (including other unselected word lines) to disable word line WL2.

[0120] Figure 7B A waveform diagram illustrating the wake-up of the latch via the memory array is shown. Figure 7C This illustrates the various bias diagrams used in the above simulation. The wake-up process can be broadly summarized into four phases: P1, P2, P3, and P4. (As follows...) Figures 7A to 7C As shown, during P1, bit line BL' and complementary bit line of latch 121a are driven by bit line drivers BLD and BLBD, respectively. And apply a voltage (e.g., 6V) to the word line (e.g., L0_WL(0)) of latch 121a to set the initial state of latch 121a.

[0121] Next, during P2, the local bit line LBL is selected via bit line selection transistor BLT1. (For example, applying a 6V voltage to the gate of BLT1, bit line BL, complementary bit line) Then apply a voltage of 0V, thereby setting the local bit line LBL and the local complementary bit line. The bias voltage is then applied. Subsequently, bit line select transistor BLT1 is turned off, enabling local bit line LBL and local complementary bit line... It becomes a floating state.

[0122] Next, during period P3, a voltage of 3.3V is applied to the gate of the source line selection transistor SLT to turn it on. As the voltage of the source line SL increases from 0V to 1V, the source voltage of the source line selection transistor SLT rises from 0V to 1V. Simultaneously, a voltage of 6V is applied to the gate of the bit line selection transistor BLT2 to turn it on. This forms a current path from the source line SL through the local source line LSL, the low threshold voltage memory cell 112a, the local bit line LBL, and the selection transistor BLT2. Furthermore, as previously stated... Figure 4 As described above, the high threshold voltage storage cell 112b is not turned on. Flow through the local complementary bit line The current in the path is much smaller than that flowing through the local bit line LBL. n The current in the path.

[0123] Subsequently, during P4, an appropriate voltage is applied to the word line L0_WL(0) of latch 121a to enable the word line L0_WL(0), thereby waking up latch 121a. Through this operation, the states of nodes n0 and n1 of latch 121a can be transitioned, and the data stored in memory cell pair 112 can be transferred to the latch, that is, the weight data stored in memory cell pair 112 is written to latch 121a.

[0124] In this simulation result, from Figure 7C As can be seen from the top and bottom diagrams, nodes n0 and n1 of latch 121a (see reference) Figure 3 The latch 121a has been successfully woken up and is operating normally, meaning it has correctly sensed data from memory cell 112. This indicates that the latch 121a has been successfully woken up and is operating normally. Figure 2 The computing circuitry 100 in the digital memory shown is a feasible architecture.

[0125] Figure 8A This is a schematic diagram of a simulation configuration according to an embodiment of the present invention. Figure 8A The illustrated circuit is basically the same as Figure 7A The differences are the same, except that some bias voltages used in practical simulations differ depending on the power supply decoding operation. Aside from these differences, the rest of the components can be found in the reference section. Figure 7AThe above description states that the power supply voltage PWR of latch 121a is continuously supplied (e.g., a 1V voltage is continuously applied). Therefore, each latch 121a already has stored data before the memory array 110 wakes it up. Thus, when writing data to latch 121a, there is a high possibility of signal conflict with existing data. Therefore, in this embodiment, power supply decoding is used to wake up the latches. That is, the power supply voltage PWR is not applied before the memory array 110 wakes up each latch 121a, i.e., each latch 121a is left in a floating state. The latches are then woken up by the local bit line LBL and the local complementary bit line of the memory array 110. and the bit line BL' and complementary bit line of latch 121a After the bias voltages of all latches are set, the power supply voltage PWR is applied to wake up each latch 121a.

[0126] also, Figure 8B This is a waveform diagram illustrating the wake-up of the latch via a memory array, according to another embodiment. Figure 8C This illustrates the various bias diagrams used in the above simulation. The wake-up process can be broadly summarized into four phases: P1, P2, P3, and P4. (As follows...) Figures 8A to 8C As shown, during P1, the bit line drivers BLD and BLBD are used to control the bit line BL' and complementary bit line of latch 121a, respectively. Precharge to 0V. Afterwards, bit line drivers BLD and BLDB are turned off, and bit line BL' and complementary bit line... It becomes floating. At this time, a voltage of 7V is applied to the gates of the bit line selection transistor BLT2 (both sides), turning it on. During this P1 period, the power supply voltage PWR remains in the floating state (approximately 0V).

[0127] Next, during P2, a voltage of 7V is applied to the gate of the source line selection transistor SLT to turn on the source line selection transistor SLT (both sides). As the voltage of the source line SL increases from 0V to 1V, the voltage at the source of the source line selection transistor SLT rises from 0V to 1V. Simultaneously, the bit line selection transistor BLT1 remains on. This forms a current path from the source line SL through the local source line LSL, the low threshold voltage storage cell 112a, the local bit line LBL, and the selection transistor BLT2. During P2, the power supply voltage PWR remains in a floating state (approximately 0V). Furthermore, during P2, a voltage (e.g., 1V) is applied to the word line L0_WL(0) of the latch 121a to select that word line L0_WL(0).

[0128] Subsequently, during P3, the bias voltage of the local bit line LBL has been set. At this time, the power supply voltage PWR (e.g., 1V) of latch 121a is applied to wake up latch 121a. Through this operation, the states of nodes n0 and n1 of latch 121a can be transitioned, and the data stored in memory cell pair 112 can be transferred to the latch, that is, the weight data stored in memory cell pair 112 is written to latch 121a.

[0129] Finally, during P4, the bit line BL' and complementary bit line of latch 121a are... Discharge is performed. Furthermore, the bit line selection transistor BLT2 remains off throughout the entire process.

[0130] In this simulation result, from Figure 8C As can be seen in the diagram below, nodes n0 and n1 of latch 121a (see reference) Figure 3 The latch 121a has been successfully woken up and is operating normally, meaning it has correctly sensed the data from memory cell 112. This indicates that... Figure 2 The digital memory computing circuit 100 shown is capable of power decoding operation using the power supply voltage PWR.

[0131] Figures 9A to 9C The diagram illustrates the simulation results showing that the latch of the present invention can still operate normally even when there is a delay between the word line of the latch and the power supply voltage of the latch. Figures 9A to 9C The word lines of latch 121a were verified (e.g.) Figure 2 The waveforms of several delay times between word line L0_WL(0) and the latch power supply voltage PWR are used to change the setting level of the local bit line LBL bias voltage using these delay times, such as 20ns, 10ns, and 5ns. For example, when the delay times between word line L0_WL(0) and the latch power supply voltage PWR are 20ns, 10ns, and 5ns, the setting levels of the local bit line LBL bias voltage are 0.43V, 0.25V, and 0.14V, respectively. Figures 9A to 9C It can be seen that even with a bias voltage of only 0.14V on the local bit line LBL, the operation of waking up each latch 121a can still work correctly.

[0132] Figures 10A to 10C A simulation result diagram illustrating the energy consumption assessment of an embodiment of the present invention is shown. Also refer to... Figure 2 As described above, when the latch 121a is woken up by the memory array 110, the source line SL of the memory array 110... n and complementary source pole lines A bias voltage of 1V is applied, while the power supply voltage PWR of latch 121a is approximately 1V. This allows latch 121a to be woken up and the weighted data stored in memory cells 112 of memory array 110 to be transferred to latch 121a.

[0133] Therefore, when evaluating the energy consumption of the wake-up latch 121a, the source line SL can be considered. n and complementary source pole lines Apply a voltage of 1V and the power supply voltage PWR. Here, Figure 10A The voltage VSL=1V applied to the source line SL and its current are shown. Figure 10B This shows the complementary source pole line The applied voltage =1V and its current; Figure 10C The display shows the current at a power supply voltage PWR=1V.

[0134] Accordingly, the total energy consumption in one operating cycle (I×V×t, i.e., current×voltage×time) is approximately 0.26pJ + 0.19pJ = 0.45pJ, while the energy consumption of the power supply voltage PWR (0.5aJ) is very small and can be almost ignored. Furthermore, the energy consumption of in-memory computation (using a NOR memory array and a sense amplifier to sense data from the array) is approximately 21pJ. Therefore, the energy consumption of in-memory computation in this invention is low.

[0135] Figures 11A to 11B These are simulation results illustrating various energy-saving methods according to embodiments of the present invention. Figure 11A In the simulation results, the power supply voltage PWR of latch 121a was reduced to 0.8V, but the bit line capacitance and source line capacitance were set to the same level as... Figure 10A , 10B Same, such as 200fF). At this time Figure 11A The above shows that the source line SL can charge the local bit line LBL with only about 0.8V, and its energy consumption is 0.17pJ. Figure 11A The complementary source line is also shown below. The applied voltage is approximately 0.8V, and its energy consumption is 0.12pJ. Since the energy consumption of the power supply voltage PWR of latch 121a is still negligible, the total energy consumption is approximately 0.29pJ.

[0136] In addition, Figure 11B In the simulation results, the power supply voltage Vdd of latch 121a was reduced to 0.8V, but the bit line capacitance and source line capacitance were set to the same level as... Figure 10A , 10B Half of that, such as 100fF. At this time... Figure 11BThe above shows that the source line SL can charge the local bit line LBL with only about 0.8V, and its energy consumption is 0.1pJ. Figure 11A The complementary source line is also shown below. The applied voltage is approximately 0.8V, and its energy consumption is 0.06pJ. Since the energy consumption of the power supply voltage PWR of latch 121a is still negligible, the total energy consumption is approximately 0.16pJ.

[0137] Therefore, the simulation results above show that the power consumption per bit can be effectively reduced by appropriately lowering the power supply voltage PWR of latch 121a. Furthermore, by designing to reduce the bit line capacitance and source line capacitance of memory array 110, the power consumption per bit can be reduced even more effectively.

[0138] Figure 12A and Figure 12B This is a schematic diagram of an integrated 3D memory device with in-memory computing function according to at least one embodiment of the present invention, wherein... Figure 12B yes Figure 12A A partially enlarged view. Figure 2 The description primarily focuses on the architecture of the computing circuitry within the digital memory, but it does not present the components required for general operations such as programming, erasing, and reading of the memory array 110, such as sensing amplifiers. Figure 12A The diagram illustrates a general architectural concept for a 3D memory. A 3D memory device comprises multiple tile-like MEMs, which are constructed as follows: Figure 2 This 3D memory device is composed of memory arrays, etc. For ease of explanation, only the local bit line LBL (such as the upper metal layer TM1) is shown here. This 3D memory device is provided with two sets of bit line selection transistors BLT_A and BLT_B, etc., where bit line selection transistor BLT_A is equivalent to the aforementioned Figure 2 The bit line selection transistors shown are BLT, BBLT, etc.

[0139] Furthermore, the bit line selection transistor BLT_A can be connected to the in-memory computing circuit dCIM via the bottom metal layer BM, which includes the aforementioned... Figure 2 The circuit consisting of latch 121a, NOR gate 121b and adder tree 130 described herein.

[0140] In addition, another set of bit line select transistors, BLT_B, is used for general operations such as programming, erasing, and reading of the 3D memory device. For example, when operating the 3D memory device, the appropriate operating voltage can be applied to the local bit line LBL through the bit line select transistors BLT_B. Generally, the 3D memory device can share the page buffer PB and the sense amplifier SA. During a read operation, the sense amplifier S can sense the current when the memory cell is turned on to determine the data being read. For a general structure, the bit line select transistors BLT_B can be connected to the page buffer PB (e.g., through the upper metal layer TM2) via the upper metal layer TM2. Figure 12B (As shown).

[0141] By setting two independent sets of bit line selection transistors BLT_A and BLT_B, the 3D memory device can connect the local bit line to the in-memory computing circuit dCIM through the bit line selection transistor BLT_A, so as to transfer the data (weight data) stored in the 3D memory device to the in-memory computing circuit dCIM.

[0142] In addition, the bit line select transistor BLT_B enables the 3D memory device to perform general operations, such as writing weight values ​​to the 3D memory device, verifying the correctness of stored data, or erasing the data stored in the 3D memory device to rewrite the data.

[0143] The embodiments of the present invention do not particularly limit the specific structure of the 3D memory device, as long as it has two independent sets of bit line selection transistors BLT_A and BLT_B to facilitate digital memory calculations and general memory operations.

[0144] Figure 13 This is a schematic diagram of a computing circuit within a digital memory according to another embodiment of the present invention. In the above... Figure 2 In one embodiment, each latch 121a of the latch array 120 is woken up by a pair of memory cells 112 in the memory array 110. Figure 13 In one embodiment, each latch 221a of the latch array 220 transmits data by being woken up by only one storage unit 212.

[0145] like Figure 13 and Figure 2 As shown, the architecture of the computing circuit 200 in the digital memory of this embodiment is similar to... Figure 2 The architecture of the computing circuit 100 within the digital memory shown is basically similar, with differences only in the structure of the memory string 214, the latch, and its related control method. Furthermore, for ease of explanation, Figure 13 The circuit diagram shown represents only a portion of the computing circuitry 200 within the digital memory; the remaining parts can be referenced. Figure 2To construct the architecture. For example, memory array 210 may include multiple stacked structures 210a (such as... Figure 2 Stacked structures 110a, 110b, etc.), each stacked structure 210a may include multiple memory strings 214 (e.g., Figure 2 (Memory string 114). Furthermore... Figure 13 The latch array 220 illustrates only one latch 221a, but each latch 221a of the latch array 220 can also be configured to... Figure 2 It has the same architecture as the latch array 120.

[0146] In addition, Figure 2 Each latch 121a is awakened by a pair of memory cells 112 (i.e., a two-side bitline architecture), and Figure 16 The latch 221a is awakened by only one memory cell 212 (i.e., a one-side bitline architecture). In this example, the memory array 210 could also be a 3D NOR flash memory array. In each memory string 214 of each stack structure 210, one memory cell 212 is used as the storage unit. Conversely, in Figure 2 In each memory string 114 of each stack structure 110a, 110b, etc., a storage cell pair 112 (i.e., containing two storage cells 112a, 112b) is used as a storage cell. In addition, the storage cell 212 can be programmed to a low threshold voltage state or a high threshold voltage state.

[0147] Figure 13 The latch 221a shown is essentially the same as Figure 3 The latch 121a shown has the same architecture, also constructed using six transistors (MOS) T1~T6, which is equivalent to an SRAM. Therefore, the transistor connection structure of latch 221a is omitted here, and only the differences are explained. It will be used together in the description. Figure 3 The labels are used to explain.

[0148] like Figure 13 As shown, because this embodiment uses a single memory cell 212 to wake up the latch 221a, only the bit line BL' of the latch 221a is coupled to the local bit line LBL of the memory array 210 via the select transistor BLT_A. The complementary bit line of the latch 221a... Then coupled to the reference voltage V REF Furthermore, this reference voltage V REF It can be adjusted.

[0149] In this case, if the reference voltage V REFIf the voltage is 0.15V, then as long as the voltage of bit line BL' of latch 221a reaches 0.3V, latch 221a can operate normally in transition mode.

[0150] In addition, latch circuit 221 also includes logic circuit 221c. Logic circuit 221c has a first input, a second input, and an output, wherein the output is coupled to the word line of latch 221a, the first input receives the control signal CTL, and the second input is coupled to the power supply voltage PWR of latch 221a. Logic circuit 221c can be a NOR gate, a NAND gate, an inverter, or other logic gate. This circuit ensures that word line L0_WL(0) and power supply decoding (using power supply voltage PWR) can be switched on and off. That is, logic circuit 221c is designed such that when word line L0_WL(0) is on, power supply decoding (Vdd) is off, or when word line L0_WL(0) is off, power supply decoding (using power supply voltage PWR) is on. Table 3 below shows the truth table for logic circuit 221c using NOR gates.

[0151] Table 3

[0152]

[0153] Figure 14 This is an example of a logic circuit 221c illustrated according to an embodiment of the present invention. In this example, the logic circuit 221c can be implemented using NOR gates. Figure 14 As shown, logic circuit 221c further includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The first PMOS transistor P1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first PMOS transistor P1 is coupled to the power supply voltage PWR of latch 221a, and the first terminal of the first PMOS transistor P1 is coupled to the power supply Vdd of logic circuit 221c. The second PMOS transistor P2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second PMOS transistor P2 is coupled to the control signal CTL, the first terminal of the second PMOS transistor P2 is coupled to the second terminal of the first PMOS transistor P1, and the second terminal of the second PMOS transistor P2 is coupled to the output terminal of logic circuit 221c.

[0154] Furthermore, the first NMOS transistor N1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first NMOS transistor N1 is coupled to the power supply voltage PWR of the latch 221a, the first terminal of the first NMOS transistor N1 is coupled to the output terminal of the logic circuit 221c, and the second terminal of the first NMOS transistor N1 is coupled to ground. Also, the second NMOS transistor N2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second NMOS transistor N2 is coupled to the control signal CTRL, the second terminal of the second NMOS transistor N1 is coupled to the output terminal of the logic circuit 221c, and the second terminal of the second NMOS transistor N1 is coupled to ground.

[0155] Furthermore, if logic circuit 221c is not implemented using the aforementioned NOR gate, then logic circuit 221c can be designed using other circuit configurations. For example... Figure 13 and Figure 14 As shown, the output of logic circuit 221c provides an output voltage Vg to the word line L0_WL(0) of latch 221a. In this architecture, logic circuit 221c uses the analog power supply voltage PWR of latch 221a as an input signal, instead of a digital input. The transition state of the output voltage Vg (i.e., the voltage of word line L0_WL(0)) can be adjusted by the power supply voltage PWR, i.e., power supply decoding.

[0156] Figure 15 Draw a timing diagram illustrating the power supply decoding operation of logic circuit 221c. (Reference) Figure 14 and Figure 15 During sensing operation, the control signal remains at a low level (e.g., 0V). When sensing memory cell 210a (refer to...) Figure 13 The bit line voltage of bit line BL' and the reference voltage V of latch 221a. REF It will be charged. Furthermore, the supply voltage PWR of latch 221a is provided to the second input of the NOR gate. The supply voltage PWR will rise from a low level (e.g., 0V) to a high level (e.g., 1V). Initially, the output voltage Vg is at a high level, and transistors T1 and T2 are turned on. Therefore, during the rise of the supply voltage PWR, the currents I0 and I1 flowing through transistors T3 and T5, respectively, will affect the bit line voltage VBL and the reference voltage V. REF Charging. In this situation, the power supply voltage PWR will lose power to the line voltage VBL and the reference voltage V. REF Furthermore, the load on the power supply voltage PWR increases during its ramp-up period. Therefore, the ramp-up rate decreases.

[0157] However, according to this embodiment, by coupling the power supply voltage PWR to the second input of the logic circuit 221c (e.g., a NOR gate), the trigger point of the NOR gate 221c can be adjusted to prevent the current I0 and current I1 from clashing with the bit line voltage VBL and the reference voltage V. REF Charging. According to this embodiment, as... Figure 15 As shown, when the supply voltage PWR increases to the output voltage V_trigger, the output voltage Vg of the NOR gate 221c will change state, such as from a high level (e.g., 1V) to a low level (e.g., 0V). Afterwards, transistors T1 and T2 will be turned off. Therefore, currents I0 and I1 will no longer flow through transistors T1 and T2, thus affecting the bit line voltage VBL and the reference voltage V. REF Charge it.

[0158] Therefore, according to this embodiment, the transition time of the output voltage Vg of the logic circuit 221c can be adjusted by the trigger voltage V_trigger during the rise of the power supply voltage PWR. Furthermore, the trigger voltage V_trigger can be further adjusted by modifying the dimensions of the PMOS and NMOS transistors constituting the logic circuit 221c. Figure 15 In the embodiment shown, the trigger voltage V_triggerthe can be adjusted by modifying the dimensions of the first PMOS transistor P1, the second PMOS transistor P2, and the first (or second) NMOS transistor N1 (or N2).

[0159] Generally, the trigger voltage V_trigger can be considered as a voltage divider of the power supply voltage PWR. Furthermore, the trigger voltage V_trigger can be determined by the internal resistances of the first PMOS transistor P1, the second PMOS transistor P2, and the first NMOS transistor N1. If the internal resistances of the first PMOS transistor P1, the second PMOS transistor P2, and the first NMOS transistor N1 are r1, r2, and r3 respectively, then the trigger voltage V_trigger can be determined by the following formula.

[0160] V_trigger = r3 / (r1 + r2 + r3)

[0161] Furthermore, the internal resistance of a MOS transistor can be determined by the width of the MOS transistor. From this perspective, if the widths of the first PMOS transistor P1, the second PMOS transistor P2, and the first NMOS transistor N1 are w1, w2, and w3 respectively, then the trigger voltage V_trigger can be determined by the following formula.

[0162] V_trigger = w3 / (w1 + w2 + w3)

[0163] also, Figure 13 The logic circuit 221c shown can be omitted, meaning that power supply decoding can be omitted to wake up the latch 221a. In other words, the power supply voltage PWR of the latch 221a is continuously supplied throughout the wake-up process. Furthermore, Figure 6 The circuit architecture shown with the fixed output of NOR gate 221b can also be applied to Figure 13 The latch 221a shown.

[0164] The above description refers to the method of waking up each latch 221a using a single memory cell. Then, the weight data stored in the memory array 210 is written to each latch 221a. Following this, calculations are performed within the digital memory. Figure 13 When performing in-memory computations using the same architecture, the main differences lie only in the memory array 210 and the complementary bit lines of the latch 221a. It is coupled to the reference voltage V REF In addition, the methods of computation within digital memory and Figure 5 The way they are drawn is the same.

[0165] That is, after the weight value (weight signal) is written to each latch 221a, all bit line select transistors (BLTs) in the memory array 210 are turned off, making the latch array 220 independent of the memory array 210. Furthermore, appropriate voltages are applied to all bit lines L0_WL(0) to LN_WL(N) of the latch array 220 to turn off (disable) all bit lines L0_WL(0) to LN_WL(N). Then, each NOR gate 221b performs a product calculation based on the received weight signal W_B and the externally input signal IN_B. Finally, the products are added via an adder tree to output the MAC value.

[0166] Figure 16 This is a schematic diagram illustrating a variation of the latch according to another embodiment of the present invention. Figure 16 The latch 321a shown is with Figure 13 The difference between latch 221a and latch 321a is that latch 321a is composed of five transistors T22~T26, i.e., the omitted transistor T1 in latch 221a. Latch 321a has word line L0_WL(0), bit line BL' and complementary bit line. .

[0167] like Figure 16As shown, transistors T22 to T26 each have a control terminal (gate), a first terminal (first source / drain), and a second terminal (second source / drain). The first terminal of transistor (first transistor) T22 is coupled to a reference voltage V. REF The second end is coupled to the second node n1, and the control end is coupled to the complementary bit line. Transistor T23 (second transistor) has its first terminal coupled to the power supply voltage PWR, its second terminal coupled to the first node n0 and further coupled to the bit line BL', and its control terminal coupled to the second node n1. Transistor T24 (third transistor) has its first terminal coupled to the first node n0, its second terminal grounded, and its control terminal coupled to the second node n1. Transistor T25 (fourth transistor) has its first terminal coupled to the power supply voltage PWR, its first terminal coupled to the second node n1, and its control terminal coupled to the first node n0. Transistor T26 (fifth transistor) has its first terminal coupled to the second node n1, its second terminal grounded, and its control terminal coupled to the first node n0. Similarly, the latch 321a formed by these five transistors T22~T26 is equivalent to SRAM.

[0168] Furthermore, one input of NOR gate 321b is coupled to node n1 to receive the weight signal W_B from the memory array, and similarly, the other input of NOR gate 321a receives the input signal IN_B from the outside. The weight signal W_B and the input signal IN_B are multiplied by NOR gate 321a.

[0169] In this architecture, the transistor T1 (through the gate) on the node n0 side is omitted, and node n0 is directly connected to the bit line BL'. Thus, the latch 321a consists of only 5 transistors, making the circuit simpler and better meeting the functional requirements of computing circuits within digital memory.

[0170] Furthermore, this latch 321a can be applied to Figure 13 The memory array 210 shown is designed to be activated by a single memory cell 212 to write weighted data to a latch 321a. Furthermore, regarding the latch array comprised of latches 321a, the configuration of each latch 321a can be found in [reference needed]. Figure 2 The description is as follows, and the configuration of each latch 321a with the memory array can be found in the following reference. Figure 13 Explanation.

[0171] In addition, with Figure 13 The description is the same. Figure 16 The logic circuit 321c shown can be omitted, meaning that power supply decoding can be omitted to wake up the latch 321a. In other words, the power supply voltage PWR of the latch 321a is continuously supplied throughout the wake-up process. Furthermore, Figure 6The circuit architecture shown with the fixed output of NOR gate 221b can also be applied to Figure 16 The latch 321a shown.

[0172] In addition, regarding wake-up Figure 16 The latch 321a's method of operation, and the method of calculating the weight value (weight signal) after writing it into the digital memory of the latch 321a, are similar to the previous methods. Figure 4 , Figure 5 The method is the same. Therefore, it can be used as a reference. Figure 4 , Figure 5 The explanation will be adjusted accordingly, and will not be elaborated further here.

[0173] Figure 17A and Figure 17B This is a 3D memory device illustrated according to another variation of the embodiments of the present invention. The 3D memory device of this variation uses... Figure 16 The latch 321a is shown. In Figure 17A The input of the weight signal W_B of each NOR gate 321b is coupled to the corresponding latch node n1 of each latch 321a. Figure 17B The input of the weight signal W_B of each NOR gate 321b is coupled to node n0 of the corresponding latch 321a. This allows for adjustment of the capacitive load.

[0174] In summary, the embodiments of the present invention utilize latch circuits, NOR gates, and adder trees to construct an in-memory computing circuit for digital computation. During the data sensing phase, the latch can read weight information from the memory array. After data sensing is complete, the in-memory computing circuit can perform MAC value calculation independently of the memory array using a local bit line selection transistor between the in-memory computing circuit and the memory array, employing a low-power MOS circuit. Therefore, the architecture of the embodiments of the present invention achieves fast in-memory computation while reducing the power consumption per bit.

Claims

1. An in-memory computing circuit, comprising: a plurality of latches, each of the plurality of latches having a word line, a bit line, a complementary bit line, a first output and a second output, wherein the bit line of each of the plurality of latches is coupled to a local bit line of a respective memory string of a plurality of memory strings in a memory array, the complementary bit line of each of the plurality of latches is coupled to a local complementary bit line of the respective memory string in the memory array, the respective memory string comprising a plurality of storage cells, each of the storage cells being a pair of storage cells, the second output providing a weight signal sensed by the latch from the pair of storage cells; and a plurality of NOR gates, each of the plurality of NOR gates having a first input, a second input and an output, wherein the first input of each of the plurality of NOR gates is coupled to the second output of a respective latch of the plurality of latches, the second input of each of the plurality of NOR gates receives an input signal from outside, the output of each of the plurality of NOR gates outputs a product of the weight signal and the input signal.

2. The in-memory computing circuit of claim 1, wherein each of the plurality of latches further comprises: a first transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the bit line, and the second terminal is coupled to a first node as the first output; a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the complementary bit line, and the second terminal is coupled to a second node as the second output; a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to a power supply voltage of the latch, and the second terminal is coupled to the first node; a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to the first node, and the second terminal is coupled to ground; a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the power supply voltage, and the second terminal is coupled to the second node; and a sixth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the second node, and the second terminal is coupled to the ground, wherein the third and the fifth transistors are P-type transistors, and the first, the second, the fourth and the sixth transistors are N-type transistors.

3. The in-memory computing circuit of claim 1, further comprising: an adder tree receiving the products outputted by the output of each of the plurality of NOR gates and adding the products outputted by the plurality of NOR gates to output a multiply-and-accumulate (MAC) value, ​ wherein each of the plurality of latches is disabled after sensing each of the weight signals stored from the memory array.

4. The in-memory computing circuit of claim 1, wherein an output signal of the NOR gate is fixed by setting the second input of the NOR gate to logic 1 when writing data from the memory array to the latch.

5. The in-memory computing circuit of claim 1, wherein a power supply voltage for the latch is continuously supplied.

6. The in-memory computing circuit of claim 1, wherein a power supply voltage for the latch is supplied only when writing data from the memory array to the latch.

7. The in-memory computing circuit of claim 1, wherein the memory cell pair comprises a first memory cell and a second memory cell, each having a control terminal, a first terminal, and a second terminal, the control terminals of the first memory cell and the second memory cell being coupled to the same word line, the first terminal of the first memory cell being coupled to a local source line, the second terminal being coupled to the local bit line, and the first terminal of the second memory cell being coupled to a local complementary source line, the second terminal being coupled to the local complementary bit line.

8. The in-memory computing circuit of claim 1, wherein the first memory cell is a low threshold voltage memory cell, and the second memory cell is a high threshold voltage memory cell.

9. The in-memory computing circuit of claim 7, wherein the memory array is a 3D NOR type flash memory array.

10. An in-memory computing circuit, comprising a latch having a word line, a bit line, a complementary bit line, a first output terminal, and a second output terminal; a first logic circuit having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal is coupled to the word line of the latch, the first input terminal receives a control signal, and the second input terminal is coupled to a power supply voltage for the latch, wherein the complementary bit line of the latch is coupled to a reference voltage, during operation of the latch, the power supply voltage is ramped from a low level to a high level.

11. The in-memory computing circuit of claim 10, wherein a time point of a state transition of an output signal of the first logic circuit is determined by a trigger voltage, the trigger voltage being between the low level and the high level during the ramping of the power supply voltage.

12. The in-memory computing circuit of claim 11, wherein the output signal of the first logic circuit is transitioned in response to when a voltage value of the power supply voltage reaches the trigger voltage.

13. The in-memory computing circuit of claim 10, wherein the first logic circuit is a NOR gate.

14. The in-memory computing circuit of claim 13, wherein the first logic circuit further comprises: a first PMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first PMOS transistor is coupled to the power supply voltage, and the first terminal of the first PMOS transistor is coupled to a power supply of the first logic circuit; a second PMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second PMOS transistor is coupled to the control signal, the first terminal of the second PMOS transistor is coupled to the second terminal of the first PMOS transistor, and the second terminal of the second PMOS transistor is coupled to an output terminal of the first logic circuit; a first NMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first NMOS transistor is coupled to the power supply voltage of the latch, the first terminal of the first NMOS transistor is coupled to the output terminal of the first logic circuit, and the second terminal of the first NMOS transistor is coupled to ground; and a second NMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second NMOS transistor is coupled to the control signal, the second terminal of the second NMOS transistor is coupled to the output terminal of the first logic circuit, and the second terminal of the second NMOS transistor is coupled to the ground.

15. The in-memory computing circuit of claim 14, wherein the trigger voltage is determined based on a ratio of a width of the first NMOS transistor relative to a sum of widths of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor.

16. The in-memory computing circuit of claim 10, wherein each of the plurality of latches further comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the bit line, and the second terminal is coupled to a first node as the first output terminal; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the complementary bit line, and the second terminal is coupled to a second node as the second output terminal; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to a power supply voltage of the latch, and the second terminal is coupled to the first node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to the first node, and the second terminal is coupled to ground; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the power supply voltage, and the second terminal is coupled to the second node; and a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the second node, and the second terminal is coupled to the ground. ​ ​ ​ ​ ​ ​ ​ wherein the third and fifth transistors are P-type transistors, and the first, second, fourth and sixth transistors are N-type transistors.

17. The in-memory computing circuit of claim 10, wherein each of the plurality of latches further comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the reference voltage, the second terminal is coupled to a second node that is the second output terminal, and the control terminal is coupled to the complementary bit line; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to a first node that is the first output terminal and further coupled to the bit line, and the control terminal is coupled to the second node; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the first node, the second terminal is coupled to ground, and the control terminal is coupled to the second node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to the second node, and the control terminal is coupled to the first node; and a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the second node, the second terminal is coupled to ground, and the control terminal is coupled to the first node, wherein the second and fourth transistors are P-type transistors, and the first, third, and fifth transistors are N-type transistors.

18. The in-memory computing circuit of claim 10, wherein the first logic circuit is a NAND gate or an inverter.

19. An in-memory computing circuit, comprising: a plurality of latches, each of the plurality of latches having a word line, a bit line, a complementary bit line, a first output terminal, and a second output terminal, wherein the bit line of each of the plurality of latches is coupled to a local bit line of a respective memory string of a plurality of memory strings in a memory array, the respective memory string comprising a plurality of storage units, each of the plurality of storage units being a single storage unit, the second output terminal of each of the plurality of latches providing a sensed weight signal from the storage unit by the latch, and wherein the complementary bit line of each of the plurality of latches is coupled to a reference voltage; a plurality of first logic circuits, each of the plurality of first logic circuits having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of each of the plurality of first logic circuits is coupled to the word line of a respective latch of the plurality of latches, the first input terminal of each of the plurality of first logic circuits receiving a control signal, and the second input terminal of each of the plurality of first logic circuits being coupled to a power supply voltage of the respective latch of the plurality of latches; and ​ a plurality of second logic circuits each having a first input, a second input, and an output, wherein the first input of each of the plurality of second logic circuits is coupled to the second output of the corresponding latch of the plurality of latches, the second input of each of the plurality of second logic circuits receives an input signal from outside, and the output of each of the plurality of second logic circuits outputs a product of the weight signal and the input signal.

20. The in-memory computing circuit of claim 19, further comprising: a summer tree receiving the products outputted by the output of each of the plurality of second logic circuits and adding the plurality of products outputted by the plurality of second logic circuits to output a multiply-and-accumulate (MAC) value, wherein each of the plurality of latches is disabled after sensing the corresponding weight signal stored from the memory array.

21. The digital in-memory computing circuit of claim 19, wherein the bit line of each of the plurality of latches is coupled to the local bit line of the corresponding memory string via a bit line selection transistor.

22. The in-memory computing circuit of claim 19, wherein when writing data from the memory array to the plurality of latches, the output signal of the output of each of the plurality of second logic circuits is fixed by setting the second input of each of the plurality of second logic circuits to logic 1.

23. The in-memory computing circuit of claim 19, wherein each of the plurality of latches further comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the bit line, and the second terminal is coupled to a first node as the first output; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the word line, the first terminal is coupled to the complementary bit line, and the second terminal is coupled to a second node as the second output; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to a power supply voltage of the latch, and the second terminal is coupled to the first node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the second node, the first terminal is coupled to the first node, and the second terminal is coupled to ground; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the power supply voltage, and the second terminal is coupled to the second node; and a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first node, the first terminal is coupled to the second node, and the second terminal is coupled to the ground. ​ wherein the third and the fifth transistors are P-type transistors, and the first, the second, the fourth and the sixth transistors are N-type transistors.

24. The in-memory computing circuit of claim 19, wherein each of the plurality of latches further comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the reference voltage, the second terminal is coupled to a second node as the second output terminal, and the control terminal is coupled to the complementary bit line; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to a first node as the first output terminal and further coupled to the bit line, and the control terminal is coupled to the second node; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the first node, the second terminal is grounded, and the control terminal is coupled to the second node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to the second node, and the control terminal is coupled to the first node; and a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the second node, the second terminal is coupled to the ground, and the control terminal is coupled to the first node, wherein the second and the fourth transistors are P-type transistors, and the first, the third, and the fifth transistors are N-type transistors.

25. The in-memory computing circuit of claim 19, wherein the power supply voltage is ramped from a low level to a high level during operation of the latches.

26. The in-memory computing circuit of claim 19, wherein a time point of a transition of an output signal of each of the plurality of first logic circuits is determined by a trigger voltage, which is between the low level and the high level during the ramping of the power supply voltage.

27. The in-memory computing circuit of claim 26, wherein the output signal of the first logic circuit is transitioned in response to when a voltage value of the power supply voltage reaches the trigger voltage.

28. The in-memory computing circuit of claim 19, wherein each of the plurality of first logic circuits is a NOR gate.

29. The in-memory computing circuit of claim 28, wherein the NOR gate further comprises: a first PMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first PMOS transistor is coupled to the power supply voltage, and the first terminal of the first PMOS transistor is coupled to a power supply of the first logic circuit; a second PMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second PMOS transistor is coupled to the control signal, the first terminal of the second PMOS transistor is coupled to the second terminal of the first PMOS transistor, and the second terminal of the second PMOS transistor is coupled to an output terminal of the first logic circuit; and ​ a first NMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first NMOS transistor is coupled to the power supply voltage of the latch, the first terminal of the first NMOS transistor is coupled to the output terminal of the first logic circuit, and the second terminal of the first NMOS transistor is coupled to a ground; and a second NMOS transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second NMOS transistor is coupled to the control signal, the second terminal of the second NMOS transistor is coupled to the output terminal of the first logic circuit, and the second terminal of the second NMOS transistor is coupled to the ground.

30. The in-memory computing circuit of claim 29, wherein the trigger voltage is determined based on a ratio of a width of the first NMOS transistor relative to a sum of widths of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor.

31. The in-memory computing circuit of claim 19, wherein each of the plurality of first logic circuits is a NAND gate or an inverter.

32. The in-memory computing circuit of claim 19, wherein each of the plurality of second logic circuits is a NOR gate.

33. The in-memory computing circuit of claim 19, wherein the single memory cell of each of the plurality of memory cells has a control terminal, a first terminal, and a second terminal, the control terminal of the single memory cell is coupled to one of a plurality of word lines of the memory string, and the first terminal of the single memory cell is coupled to a local source line, and the second terminal of the single memory cell is coupled to a local bit line.

34. The in-memory computing circuit of claim 33, wherein the memory array is a 3D NOR flash memory array.

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