Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of suppressing cracking of an insulating substrate even when warpage of a product occurs after transfer molding. The semiconductor device includes: an insulating substrate having an insulating layer, a front surface pattern, and a back surface pattern; a semiconductor element mounted on the surface pattern; and a molding resin that seals the insulating substrate and the semiconductor element in a state in which a surface of the rear surface pattern on the opposite side from a surface facing the insulating layer is exposed. The rear surface pattern is bonded to the heat sink by solder, the surface of the rear surface pattern bonded to the heat sink and the surface of the molded resin facing the heat sink are at the same height position, and the front surface pattern is provided with first slits for dividing the front surface pattern into a plurality of regions. The back pattern is provided with a second slit for dividing the back pattern into a plurality of regions, and when viewed from the thickness direction of the insulating substrate, the first slit and the second slit do not overlap or only partially overlap.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] For example, Patent Document 1 discloses a semiconductor device comprising: a plurality of wiring layers (equivalent to surface patterns), an insulating substrate (equivalent to insulating layers) bonded to a first back surface of the plurality of wiring layers, a plurality of heat dissipation layers (equivalent to back surface patterns) with a second main surface bonded to the insulating substrate, semiconductor elements bonded to any one of the first main surfaces of the plurality of wiring layers, and a sealing resin covering the insulating substrate, the plurality of wiring layers, and the semiconductor elements. By configuring the plurality of wiring layers bonded to the surface of the insulating substrate and the plurality of heat dissipation layers bonded to the back surface of the insulating substrate to overlap when viewed from the thickness direction of the insulating substrate, the difference in the amount of expansion and contraction between the surface side and the back side of the insulating substrate due to temperature changes is reduced, thereby suppressing warping of the insulating substrate.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2020 / 149225 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] However, the technology described in Patent Document 1 does not take into account the warping of the product after transfer molding. In particular, since the slits dividing the insulating substrate into multiple wiring layers on the surface side and the slits dividing it into multiple heat dissipation layers on the back side are located at the same position when viewed from the thickness direction of the insulating substrate, there is a problem that the entire substrate containing multiple wiring layers and multiple heat dissipation layers is prone to bending and cracking.

[0008] Therefore, the purpose of this disclosure is to provide a technique for suppressing the cracking of the insulating substrate even when product warping occurs after transfer molding.

[0009] Technical means for solving technical problems

[0010] The semiconductor device disclosed herein includes: an insulating substrate having an insulating layer, a surface pattern formed on the surface of the insulating layer, and a back pattern formed on the back side of the insulating layer; a semiconductor element mounted on the surface pattern; and a sealing resin that seals the insulating substrate and the semiconductor element while exposing the side opposite to the side of the back pattern facing the insulating layer. The back pattern is bonded to a heat sink by solder. The side of the back pattern bonded to the heat sink is at the same height as the side of the sealing resin facing the heat sink. A first slit is provided on the surface pattern to divide the surface pattern into multiple regions, and a second slit is provided on the back pattern to divide the back pattern into multiple regions. When viewed from the thickness direction of the insulating substrate, the first slit and the second slit do not overlap or only partially overlap.

[0011] Invention Effects

[0012] According to this disclosure, when viewed from the thickness direction of the insulating substrate, the overlap between the first slit on the surface side and the second slit on the back side of the insulating substrate is reduced, thus suppressing the cracking of the insulating substrate even if the product warps after transfer molding.

[0013] The purpose, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view of the semiconductor device involved in the implementation.

[0015] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0016] Figure 3 This is a cross-sectional view illustrating the chip bonding process in the embodiment.

[0017] Figure 4 This is a cross-sectional view illustrating the wire bonding process in the embodiment.

[0018] Figure 5 This is a cross-sectional view illustrating the wire bonding process in the embodiment.

[0019] Figure 6 This is a cross-sectional view showing the molding process in the embodiment.

[0020] Figure 7 This is a cross-sectional view illustrating the solder mounting process in the embodiment.

[0021] Figure 8This is a cross-sectional view of a semiconductor device used to illustrate the generation of solder voids in the embodiments.

[0022] Figure 9 This is a bottom view illustrating an example of an insulating substrate included in a semiconductor device according to an embodiment.

[0023] Figure 10 This is a bottom view illustrating another example of an insulating substrate included in a semiconductor device according to an embodiment.

[0024] Figure 11 This is an enlarged cross-sectional view of the area around the second slit provided in the back pattern of the semiconductor device included in the embodiment.

[0025] Figure 12 This is an enlarged cross-sectional view of the semiconductor device included in a variation of the embodiment, around a second slit provided in a back pattern.

[0026] Figure 13 This is a cross-sectional view of a semiconductor device used to illustrate the generation of solder voids in related technologies. Detailed Implementation

[0027] <Implementation Method>

[0028] <Structure of Semiconductor Devices>

[0029] The embodiments are described below using the accompanying drawings. Figure 1 This is a cross-sectional view of the semiconductor device involved in the implementation.

[0030] like Figure 1 As shown, the semiconductor device includes an insulating substrate 1, a plurality of semiconductor elements 2, a plurality of lead frames 3, and a molding resin 5 as a sealing resin.

[0031] The insulating substrate 1 includes an insulating layer 1a, a surface pattern 1b, and a back pattern 1c. The insulating layer 1a is made of ceramic. The surface pattern 1b is made of a metal such as copper or aluminum and is formed on the surface of the insulating layer 1a. A first slit 6 is provided on the surface pattern 1b to divide the surface pattern 1b into multiple regions. The back pattern 1c is made of a metal such as copper or aluminum and is formed on the back side of the insulating layer 1a. A second slit 7 is provided on the back pattern 1c to divide the back pattern 1c into multiple regions. When viewed from the thickness direction of the insulating substrate 1, the second slit 7 is arranged in a grid pattern. Furthermore, when viewed from the thickness direction of the insulating substrate 1, the second slit 7 is arranged to surround the semiconductor element 2.

[0032] Multiple semiconductor elements 2 are mounted on surface pattern 1b via solder 4. These semiconductor elements 2 function as switching or rectifying elements. Examples of semiconductor elements include IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The rectifying element is a diode.

[0033] The material constituting the plurality of semiconductor elements 2 is, for example, silicon (Si). However, the material constituting the plurality of semiconductor elements 2 is not limited to silicon; for example, it can also be a wide-bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C). Wide-bandgap semiconductor materials are materials with a bandgap wider than that of Si. The plurality of semiconductor elements 2 made of wide-bandgap semiconductor materials can operate with high currents and in high-temperature environments. Therefore, the material constituting the plurality of semiconductor elements 2 is preferably a wide-bandgap semiconductor material.

[0034] The material of the multiple lead frames 3 is, for example, copper. The multiple lead frames 3 are bonded to the surface electrodes of the semiconductor element 2 by solder 4, or to the surface pattern 1b by solder 4, or connected to the wire pads of the semiconductor element 2 via aluminum wires 8.

[0035] The molding resin 5 is, for example, an epoxy-based thermosetting resin. The molding resin 5 seals the insulating substrate 1 and the semiconductor element 2 with the side opposite to the side opposite to the insulating layer 1a in the back pattern 1c exposed.

[0036] Here, the semiconductor device and heat sink 10 (see reference) Figure 7 Since the surface of the back pattern 1c that engages with the heat sink 10 and the surface of the molding resin 5 that is opposite to the heat sink 10 are at the same height, no step is created between the back pattern 1c and the molding resin 5.

[0037] <Methods for Manufacturing Semiconductor Devices>

[0038] Next, use Figures 2-7 The manufacturing method of semiconductor devices is explained. Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 3 This is a cross-sectional view illustrating the chip bonding process in the embodiment. Figure 4 This is a cross-sectional view illustrating the wire bonding process in the embodiment. Figure 5 This is a cross-sectional view illustrating the wire bonding process in the embodiment. Figure 6This is a cross-sectional view showing the molding process in the embodiment. Figure 7 This is a cross-sectional view illustrating the solder mounting process in the embodiment. Additionally, Figure 2 It is a diagram that extracts only the main processes from the manufacturing method of semiconductor devices and provides a simple description.

[0039] First, such as Figure 2 and Figure 3 As shown, in step S1, solder 4 is disposed on the surface pattern 1b of the insulating substrate 1, and a semiconductor element 2 is mounted thereon. The solder 4 is melted by reflow or the like, thereby bonding the semiconductor element 2 to the insulating substrate 1. In addition, in this embodiment, bonding by solder 4 is described as an example, but it is not limited to this, and sintering by silver or copper can also be performed.

[0040] Next, as Figure 2 and Figure 4 As shown, in step S2, solder 4 is disposed on the surface electrode and surface pattern 1b of semiconductor element 2, and lead frame 3 is disposed on it. Solder 4 is melted by reflow or the like, thereby bonding the surface electrode of semiconductor element 2 to lead frame 3, and simultaneously bonding the surface pattern 1b to lead frame 3.

[0041] Next, as Figure 2 and Figure 5 As shown, in step S3, aluminum wire 8 with a diameter of about 100 to 400 μm is used to connect the wire pads of the semiconductor element 2 to the signal terminals of the lead frame 3 by ultrasonic waves.

[0042] Next, as Figure 2 and Figure 6 As shown, in step S4, the wire-bonded finished product and sheet resin, which serves as the material for molding resin 5, are placed in the lower mold of a mold (not shown). The upper mold is closed, and the resin is gelled at a high temperature of approximately 180°C. Pressure is applied to force it through the runner and gate, and into the space (cavity) within the mold. The gelled resin is then re-cured at high temperature to form molding resin 5 with the same shape as the cavity. It is then removed from the mold.

[0043] Next, as Figure 2 and Figure 7 As shown, in step S5, solder 11 and a semiconductor device as a molded finished product are disposed on the heat sink 10, which is a heat dissipation component. The solder 11 is melted by reflow or the like, and the semiconductor device and the heat sink 10 are joined together.

[0044] In the above processes, the insulating substrate 1 is exposed to a high-temperature environment during the chip bonding process (step S1), the wire bonding process (step S2), the molding process (step S4), and the soldering and mounting process (step S5). Since the ceramic of the insulating layer 1a constituting the insulating substrate 1 is a brittle material, it has low resistance to bending, and it is important to avoid warping as much as possible in each process.

[0045] However, because the insulating substrate 1 requires both electrical conductivity and heat dissipation, a surface pattern 1b and a back pattern 1c are bonded and patterned on its surface and back side, respectively. Copper is generally used for both the surface pattern 1b and the back pattern 1c due to its superior performance. Copper is a relatively rigid material, and its coefficient of linear expansion differs from that of ceramics. Therefore, if the surface and back sides of the insulating layer 1a are not well balanced, warping will occur with temperature changes. Typically, for electrical conduction, the surface pattern 1b is divided into multiple regions by the first slit 6, resulting in lower rigidity than the undivided surface pattern 1b. To balance the reduced rigidity of the surface pattern 1b, a second slit 7 is provided on the back pattern 1c to further reduce its rigidity.

[0046] Furthermore, the back pattern 1c is a heat dissipation path for transferring heat generated from the semiconductor element 2 to the heat sink 10. Therefore, the second slit 7 is not located directly below the semiconductor element 2, but rather around the area directly below the semiconductor element 2. In other words, the second slit 7 is positioned to surround the area on the surface pattern 1b corresponding to the portion on which the semiconductor element 2 is mounted.

[0047] Next, the solder voids 12 generated in the solder 11 will be explained. Figure 13 This is a cross-sectional view of a semiconductor device used to illustrate the generation of solder voids 12 in related technologies. Figure 8 This is a cross-sectional view of a semiconductor device used to illustrate the generation of solder void 12 in the embodiment.

[0048] If air is entangled during soldering with the heat sink 10 and remains in the solder 11, it will cause problems like... Figure 13 As shown, solder voids 12 are formed, hindering heat dissipation. The smaller the area of ​​the bonding component that joins with the heat sink 10, the easier it is for the solder voids 12 to escape, but the solder voids 12 are difficult to escape from bonding components with a large area, such as the insulating substrate 1. However, in the large-area insulating substrate 1, the area directly below the semiconductor element 2 mainly contributes to heat dissipation. Therefore, as Figure 8As shown, if the solder voids 12 can be discharged into the second slit 7 provided on the back pattern 1c, the impact on heat dissipation will be reduced, and a semiconductor device with good heat dissipation can be achieved. Since the location of the solder voids 12 is uncertain, the effect of discharging the solder voids 12 from directly below the semiconductor element 2 can be further improved by creating a depressurized atmosphere or by oscillating it.

[0049] As described above, in order to drain the solder voids 12 into the second slit 7, it is necessary to prevent the second slit 7 from being filled with the molding resin 5. When the wire-bonded finished product is placed in the lower mold of the mold, it needs to be positioned by the lead frame 3. This is because, in order to prevent resin leakage when the upper and lower molds are closed and resin is injected into the cavity, the lead frame 3 and the mold are machined to be gap-free. However, due to slight offsets in the precision and clearance of the jigs used when bonding the lead frame 3 and the insulating substrate 1 with solder 4, although the insulating substrate 1 can only contact the surface of the lower mold, it is difficult to embed the back pattern 1c into the lower mold without gaps.

[0050] Therefore, by connecting only the outermost periphery without completely dividing the back pattern 1c as the surface pattern 1b, it is possible to suppress the flow of molding resin 5 into the second slit 7. Although the width of the outermost connected portion in the back pattern 1c depends on the pressure during resin injection and the flatness of the insulating substrate 1, it is preferably around 1 mm.

[0051] Figure 9 This is a bottom view showing an example of an insulating substrate 1 included in a semiconductor device according to an embodiment. Figure 10 This is a bottom view illustrating another example of the insulating substrate 1 included in the semiconductor device according to the embodiment. Figure 9 As shown, when the outermost periphery of the back pattern 1c is not connected, during transfer molding, resin flow from the outermost periphery of the back pattern 1c is suppressed by pressing a cushioning sheet or the like onto the back pattern 1c. However, the greater the thickness of the back pattern 1c, the more difficult this becomes. Figure 10 As shown, since the back pattern 1c is connected at the outermost periphery, there is no need for a cushioning sheet or the like, so the inflow of resin can be suppressed without being limited by the thickness of the back pattern 1c.

[0052] Regarding the suppression of warpage of the monomer of insulating substrate 1, as described above, it is also important to suppress the cracking of insulating substrate 1 in the event of warpage in the product after transfer molding. Warpage of the product after transfer molding is caused by differences in expansion and contraction between molding resin 5 and insulating substrate 1. Therefore, it is important to make the coefficients of linear expansion of molding resin 5 and insulating substrate 1 similar.

[0053] The main components that determine the mechanical properties of molding resin 5, such as the coefficient of linear expansion, are resin and filler. Increasing the proportion of filler can reduce the coefficient of linear expansion. However, if the proportion of filler is too high, the resin's flowability will deteriorate during transfer molding. Therefore, in practice, the proportion of filler is adjusted to keep the coefficient of linear expansion within the range of 10 ppm / ℃ to 20 ppm / ℃.

[0054] On the other hand, if the insulating substrate 1 is considered as a composite of ceramic (insulating layer 1a) and copper patterns on the surface and back (surface pattern 1b and back pattern 1c), the coefficient of linear expansion can be adjusted by changing its thickness. Ceramic, for example, often uses silicon nitride, with a coefficient of linear expansion of 3.5 ppm / ℃, while the copper patterns have a coefficient of linear expansion of 16.7 ppm / ℃. The coefficient of linear expansion of their composite is a value between these two, approaching one more than the other depending on their respective stiffness ratios. The stiffness ratio can be approximated by the ratio of the product of their respective volumes and elastic moduli.

[0055] The linear expansion coefficient of molding resin 5, 10 ppm / ℃, is between that of silicon nitride and copper, as long as their rigidity is the same. The elastic modulus of silicon nitride is 300 GPa, and that of copper is 117 GPa. Let the thickness of silicon nitride be t1, and the thickness of copper be t2. The area ratio of copper varies depending on the design specifications. If it is set to approximately 90%, then 300 × t1 × 1 = 117 × t2 × 0.9, and t2 = 300 / (117 × 0.9) × t1 ≈ 2.85 × t1.

[0056] In other words, if the combined thickness of the copper patterns on the surface and back is 2.8 times the thickness of the ceramic, and the copper patterns on the surface and back are of the same thickness (1.4 times the thickness of the ceramic), the coefficient of linear expansion is approximately 10 ppm / ℃. By further increasing the thickness of the copper patterns, the coefficient of linear expansion can be made greater than 10 ppm / ℃. Theoretically, by increasing the copper content, the coefficient of linear expansion can be made infinitely close to that of copper. However, considering the manufacturing limitations of the insulating substrate 1 and the size limitations of the semiconductor device, the upper limit of the thickness of the copper patterns on the surface and back can be considered to be approximately 3 to 3.5 times the thickness of the ceramic.

[0057] It is impossible to eliminate the warping of the insulating substrate 1 monomer and the warping of the product after transfer molding. Therefore, it is also important to make the insulating layer 1a, which is made of ceramic, a brittle material, less prone to cracking.

[0058] When no slits are provided on the surface pattern 1b and the back pattern 1c, the surface pattern 1b and the back pattern 1c can protect the insulating layer 1a and enhance its bending resistance. On the other hand, when slits are provided, due to the significant difference in rigidity between certain portions of the surface pattern 1b (or the back pattern 1c) and the portion of the first slit 6 (or the second slit 7), bending and cracking are more likely to occur in the portion of the first slit 6 (or the second slit 7). When viewed from the thickness direction of the insulating substrate 1, cracking is more likely to occur when the first slit 6 and the second slit 7 overlap.

[0059] To address this problem, in the embodiment, when viewed from the thickness direction of the insulating substrate 1, the first slit 6 and the second slit 7 do not overlap, or only partially overlap. Hereinafter, the case where the first slit 6 and the second slit 7 only partially overlap will be described. Both the first slit 6 and the second slit 7 have at least one straight portion. When viewed from the thickness direction of the insulating substrate 1, in the case where the first slit 6 and the second slit 7 partially overlap, the length of the overlap between the predetermined straight portion of the first slit 6 and the predetermined straight portion of the second slit 7 is less than 50% of the combined length of the predetermined straight portion of the first slit 6 and the predetermined straight portion of the second slit 7. Furthermore, in... Figure 9 and Figure 10 In the middle, the second slit 7 is formed in a lattice shape and has multiple straight sections.

[0060] In this way, by reducing the overlap between the first slit 6 and the second slit 7, a structure that makes the insulating substrate 1 less prone to breakage can be achieved even if product warping occurs after transfer molding.

[0061] <Effect>

[0062] As described above, the semiconductor device according to the embodiment includes: an insulating substrate 1 having an insulating layer 1a, a surface pattern 1b formed on the surface of the insulating layer 1a, and a back pattern 1c formed on the back side of the insulating layer 1a; a semiconductor element 2 mounted on the surface pattern 1b; and a molding resin 5 that seals the insulating substrate 1 and the semiconductor element 2 with the opposite side of the back pattern 1c to the side opposite to the insulating layer 1a exposed. The back pattern 1c is bonded to a heat sink 10 by solder 11, and the side of the back pattern 1c bonded to the heat sink 10 is located at the same height as the side of the molding resin 5 opposite to the heat sink 10. A first slit 6 is provided on the surface pattern 1b to divide the surface pattern 1b into multiple regions, and a second slit 7 is provided on the back pattern 1c to divide the back pattern 1c into multiple regions. When viewed from the thickness direction of the insulating substrate 1, the first slit 6 and the second slit 7 do not overlap, or only partially overlap.

[0063] Specifically, both the first slit 6 and the second slit 7 have at least one straight portion. When viewed from the thickness direction of the insulating substrate 1, the length of the overlap between the predetermined straight portion of at least one straight portion of the first slit 6 and the predetermined straight portion of at least one straight portion of the second slit 7 is less than 50% of the sum of the lengths of the predetermined straight portions of the first slit 6 and the second slit 7.

[0064] Therefore, when viewed from the thickness direction of the insulating substrate 1, the overlap between the first slit 6 on the surface side and the second slit 7 on the back side of the insulating substrate 1 is reduced, thus suppressing the cracking of the insulating substrate 1 even if product warping occurs after transfer molding. As a result, the semiconductor device can be used for a long time.

[0065] Furthermore, since the molding resin 5 is not filled in the second slit 7, solder voids 12 remaining in the solder 4 can be discharged into the second slit 7 during solder bonding. As a result, heat generated from the semiconductor element 2 can be effectively dissipated.

[0066] Furthermore, since the back pattern 1c is connected at the outermost periphery of the back pattern 1c, it is possible to suppress the flow of molding resin 5 into the second slit 7 during transfer molding.

[0067] Furthermore, because the second slit 7 surrounds the area on the surface pattern 1b corresponding to the portion on which the semiconductor element 2 is mounted, solder voids 12 are less likely to form directly below the semiconductor element 2. This improves the heat dissipation of the semiconductor device.

[0068] Furthermore, the thickness of both the surface pattern 1b and the back pattern 1c is more than 1.4 times the thickness of the insulating layer 1a. Therefore, the effect of suppressing the warping of the insulating substrate 1 is increased, and consequently, the effect of suppressing the warping of the product after transfer molding is also increased.

[0069] Furthermore, since semiconductor element 2 is a wide-bandgap semiconductor element, it may operate at higher temperatures compared to Si semiconductor elements. However, because the heat dissipation effect of the semiconductor device can be improved as described above, the temperature rise of semiconductor element 2 can be suppressed. As a result, the loss of semiconductor element 2 can be suppressed.

[0070] Furthermore, while SiC-based MOSFETs can operate at high temperatures, their losses deteriorate drastically at high temperatures, making it desirable to use them at the lowest possible temperature. Since the structure of the semiconductor device described in this embodiment can effectively transfer heat generated from the semiconductor element 2 to the heat sink 10 and suppress the temperature rise of the semiconductor element 2, it is particularly suitable for MOSFETs made of SiC.

[0071] <Modifications of the Implementation>

[0072] Next, variations of the implementation method will be described. Figure 11 This is an enlarged cross-sectional view of the area around the second slit 7 provided in the back pattern 1c of the semiconductor device included in the embodiment. Figure 12 This is an enlarged cross-sectional view of the semiconductor device included in the modified embodiment, around the second slit 7 provided in the back pattern 1c.

[0073] In semiconductor devices, high voltages are sometimes applied to the surface and back sides of the insulating substrate 1. For example, in electric vehicles, the voltage is approximately 400V to 1000V. Figure 11 As shown, when the second slit 7 penetrates the back pattern 1c and forms on the back side of the insulating layer 1a, if a solder void 12 exists in the second slit 7 (refer to...) Figure 8 If the solder void 12 comes into contact with the insulating layer 1a, a partial discharge 13 may occur from the insulating layer 1a.

[0074] To avoid this problem, such as Figure 12 As shown, in a modified embodiment, the second slit 7 does not penetrate the back pattern 1c and is not formed on the back side of the insulating layer 1a. That is, even in the area where the second slit 7 is provided, the back pattern 1c is in close contact with the back side of the insulating layer 1a.

[0075] Next, the manufacturing method of the insulating substrate 1 will be described. There are two methods. One method is to attach the back pattern 1c, which is formed by stamping or other means to form the second slit 7, to the insulating layer 1a. The other method is to first attach the back pattern 1c, which does not have the second slit 7, and then pattern it by etching to dissolve copper, thereby forming the second slit 7. Generally speaking, the latter manufacturing method is more commonly used.

[0076] In the back pattern 1c, the portion where the second slit 7 is not formed is masked, and only the portion where the second slit 7 is formed is sprayed with etching solution and dissolved to achieve patterning. Normally, the insulating layer 1a is exposed in the etched portion, but in a variation of the embodiment, the second slit 7 is formed by half-etching during the etching of the back pattern 1c by stopping the etching midway in the thickness direction of the insulating substrate 1. Therefore, the insulating layer 1a is not exposed in the etched portion. As a result, since the solder voids 12 do not contact the insulating layer 1a, the occurrence of partial discharge 13 can be suppressed.

[0077] While this disclosure has been described in detail, the foregoing description is exemplary in all respects and not restrictive. Examples are to be understood as numerous variations not shown can be contemplated.

[0078] Furthermore, it is possible to freely combine the various implementation methods, or appropriately modify or omit the various implementation methods.

[0079] Label Explanation

[0080] 1 Insulating substrate, 1a Insulating layer, 1b Surface pattern, 1c Back pattern, 2 Semiconductor element, 5 Molding resin, 6 First slit, 7 Second slit, 10 Heat sink, 11 Solder.

Claims

1. A semiconductor device, characterized by comprising: including: an insulating substrate having an insulating layer, a surface pattern formed on a surface of the insulating layer, and a back surface pattern formed on a back surface of the insulating layer; a semiconductor element mounted on the surface pattern; and a sealing resin sealing the insulating substrate and the semiconductor element in a state in which a surface opposite to the surface of the back surface pattern opposite to the insulating layer is exposed, the back surface pattern is joined to a heat sink with solder, a surface of the back surface pattern joined to the heat sink is at the same height position as a surface of the sealing resin opposite to the heat sink, a first slit for dividing the surface pattern into a plurality of regions is provided on the surface pattern, a second slit for dividing the back surface pattern into a plurality of regions is provided on the back surface pattern, the first slit and the second slit do not overlap or overlap only partially when viewed in a thickness direction of the insulating substrate.

2. The semiconductor device according to claim 1, wherein the second slit is not filled with the sealing resin.

3. The semiconductor device according to claim 1 or 2, wherein the back surface pattern is connected at an outermost periphery of the back surface pattern.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second slit surrounds a position on the surface pattern corresponding to a position at which the semiconductor element is mounted.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first slit and the second slit each have at least one straight portion, a length of an overlap portion of a predetermined straight portion of the at least one straight portion of the first slit and a predetermined straight portion of the at least one straight portion of the second slit is 50% or less of a total of a length of the predetermined straight portion of the first slit and a length of the predetermined straight portion of the second slit when viewed in the thickness direction of the insulating substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein a thickness of the surface pattern and a thickness of the back surface pattern are each 1.4 times or more of a thickness of the insulating layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second slit does not penetrate the back surface pattern and is not formed to the back surface of the insulating layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor element is a wide bandgap semiconductor element.

9. A method of manufacturing a semiconductor device according to claim 7, wherein the second slit is formed by half-etching in which etching is stopped halfway in the thickness direction of the insulating substrate when etching the back surface pattern. ​

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