A sonar system compensation circuit and method based on multi-channel switching

Abstract

The present application relates to a kind of sonar system compensation circuit and method based on multi-channel switching;Wherein the circuit uses cascade architecture, the core is to use domestic CBMG708 multiplexer to build at least one program-controlled gain stage, by the gain resistance of different resistance in series after each selection end is connected to operational amplifier, multiple signal channels with 6dB gradient basic gain are formed.Combined with FPGA+ARM dual-core control module, according to target action distance, corresponding channel is gated in real time, the fast and accurate gain compensation of sonar signal of different distances such as near, middle and far is realized.The method ensures that the output signal amplitude in the whole distance range is higher than the detection threshold, while having the advantages of small gain error, low power consumption and supply chain controllable, effectively solves the problem of insufficient flexibility and slow response of traditional single-channel compensation circuit.

Description

Technical Field

[0001] This invention relates to the field of sonar signal communication technology, and in particular to a sonar system compensation circuit and method based on multi-channel switching. Background Technology

[0002] In underwater target detection, the intensity of sonar echo signals attenuates exponentially with increasing range. If the receiving circuit uses a fixed gain, it will cause saturation distortion of near-range targets, while the signal of far-range targets will fall below the detection threshold and cannot be effectively identified. Therefore, it is necessary to design a gain compensation circuit that can dynamically adapt to different ranges.

[0003] In existing technologies, a single-channel programmable amplifier (PGA) is often used to achieve gain adjustment. For example, the amplification factor is changed by switching the feedback resistor network of the operational amplifier through a digital potentiometer or analog switch. However, this approach has inherent drawbacks: First, the single channel limits flexibility, making it difficult to achieve rapid multi-gradient gain matching across near, medium, and far distances in scenarios requiring rapid response to targets at different distances. Second, response speed is limited by the setup time of the PGA itself or the communication rate of the digital interface, making it difficult to achieve sub-microsecond-level rapid gain switching. Furthermore, many existing solutions rely on imported core chips (such as PGAs or analog switches from companies like ADI and TI), facing high supply chain risks, high costs, and poor compatibility with domestically developed sonar system platforms.

[0004] In recent years, domestic analog chip technology has made significant progress. For example, the CBMG708 8:1 multiplexer launched by Chipwise Microelectronics possesses excellent characteristics such as low on-resistance (typically 3Ω), fast switching speed (14ns), and wide power supply voltage (1.8V-5.5V). Although this chip is a multi-channel device, those skilled in the art usually regard it only as a simple signal routing switch, and its conventional application is concentrated in signal gating in data acquisition systems. In the specific technical field of sonar compensation circuits, existing technologies have not disclosed how to creatively combine the multi-channel characteristics of the CBMG708 with gain adjustment functions, nor have they revealed a technical solution for constructing a programmable gain stage with discrete, highly consistent gradient gain by pre-setting differentiated RC networks on each channel. Therefore, there is an urgent need for a new sonar compensation circuit structure that can fully utilize the advantages of such domestic multiplexers and solve the problems of insufficient flexibility and slow response of traditional single-channel PGAs. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a sonar system compensation circuit based on multi-channel switching, comprising: The signal input node (RCV_IN) is used to receive the raw electrical signals generated by the sonar transducer; A signal conditioning unit, connected to the signal input node, is used to perform preliminary amplification and noise filtering on the original electrical signal; At least one programmable gain stage, the core of which includes a multiplexer (U7, CBMG708) and an operational amplifier (U4, CBM8091). The multiplexer (U7) has a common terminal and multiple selection terminals. Each selection terminal is connected in series with a gain resistor (R25, R33, R42...) with different resistance values, and then they are all connected to the inverting input terminal of the operational amplifier (U4) to form multiple signal channels with different basic gains. The control module, electrically connected to the address selection ports (A0, A1, A2) of the multiplexer (U7), is configured to output a channel selection signal based on the target's effective distance to dynamically select the corresponding signal channel; A cascaded filtering unit, connected to the output of the programmable gain stage, is used to perform frequency band purification on the gain-compensated signal. By selecting channels with different gains, it achieves accurate compensation for sonar signals at different distances, ensuring that the output signal amplitude is higher than the detection threshold.

[0006] In one embodiment of the present invention, the base gain of the plurality of signal channels is preset in a 6dB gradient, covering a range from 0dB to 42dB.

[0007] In one embodiment of the present invention, the gain resistor is specifically configured as follows: The gain resistors for the channels used for near-field signal compensation are 1kΩ, 2kΩ, and 4.02kΩ, which correspond to 0dB, 6dB, and 12dB base gains, respectively. The gain resistors for the channels used for mid-range signal compensation are 8.06kΩ, 18kΩ, and 47kΩ, which correspond to 18dB, 24dB, and 30dB base gain, respectively. The gain resistors for the channels used for long-distance signal compensation are 64.9kΩ and 127kΩ, corresponding to a base gain of 36dB and 42dB, respectively.

[0008] In one embodiment of the invention, the system includes two programmable gain stages, and by combining and gating different signal channels in the two stages, an extended gain range from 0dB to 84dB is achieved.

[0009] In one embodiment of the present invention, the operational amplifier used in the signal conditioning unit and the cascaded filtering unit is a domestically produced CBM8091 chip.

[0010] In one embodiment of the present invention, the control module includes an FPGA and an ARM dual-core processor architecture; The ARM processor is used to query the pre-stored code value-distance adaptation table based on the target operating distance and generate the channel selection code value. The FPGA is used to receive the channel selection code value and generate corresponding timing control signals to drive the multiplexer (U7).

[0011] In one embodiment of the invention, the ARM processor and the FPGA simultaneously interact with each other via a shared block memory (BRAM).

[0012] In one embodiment of the present invention, the switching logic of the multiplexer (U7) is configured to suppress switching transient interference, and its channel switching delay time is ≤14ns.

[0013] In one embodiment of the present invention, the overall gain error of the circuit is controlled within 3%, which is determined by the accuracy of the gain resistor, the consistency of the multiplexer channel on-resistance, and the amplitude-frequency characteristics of the filter network.

[0014] The present invention also provides a sonar signal compensation method, comprising: Step S1: Receive the raw electrical signal from the sonar; Step S2: Perform preliminary amplification and first-stage filtering on the signal; Step S3: Based on the target operating distance, signal channels with different basic gains are preset by controlling the address gating of the multiplexer (U7); Step S4: Perform calculations and amplification on the signal of the selected channel; Step S5: Perform secondary and tertiary filtering on the amplified signal to output a sonar signal with clean frequency band and amplitude compensation.

[0015] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The sonar system compensation scheme of the present invention adopts a combination of a domestically produced CBMG708 multiplexer and a differentiated gain resistor network to construct a unique programmable gain stage, achieving a wide range of gain coverage from 0-84dB with a 6dB gradient, solving the problem that traditional single-channel circuits cannot dynamically adapt to signal attenuation at different distances. Its 14ns-level fast switching and "break-before-connect" logic ensure distortion-free compensation of the signal across the entire distance, with the overall gain error controlled within 3%. Combined with FPGA+ARM dual-core intelligent control, it achieves precise and rapid channel selection. The core chip of the solution is entirely domestically produced, which, while improving performance, also has advantages in high reliability and supply chain security, making it particularly suitable for portable sonar equipment and marine exploration fields with high requirements for independent control. Attached Figure Description

[0016] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0017] Figure 1 This is a schematic block diagram illustrating the principle and function of the sonar system compensation circuit based on multi-channel switching of the present invention; Figure 2 This is a schematic diagram of the operational amplifier described in this invention; Figure 3 This is a schematic diagram of the first-stage filter described in this invention; Figure 4 This is the schematic diagram of the first-stage programmable amplifier described in this invention; Figure 5 This is a schematic diagram of the two-stage filter described in this invention; Figure 6 This is the schematic diagram of the two-stage programmable amplifier described in this invention; Figure 7 This is a schematic diagram of the three-stage filter described in this invention; Figure 8 This is a flowchart of the software program control for the sonar signal compensation method in this invention; Figure 9 This is the full-link diagram of signal flow as described in this invention. Detailed Implementation Example

[0018] like Figure 1 As shown, this embodiment provides a sonar system compensation circuit based on multi-channel switching, which adopts a cascaded architecture. The signal flow follows the path of "operational amplifier (U3) → first-stage filter (composed of R30, C32, etc.) → first-stage programmable amplifier (U4, U7 and gain resistor network) → second-stage filter (composed of R32, C33, etc.) → second-stage programmable amplifier (structure same as the first stage) → third-stage filter (structure same as the second stage)"; and simultaneously combined with Figure 9 The signal flow is shown in the end-to-end diagram, ultimately reaching the back-end processing system. The core innovation of this architecture lies in the deep integration of the channel switching function of the multiplexer (CBMG708) and the amplification function of the operational amplifier (CBM8091) through a differentiated gain resistor network, forming a unique programmable gain stage.

[0019] Specifically, the signal is dynamically assigned different gains based on the target distance, and its flow can be precisely located as follows: RCV_IN → PRE_OP_OUT → RCV_1ST_OUT → RCV_2ST_OUT → RCV_3ST_OUT → RCV_4ST_OUT → RCV_OUT. This clear link ensures efficient and low-loss signal transmission between various functional modules.

[0020] Furthermore, such as Figure 2 The operational amplifier shown has its raw electrical signal output from the sonar transducer connected to the RCV_IN node on the PCB via a connector and sent to the non-inverting input (pin 3) of the first CBM8091 chip (U3). Its inverting input (pin 4) is connected to the output (pin 1) via a feedback network consisting of R40 = 3kΩ and C35 = 10pF, forming a non-inverting amplifier circuit. The gain is determined by R40 and the grounding resistor R45 = 1kΩ, with a theoretical value of A_V = 1 + 3kΩ / 1kΩ = 4 (12dB). The output signal is initially impedance matched by resistor R17 before being sent to the PRE_OP_OUT node.

[0021] Furthermore, such as Figure 3 The first-stage filter shown in the diagram transmits the signal from the PRE_OP_OUT node via resistor R30 = 1.3kΩ. R30 and capacitor C32 = 1nF form an RC low-pass filter network, with a cutoff frequency designed to attenuate high-frequency noise above 100kHz. The signal is finally impedance matched to the output via resistor R23 = 10Ω and stably output to the RCV_1ST_OUT node, providing a clean and matched signal source for the subsequent CBMG708 stage.

[0022] Regarding multi-channel programmable gain modules, such as Figure 4 As shown, the core of the single-stage programmable amplifier is the multiplexer U7 (CBMG708) and the operational amplifier U4 (CBM8091). This is the core feature: each of its eight selection terminals (S1 to S8) is connected in series with a gain resistor of a different value (R25, R33, R42, R50, R26, R34, R43, R51), which are then connected to the inverting input of the operational amplifier U4. This unique connection method ensures that each selected channel, due to the different series resistances, constitutes a non-inverting amplifier with a specific base gain.

[0023] By differentiating the parameters of the resistor elements, a base gain of 6dB was achieved for the 8 channels, as detailed below (see also Table 1): Near-field channels (S1~S3): R25=1kΩ, R33=2kΩ, R42=4.02kΩ, achieving base gains of 0dB, 6dB, and 12dB respectively.

[0024] Mid-range channels (S4~S6): R50=8.06kΩ, R26=18kΩ, R34=47kΩ, achieving base gains of 18dB, 24dB, and 30dB respectively.

[0025] Long-distance channels (S7~S8): R43=64.9kΩ, R51=127kΩ, achieving base gains of 36dB and 42dB respectively.

[0026] The control module can dynamically select the corresponding channel by sending a 3-bit binary code value to the address selection port (A0, A1, A2) of U7. For example, sending (A2,A1,A0) = (0,0,0) selects channel S1 with a gain of 0dB, suitable for close-range targets of 1~10m; sending (1,1,1) selects channel S8 with a gain of 42dB, suitable for distant targets of 80~100m.

[0027] The 6dB gradient channel-distance adaptation table is summarized below: Furthermore, such as Figure 6 The two-stage programmable amplifier shown has the same circuit principle and connection method as the first-stage programmable amplifier (…). Figure 4 The two channels are completely identical, forming the second-level gain compensation. By combining and gating different channels of the first and second levels, the total gain can be extended from 0dB to 84dB. The specific correspondence is shown in the code value-distance adaptation table below: Regarding cascaded filter units, such as Figure 5 The secondary filter: The signal output from the first-stage programmable gain stage (RCV_2ST_OUT) is input through resistor R32 = 13.3kΩ. R32, along with capacitors C33 = 100pF and C38 = 100pF, forms a dual-capacitor RC low-pass filter network to further purify the signal frequency band. Resistor R46 is a bias resistor, assisting in forming a DC path.

[0028] like Figure 7 The three-stage filter: its circuit structure is similar to that of a two-stage filter ( Figure 5 The signal output from the second-stage programmable amplifier is completely consistent with the signal output from the second-stage programmable amplifier. The signal is then filtered to ensure the bandwidth purity of the output signal RCV_OUT.

[0029] Specifically, the control module adopts a dual-core architecture of FPGA and ARM. The FPGA's general-purpose I / O ports are directly connected to the address selection ports A0, A1, and A2 of the CBMG708 to provide fast and accurate channel switching control signals. The FPGA and ARM share data at high speed through the chip's internal block RAM (BRAM), with the ARM responsible for gain decisions and the FPGA responsible for hardware timing execution. Example

[0030] Combination Figure 8 The software flowchart shown below provides a detailed explanation of the signal compensation control method of the present invention.

[0031] This sonar signal compensation method, based on the aforementioned circuit embodiment, specifically includes the following steps: Step S101: System initialization.

[0032] After the system is powered on, the FPGA and ARM complete the initialization configuration, and the ARM loads the preset code value-distance adaptation table from the non-volatile memory.

[0033] Step S102: Receive distance information and calculate code value.

[0034] The ARM processor obtains the current target range from the host computer's display and control software via a communication interface (such as UART, SPI, etc.). Subsequently, the ARM queries the code value-distance adaptation table to calculate the channel strobe code values ​​for the first and second stage programmable gain stages required for that distance.

[0035] Step S103: Write the control code value.

[0036] The ARM processor calculates the channel strobe code value and writes it to a specified address in the block RAM (BRAM) shared with the FPGA via the internal bus.

[0037] Step S104: Determine the enable signal.

[0038] The FPGA continuously checks the enable signal. If the enable signal is invalid, it continues to wait; if the enable signal is valid (i.e., high level '1'), the process proceeds to step S105.

[0039] Step S105: Read the code value and output the control signal.

[0040] The FPGA reads the channel selection code value written by the ARM, starting from the initial address of the BRAM. Then, the FPGA converts the received code value into a specific level signal and outputs it to its corresponding I / O pin, directly driving the address ports A0, A1, and A2 of the CBMG708, thereby selecting the signal channel with a preset specific gain.

[0041] Step S106: Address increment and loop.

[0042] After the FPGA completes one code value output, it automatically increments the BRAM read address by 1, preparing to read the control code value for the next cycle. When a complete working cycle (e.g., 1ms) ends, the process returns to the initial address and begins the next round of signal acquisition and gain compensation loop, thereby achieving real-time, dynamic, and precise compensation of the sonar signal across all distances.

[0043] In summary, the specific signal amplitude deviations in the sonar system compensation scheme are as follows: The operational amplifier schematic is shown below. Figure 2 Feedback resistor: (Accuracy ±0.1%), Grounding resistance: (Accuracy ±0.1%) Theoretical gain calculation (Corresponding to 12dB gain) Gain bias introduced by resistance error, due to the difference and There is a maximum error of ±0.1%. Calculate the maximum and minimum gains respectively: Maximum gain:

[0044] Minimum gain:

[0045] Gain deviation percentage: The schematic diagram of the first-stage filter is shown in Figure 3. Calculate the impedance matching error. (Accuracy ±0.1%) (Accuracy ±1%) Total matching impedance:

[0046] Impedance error:

[0047] Amplitude loss error: , This is the inherent input impedance of the CBMG708.

[0048] The schematic diagram of the first-stage programmable amplifier is shown in Figure 4. Calculate the amplitude consistency during channel switching. CBMG708 On-resistance: , the maximum deviation: Near-distance channel load resistance: (Minimum load resistance) Amplitude loss deviation formula (Because the load resistance is much greater than 50Ω, the error is much lower than the theoretical estimate.) After the CBMG708 undergoes multi-channel switching, the minimum equivalent input resistance presented by the subsequent circuitry (such as operational amplifiers, filter networks, etc.) is... ) The CBMG708 switching delay is ≤14ns, the lowest sonar signal frequency is 50Hz (period 20ms), and the delay percentage is: It is negligible and has no amplitude distortion.

[0049] The schematic diagram of the two-stage filter is shown in Figure 5. Calculate the filter flatness. Filter resistor: (Accuracy ±0.1%), Filter capacitor: (Accuracy ±5%) (Accuracy ±5%) capacitance and capacitor Total capacity in parallel:

[0050] The cutoff frequency is: (The highest operating frequency of sonar is 50kHz, which is far lower than...) ) 50kHz signal amplitude attenuation:

[0051] The attenuation error is ≤0.1dB (caused by RC parameter error), corresponding to an amplitude fluctuation of ≤0.1%.

[0052] Total deviation summation Therefore, through item-by-item analysis and summation of operational amplifier gain error, impedance matching error, multiplexer channel conduction consistency error, and filter network flatness error, the overall gain error of the circuit in this invention is controlled within 0.53%, far below the design target of ≤3%. This fully verifies the effectiveness and superiority of the proposed "multiplexer + differentiated gain resistor" architecture in achieving high-precision, high-consistency gain compensation.

[0053] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A compensation circuit for a sonar system based on multi-channel switching, characterized in that, include: The signal input node is used to receive the raw electrical signals generated by the sonar transducer; A signal conditioning unit, connected to the signal input node, is used to perform preliminary amplification and noise filtering on the original electrical signal; At least one programmable gain stage, the core of which includes a multiplexer and an operational amplifier; The multiplexer has a common terminal and multiple selection terminals. Each selection terminal is connected in series with a gain resistor of different values ​​and then connected to the inverting input terminal of the operational amplifier, thereby forming multiple signal channels with different basic gains. The control module, electrically connected to the address selection port of the multiplexer, is configured to output a channel selection signal based on the target's effective distance to dynamically select the corresponding signal channel. A cascaded filtering unit, connected to the output of the programmable gain stage, is used to perform frequency band purification on the gain-compensated signal. By selecting channels with different gains, it achieves accurate compensation for sonar signals at different distances, ensuring that the output signal amplitude is higher than the detection threshold.

2. The sonar system compensation circuit according to claim 1, characterized in that, The base gain of multiple signal channels is preset in 6dB increments, covering a range from 0dB to 42dB.

3. The sonar system compensation circuit according to claim 1, characterized in that, The specific configuration of the gain resistor is as follows: The gain resistors for the channels used for near-field signal compensation are 1kΩ, 2kΩ, and 4.02kΩ, which correspond to 0dB, 6dB, and 12dB base gains, respectively. The gain resistors for the channels used for mid-range signal compensation are 8.06kΩ, 18kΩ, and 47kΩ, which correspond to 18dB, 24dB, and 30dB base gain, respectively. The gain resistors for the channels used for long-distance signal compensation are 64.9kΩ and 127kΩ, corresponding to a base gain of 36dB and 42dB, respectively.

4. The sonar system compensation circuit according to claim 1, characterized in that, It includes two programmable gain stages, and by combining and gating different signal channels in the two stages, an extended gain range from 0dB to 84dB can be achieved.

5. The sonar system compensation circuit according to claim 1, characterized in that, The operational amplifiers used in the signal conditioning unit and the cascaded filtering unit are domestically produced CBM8091 chips.

6. The sonar system compensation circuit according to claim 1, characterized in that, The control module includes an FPGA and ARM dual-core processor architecture; The ARM processor is used to query the pre-stored code value-distance adaptation table based on the target operating distance and generate the channel selection code value. The FPGA is used to receive the channel selection code value and generate corresponding timing control signals to drive the multiplexer.

7. The sonar system compensation circuit according to claim 6, characterized in that, Meanwhile, the ARM processor and FPGA interact with each other through a shared block memory.

8. The sonar system compensation circuit according to claim 1, characterized in that, The switching logic of the multiplexer is configured to suppress transient interference during switching, and its channel switching delay time is ≤14ns.

9. The sonar system compensation circuit according to claim 1, characterized in that, The overall gain error of the circuit is controlled within 3%, which is determined by the accuracy of the gain resistor, the consistency of the multiplexer channel on-resistance, and the amplitude-frequency characteristics of the filter network.

10. A sonar signal compensation method, characterized in that, The method, implemented based on the sonar system compensation circuit according to any one of claims 1-9, comprises: Step S1: Receive the raw electrical signal from the sonar; Step S2: Perform preliminary amplification and first-stage filtering on the signal; Step S3: Based on the target operating distance, signal channels with different basic gains are preset by controlling the address gating of the multiplexer; Step S4: Perform calculations and amplification on the signal of the selected channel; Step S5: Perform secondary and tertiary filtering on the amplified signal to output a sonar signal with clean frequency band and amplitude compensation.

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