Controller for superconducting qubits

Abstract

A superconducting controller for superconducting quantum bits is used for implementing a high-fidelity quantum gate through magnetic flux driving. The controller comprises an inductor which forms an inductance loop and is used for being coupled with a low-mutual-inductance quantum bit inductor; and a pulse shaping circuit for applying a current pulse having a predetermined shape to the inductor. The pulse shaping circuit includes: a superconducting circuit for outputting a single flux quantum (SFQ) pulse; and a digital counting circuit for generating the shape of the current (flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current of the inductor by one SFQ pulse at a time.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to U.S. Patent Application No. 18 / 197,033, entitled “Controller for Superconducting Quantum Bits”, filed on May 12, 2023. Technical Field

[0003] The embodiments described herein relate to quantum computing devices and systems including superconducting quantum bit (Qubit) controllers. Background Technology

[0004] Quantum computing enables a new paradigm of computing. Traditional computers store and manipulate information using bits, which are represented by two states, "0" and "1" (such as high and low signals). Unlike traditional bits, which are exactly in one of two states, information in quantum computing is stored in qubit devices and in quantum superposition states, which can be formed by manipulating such qubits. Attached Figure Description

[0005] Figure 1A This is a schematic diagram of an embodiment of a superconducting quantum bit.

[0006] Figure 1B This is an energy level diagram for an example of a fluxonium quantum bit.

[0007] Figure 2 The image shows a Bloch sphere.

[0008] Figure 3 The figure shows an example of a fluxonium qubit coupled to a controller.

[0009] Figure 4A The image shows an example of a single flux quantum circuit (SFQ).

[0010] Figure 4B The image shows an example of an SFQ pulse.

[0011] Figure 5 The illustration shows an example of a pulse shape that can be generated by a pulse shaping circuit in one embodiment.

[0012] Figures 6A to 6E To indicate the application Figure 5 A schematic diagram of the Bloch sphere with quantum state precession after the pulse is shown.

[0013] Figure 7A This is a schematic diagram of an embodiment of a pulse shaping circuit used to generate trapezoidal pulses and coupled to qubits.

[0014] Figure 7B This is a schematic diagram of an embodiment of a pulse shaping circuit used to generate triangular pulses and coupled to qubits.

[0015] Figure 8A For use Figure 7A A schematic diagram of an embodiment of a pulse counter circuit.

[0016] Figure 8B For Figure 7A A schematic diagram of a counter implementation (without pulse output) for the circuit.

[0017] Figure 8C for Figure 8A A further detailed schematic diagram of the pulse counter shown.

[0018] Figure 8D This is a schematic diagram of an NDRO switch embodiment.

[0019] Figure 8E This is a schematic diagram of an embodiment of a parallel programmable counter.

[0020] Figure 8F This is a schematic diagram of an embodiment of a serially programmable counter.

[0021] Figure 9 The illustration shows an example of a double-pulse shape that can be generated by a pulse shaping circuit.

[0022] Figure 10 In one implementation, it is coupled to a quantum bit and used to generate Figure 9 The diagram shows an embodiment of a pulse shaping circuit for dual pulses.

[0023] Figure 11 With a clock period of 47.5 ps and d f Plot of quantum gate error versus Josephson energy at 0.003.

[0024] Figure 12 The graph shows the relationship between quantum gate error and the waiting time between two pulses in a double-pulse curve.

[0025] Figure 13 The graph shows the relationship between quantum gate error and clock period.

[0026] Figure 14 The graph shows the relationship between quantum gate error and magnetic flux coupling.

[0027] Figure 15 The diagram shows a pulse shape that can be generated by a pulse shaping circuit in one embodiment. This pulse shape is a variant of a simple trapezoid.

[0028] Figure 16 For E L / h=0.7GHz, EC / h=0.9GHz, E J Quantum gate error and its relationship with parameters of 5.82 GHz, trapezoidal time = 3 ns, and clock period = 45 ps Figure 15 Pulse integral relationship diagram of pulse shape.

[0029] Figure 17 This is a schematic diagram of the control layers of a quantum computer.

[0030] Figure 18 This is a schematic diagram of an embodiment of a low-temperature thermostat, wherein, Figure 17 The control layer shown is located inside the cryogenic thermostat.

[0031] Figure 19 This is a schematic diagram of an embodiment of a pulse shaping circuit coupled to multiple qubits via a demultiplexer.

[0032] Figure 20 for Figure 19 A schematic diagram of an embodiment of the demultiplexer used.

[0033] Figure 21 for Figure 19 A schematic diagram of an embodiment of the pulse shaping circuit used in the circuit.

[0034] Figure 22 This is a schematic diagram of an embodiment of a pulse shaping circuit used to generate dual pulses and coupled to multiple qubits via a demultiplexer.

[0035] Figure 23 for Figure 22 A schematic diagram of an embodiment of the demultiplexer used in the circuit.

[0036] Figure 24 for Figure 22 A schematic diagram of an embodiment of the pulse counting circuit used in the circuit. Detailed Implementation

[0037] To realize qubits in quantum computing, various architectures have been proposed, one of which is the superconducting circuit. These superconducting qubits need to operate at sub-Kelvin temperatures below the superconducting transition critical temperature. Controlling and reading out these qubits is difficult, and traditionally they are achieved by exciting the qubits with microwave pulses. However, such control schemes require providing microwave signals to the qubits within the cryostat via high-quality coaxial cables. Specifically, to provide the control signal from outside the cryostat to the qubits located inside, each qubit often requires at least one or two wires. Thus, the number of coaxial cables required (with corresponding connectors, filters, and attenuators) is proportional to the number of qubits, making it difficult to scale up the system due to space and reliability constraints, as well as the increased thermal load on the cryostat caused by microwave power consumption and cable heat flow.

[0038] In one embodiment of the present disclosure, a superconducting quantum bit controller is provided, the controller comprising:

[0039] An inductor that forms an inductor loop and is used for coupling with a low mutual inductance quantum bit inductor;

[0040] A pulse shaping circuit for applying a current pulse of a predetermined shape to the inductor, the pulse shaping circuit comprising:

[0041] A superconducting circuit for outputting single flux quantum (SFQ) pulses; and

[0042] A counting circuit is used to generate the shape of the current pulse by controlling the number of SFQ pulses applied to the inductor in a manner that increments or decrements the current of the inductor by one SFQ pulse at a time.

[0043] The controller described above is based on a single flux quantum (SFQ) circuit, which can be placed near the qubit within a dilution refrigerator or cryostat. Both the qubit and the controller can be placed within a cryogenic measurement system at a temperature below the superconducting transition temperature.

[0044] In the above embodiment, the pulse shaping circuit is used to apply current (flux) pulses. The SFQ circuit outputs low-power SFQ pulses and can be driven at high clock frequencies (e.g., 25~30GHz or higher). This type of SFQ circuit is a conventional superconducting circuit.

[0045] The aforementioned controller is inductively coupled to the qubit, thereby enabling it to change the quantum state precession frequency in response to variations in the inductor current. The inductor can be in the form of an inductor loop, which is used for inductive coupling with the qubit. Fine control of the inductor current can be achieved by increasing or decreasing the superconducting loop flux with SFQ pulses. The flux through the conductive loop is proportional to the current flowing within the loop.

[0046] In one embodiment, a counting circuit is used to generate the shape of the current pulses (or equivalent flux pulses) of the superconducting loop by applying a predetermined number of SFQ pulses (positive SFQ pulses for increasing the flux within the loop) from one side, or applying a predetermined number of SFQ pulses (negative SFQ pulses for decreasing the flux within the loop) from the other side, or by applying a set time (plateau) between the flux increase / decrease. The counting circuit also allows setting the delay between the sequentially generated current (flux) pulses.

[0047] The aforementioned controller allows the application of trapezoidal pulses. Accordingly, a counting circuit is used to generate current pulses whose shape includes: a rising edge, in which a positive SFQ pulse is gradually applied; a plateau region, in which the current applied to the inductor is fixed (no positive or negative SFQ pulse is applied); and a falling edge, in which the current applied to the inductor is reduced by gradually applying a negative SFQ pulse. Further, the pulse shape can be adjusted, for example, by providing multiple plateaus, rising edges, and falling edges.

[0048] In one embodiment, the superconducting circuit includes a Josephson junction (JJ) and is used to output an SFQ pulse, a voltage pulse having a quantized area due to a 2π phase slip across the Josephson junction. The superconducting circuit can be at least one of the following types: Fast Single Flux Quantum (RSFQ); ERSFQ, eSFQ, RQL, xSFQ, xeSFQ, DSFQ, bSFQ, PCL, and variants thereof; and a quantum flux parametric converter (QFP) based circuit: AQFP, QFP, PQ, and variants thereof.

[0049] In one embodiment, the counting circuit includes a first counter for counting and limiting the number of positive SFQ pulses and a second counter for counting and limiting the number of negative SFQ pulses. Both the first and second counters may include registers. Such registers may include multiple superconducting T-flip-flops (TFFs).

[0050] In addition, a third counter may be provided to control the duration during which no pulse is applied to the coupled inductor.

[0051] Each register can be used to output a carry signal when its limit is reached. The controller is configured as follows: the first, second and third counters are arranged in sequence; the carry signal is sequentially led from the previous counter to the next counter to start the next counter in sequence.

[0052] The controller can be used to generate pulse shapes with repeating structures, wherein the controller further includes a fourth counter for controlling the time between the structures of the repeating pulse shape. The structure can be a trapezoid or a variation thereof, such as a triangle or a trapezoid with one or more other platforms (e.g., a shape formed by multiple trapezoids overlapping each other). The structure can be either symmetrical or asymmetrical.

[0053] In another embodiment, the controller is used to control multiple qubits via a demultiplexer. For example, multiple inductors may be provided, wherein each of the multiple inductors is used to couple to a corresponding qubit, respectively.

[0054] Accordingly, each inductor may have a positive input terminal and a negative input terminal at both ends. The positive input terminal is used to increase the magnetic flux through its corresponding inductor, and the negative input terminal is used to decrease the magnetic flux through its corresponding inductor. The demultiplexer is connected to the positive input terminal and the negative input terminal of each inductor.

[0055] The demultiplexer can be used to receive a pulse stream and a selection signal, which controls which of the corresponding positive and negative input terminals of each inductor receives the pulse stream. This structure, which uses the demultiplexer to control the output of both positive and negative input terminals, allows a single-pulse counter to output pulses to either the positive or negative input terminal. The polarity of the pulses output to the inductors is controlled by the demultiplexer.

[0056] For a specific selected qubit, a programmable counter can be used to adjust the pulse shape parameters (including rising and falling edges, plateaus, and wait times), and this counter can be reprogrammed for different numbers of pulse counts. Furthermore, Figure 20 and Figure 23 The demultiplexer design shown is programmable to select multiple qubits simultaneously. In this case, the selected qubits are controlled by pulse shapes with the same parameters.

[0057] The demultiplexer may include a shift register, wherein the selection signal is provided sequentially along the shift register. This structure allows the demultiplexer to employ superconducting logic of the SFQ or QFP type.

[0058] The shift register may include sequentially arranged nondestructive readout (NDRO) elements, each connected to a corresponding positive or negative input. This shift register structure of the demultiplexer can impose limitations when more complex pulse shapes are required: a pattern applied to one pair of NDRO elements may be shifted to the next pair, which may control another qubit, and the pattern may not be applicable to that other qubit. Therefore, in one embodiment, the shift register further includes dummy elements disposed between the NDRO elements, such dummy elements allowing the selection signal to be stored before being sequentially passed to the next NDRO element.

[0059] In one embodiment, the controller of claim 9, wherein the counting circuit includes two other counters.

[0060] In one embodiment, the pulse shape is used to enable the qubit inductively coupled to the controller to perform qubit operations.

[0061] In one implementation, the controller is used to control at least one of the following parameters:

[0062] Platform size;

[0063] Rising edge size;

[0064] Falling edge size;

[0065] The delay between sequentially generated magnetic flux pulses;

[0066] The delay before the first magnetic flux pulse begins oscillation.

[0067] In use, the controller is inductively coupled to the qubit. In one embodiment, the qubit is an inductive flux-type qubit. For example, the qubit can be a fluxonium-type qubit.

[0068] However, it should be noted that when there is no explicit inductor, qubits can be controlled by magnetic flux bias. For example, transmon qubits can be magnetically connected to a superconducting quantum interference device (SQUID) loop (sometimes called a split Josephson junction) and controlled by the SQUID loop.

[0069] The quantum bits in the quantum computer described in this article differ from traditional bits in that these quantum bits maintain a quantum superposition of a first logical state (0) and a second logical state (1). The quantum bits can be considered to have two quantum energy levels:

[0070]

[0071] Figure 1A This is a schematic diagram of a fluxonium qubit. Other types of qubits can also be used. The first embodiment uses a fluxonium qubit as an example. This fluxonium qubit includes a Josephson junction (JJ) 1, a capacitor 3, and an inductor 5 connected in parallel. Wherein, E... J is the coupling strength of the Josephson junction; Ec is the energy required to increase the capacitor charge by e, where e is the charge of a single electron; E L The inductance energy of a quantum bit.

[0072] A Josephson junction comprises a tunneling barrier between two superconductors. A Fluxonium qubit is a type of so-called flux qubit, wherein the two energy levels constituting the qubit are a superposition of two energy states, which, for example, correspond to currents flowing through the Josephson junction in opposite directions. In this embodiment, the aforementioned inductor is shown as an inductor. However, this inductor can also be implemented using a Josephson junction.

[0073] The above-mentioned fluxonium qubit structure generates Figure 1B The energy level diagram shown is illustrated. The two lowest energy levels in this diagram are selected as the two energy levels of the qubit mentioned above.

[0074] With the help of Figure 2 The Bloch sphere shown can best visualize the two states and the transitions between them. The ground state... Shown at the top, excited state (Pure state) is shown at the bottom. The quantum state of a qubit is represented by the position of a vector on the Bloch sphere. Any vector not located at a vertical pole represents a superposition state. The central plane (equator) of the Bloch sphere represents... The equilibrium superposition state.

[0075] To transition a quantum bit from its intrinsic energy state to a superposition state, energy must be provided to the quantum bit to trigger a transition between the ground state and the excited state. Figure 3 In the schematically illustrated embodiment, this objective is achieved through a control circuit 11 inductively coupled to the qubit. The control circuit 11 senses a current in its inductor 13, which in turn senses a magnetic flux passing through the qubit. To obtain the correct excited superposition state, the current in the inductor within the control circuit needs to be carefully adjusted over time to have a precise value at a specific time.

[0076] To achieve the above control effect, in one embodiment, the control circuit 11 includes a single flux quantum (SFQ) circuit. Figure 4AThe diagram shows a single flux quantum (SFQ) circuit 101. In a simplified form, the SFQ circuit is a loop consisting of a superconducting wire and a Josephson junction 103. The Josephson junction 103 can maintain (store) the magnetic flux. A single quantum, where, h is Planck's constant, and e is the elementary charge, i.e., the charge carried by a single electron (1.6 × 10⁻⁶). -19 C). Josephson junctions enable the insertion and release of single flux quantum (SFQ) in this loop. The series-connected pairs of Josephson junctions (J2, J3) conditionally release the stored SFQ upon the arrival of the clock / reset SFQ. With the release of the SFQ, the loop generates and outputs an SFQ pulse. The area under the curve of the SFQ pulse generated in this manner is constant and corresponds to the quantum flux. .

[0077] By applying magnetic flux to sub-bits via an SFQ circuit, the following two significant advantages can be achieved:

[0078] 1) Quantized single-flux quantum pulses allow for precise control of the energy supplied to the qubits;

[0079] 2) The SFQ circuit can be placed close to the quantum bits in a dilution refrigerator or cryostat, thereby minimizing the number of connections to the level of room temperature electronic devices and reducing control signal delay.

[0080] SFQ circuits can be used to generate flux pulse curves by using SFQ pulses within a superconducting induction loop. The magnetic flux is gradually increased by increments to generate a magnetic flux curve that allows the quantum state of the qubit to change.

[0081] Figure 4B The diagram shows the time-varying variation of the SFQ pulse. The area of ​​the SFQ pulse remains constant. The SFQ pulse width t... SFQ ≈2τ_ SFQ ≈2Ф0 / IcR. In the case of a niobium junction, the limit is... In complex RSFQ circuit scenarios, the actual f clock ≈1 / (10tSFQ). SFQ pulse energy ≈¾Ф0Ic≈2×10 -19 Joules (Ic≈100μA when operating at 4K) or 2×10 -20 Joules (Ic≈10μA when operating at milliKelvin). Under low power conditions, the maximum clock frequency of an integrated circuit (IC) can be approximately hundreds of GHz.

[0082] Figure 5The diagram shows a trapezoidal magnetic flux curve. This shape is obtained by accumulating single magnetic flux quanta. The vertical axis Y represents the number of positive single magnetic flux quanta applied to the inductor L of circuit 11. The horizontal axis X represents time corresponding to the number of clock cycles inside the controller, in arbitrary units. Over time, the number of magnetic flux quanta increases by 1 per unit time until it reaches 16 (in this embodiment). After this value remains constant (plateau) for a period of time, the number of magnetic flux quanta begins to decrease, decreasing by one quantum at a time, until it becomes 0.

[0083] Figures 6A to 6E Combined with Bloch's sphere Figure 5 The mechanism by which quantum state transitions occur due to current curves.

[0084] Figure 6A The quantum state shown is a pure state pointing towards the bottom of the Bloch sphere. First, a single magnetic flux quantum is applied to the inductor to provide energy to the quantum bits, thus initiating a quantum state transition. For example... Figure 6B As shown, the arrows indicate the quantum state transitioning from a pure state. The quantum state deflects towards the equator. At this point, even if the magnetic flux quantum value supplied to the inductor remains constant, the quantum state continues to deflect. However, by increasing the magnetic flux quantum, the quantum state transition can be accelerated to its maximum speed. Figure 6C The figure shows the midpoint of the entire quantum state transition process. The quantum state transition is maintained at its maximum velocity ( Figure 5 (As shown in the trapezoidal platform), until the quantum state begins to approach its final target position. At this time, the magnetic flux quanta applied to the inductor 13 decrease one by one, causing the quantum state transition as follows: Figure 6D The speed was reduced as shown until it reached... Figure 6E The final target position is located on the plane of the center of the Bloch sphere (in this case, it is in line with the y-axis).

[0085] When using the above system for qubit control, excellent fidelity can be achieved. This high fidelity indicates that the control over the qubit evolution process during quantum gate formation is extremely precise and reproducible with minimal error.

[0086] Figure 7A The image shown is used to generate Figure 5 A flux curve controller 201. Controller 201 is used to control qubit 203. Qubit 203 (as described above) Figure 1A and Figure 1B The aforementioned fluxonium qubits are capable of inductive coupling.

[0087] The controller 201 includes an inductor 205 for inductive coupling with the quantum bit 203. It should be noted that, although... Figure 7AThe qubit 203 shown has an inductor, but even without a specific inductor element, the qubit can still have inductance. Specifically, the qubit can be constructed from a SQUID (sometimes called a split junction) to be inductively coupled to the magnetic flux from the controller, thus still achieving inductive coupling.

[0088] The following, with reference to Figure 8, provides a more detailed description. Figure 7A The circuit shown includes some components. Overall, the circuit comprises a first pulse counter (nPC1) 209 and a second pulse counter (nPC2) 213. The first pulse counter (nPC1) 209 outputs a positive SFQ pulse 211. The second pulse counter (nPC2) 213 outputs a negative SFQ pulse 215. The term "positive" or "negative" for the SFQ pulse is an imaginary designation; it merely describes whether the pulse increases or decreases the magnetic flux in the inductor loop 205. The first pulse counter 209 outputs pulses to the inductor 205 to increase the loop flux. The pulses from the first pulse counter 209 are incrementing pulses, increasing by one pulse at a time, i.e., accumulating one unit at a time. to form Figure 5 The trapezoid shown has an upward slope.

[0089] When the first pulse counter 209 reaches its set value, it stops outputting the positive SFQ pulse 211 to keep the magnetic flux level in the inductor loop 205 constant. This stage corresponds to... Figure 5 The top edge of the trapezoid. Furthermore, when the first pulse counter 209 reaches a set value, it also outputs a carry signal. This carry signal is led to the second delay unit 219. After the second delay unit 219 counts the set time, it outputs a carry signal to the second pulse counter 213 to start the second pulse counter 213. After the second pulse counter is started, it is used to count and output SFQ pulses with opposite polarity to the first pulse counter 209. These pulses with opposite polarity reduce the magnetic flux in the inductor loop 205, thereby causing a decrease in magnetic flux. This decrease in magnetic flux is gradual, corresponding to... Figure 5 The downward slope in the middle. Thus, by using the first pulse counter 209 and the second pulse counter 213, it is possible to achieve Figure 5 The magnetic flux curve is shown.

[0090] Figure 7A The diagram also shows two components: a first delay unit 217 and a second delay unit 219. The first delay unit 217, the second delay unit 219, the first pulse counter 209, and the second pulse counter 213 are all counters, each receiving a clock signal 221. The first delay unit 217 sets the time before the trapezoidal pulse begins oscillation. The second delay unit 219 sets the plateau hold time of the trapezoidal pulse. Any of the above counters can be implemented using a fixed number of bits, or... Figure 8E and Figure 8F The programmable counter shown is designed and implemented as a programmable counter. The first delay unit 217, the second delay unit 219, the first pulse counter 209, and the second pulse counter 213 have very similar internal structures.

[0091] Figure 7B The diagram shows a variant of the pulse shaping circuit used to generate triangular pulses (i.e., pulses with a plateau duration of zero). In this variant, the second delay unit 219 is not required.

[0092] Figure 8A These are schematic diagrams of the first and second pulse counters. Figure 8B This is a schematic diagram of the first and second delay units. Their internal structures are identical, but... Figure 8B It only outputs the carry signal, not the pulse.

[0093] Figure 8C The diagram above provides a further detailed view of the internal structure. The clock input signal is an external input signal, such as a sine wave or any other signal with a periodic waveform. This input signal is converted into SFQ pulses by a standard DC-to-SFQ converter, thereby converting the input periodic waveform into a clock SFQ pulse stream. Examples of usable DC-to-SFQ converters can be found in the following two papers: V.K. Kaplunenko, M.I. Khabipov, V.P. Koshelets, K.K. Likharev, O.A. Mukhanov, V.K. Semenov, I.L. Shevchenko, and A.N. Vystavkin, Experimental Study of RSFQ Logic Elements, *IEEE Transactions on Magnetism*. Magn.), Vol. 25, No. 2, pp. 861-864, March 1989; S.V. Polonsky, V.K. Semenov, P. Bunyk, A.F. Kirichenko, A. Kidiyarova-Shevchenko, O.A. Mukhanov, P. Shevchenko, D. Schneider, D.Y. Zinoviev, K.K. Likharev, Novel RSFQ Circuit, IEEE Trans. Appl. Superconducting, Vol. 3, No. 1, pp. 2566-2577, March 1993.

[0094] Here, a counter 251 is provided that transmits the SFQ pulse clock from the input to the output when the nondestructive readout (NDRO) switch 253 is turned on. Examples of usable NDRO switches are listed below: O.A. Mukhanov, S.V. Rylov, V.K. Semenov, S.V. Vyshenskii, RSFQ Logic Arithmetic, IEEE Transactions on Magnetism, Vol. MAG-25, No. 2, pp. 857-860, March 1989.

[0095] The output signal of the aforementioned counter turns off the NDRO switch 253, thereby generating the set number of output pulses for the counter 251. This counter can be a fixed counter (clock pulse count value is 2). n It can also be a programmable counter (the clock pulse count value is a preset value).

[0096] Figure 8D This is a schematic diagram of an NDRO switch. The NDRO switch transmits a signal from its input to its output based on whether the switch is "on" or "off". The on / off state is controlled by at least one other input.

[0097] Figure 8E and Figure 8F Two implementation methods for programmable counters are shown in further detail. Figure 8E In the text, the counter is composed of T-type flip-flops (TFF) (V.K. Kapronenko, M.I. Khabibov, V.P. Kosiletz, K.K. Likharev, O.A. Mukhanov, V.K. Semyonov, I.L. Shevchenko, A.N. Vestavkin, Experimental Study of RSFQ Logic Elements, IEEE Transactions on Magnetism, Vol. 25, No. 2, pp. 861-864, March 1989; S.V. Borensky, V. The circuit consists of T-type flip-flops (TFFs) connected in series and then connected to a serial-to-parallel programming interface. These TFFs are RSFQ toggle flip-flops (TFFs) used to output an SFQ pulse every other input SFQ pulse. These series-connected TFFs are used to form fixed counters for the first and second delay units, which output carry signals with a fixed delay time. These carry signals serve as the start-up input signals for pulse counters 209 and 213. Figure 8FIn this implementation, the programming function is achieved by applying an SFQ pulse directly to the input of the first TFF before applying the start-up input signal. In both implementations, the offset of the counter is set by the applied data to limit the number of pulses counted after the start-up SFQ signal. For example, a seven-bit counter counts 2. 7 =128 clock pulses. If the programming offset data is 18, the programmed counter will only count 128-18=110 clock pulses.

[0098] The above describes a simplified case with only a single trapezoid. However, in addition, two or more trapezoids or other shapes can be formed by increasing and decreasing the magnetic flux in SFQ pulses. Figure 9 The diagram shows another example of a magnetic flux curve, which is a double trapezoidal curve. However, curves with three or more trapezoids can also be used.

[0099] Figure 10 The diagram shows a circuit that can be used to generate double-triangle / trapezoidal curves. (And...) Figure 7A Similarly, this system also provides a positive pulse to the inductor loop 205 through the positive output / input terminal 211 and a negative pulse to the inductor loop 205 through the negative output / input terminal 215.

[0100] exist Figure 10 In the circuit, the output terminal of the first pulse counter nPCt1 401 is directly connected to the positive pulse output terminal 211. The type of the first pulse counter 401 is a combination of the above. Figure 8A and Figure 8C The counter is capable of outputting SFQ pulses and carry signals. When the first pulse counter 401 reaches its set number of pulses (first threshold), the counter outputs a carry signal, which is then fed to the second counter t2 403. The second counter 403 cannot output SFQ pulse trains, only carry signals. The type of the second counter 403 is a combination of the above. Figure 8B The aforementioned counter. The second counter 403 outputs a carry signal when it reaches its threshold, hereinafter referred to as the second threshold. The carry signal is input to a third pulse counter nPC t3 405, which outputs a pulse applied to the inductor loop 205 in the opposite direction to the output pulse of the first pulse counter 401. That is, the pulse output by the third pulse counter 405 is used to reduce the magnetic flux applied to the inductor loop 205. The type of the third pulse counter is a combination of the above. Figure 8A and Figure 8C The aforementioned counter.

[0101] When the third pulse counter 405 reaches its threshold (the third threshold), it outputs a carry signal, which is then sent to the fourth counter t4 407. The fourth counter 407 is also of the above combination. Figure 8B The type that can output a carry signal but not a pulse. The fourth counter 407 is used to separate the two trapezoids in the double trapezoid curve from each other. Once the fourth counter reaches the counting threshold (fourth threshold), a carry signal is output, which is transmitted to the first TFF 409, which in turn transmits a start signal to the first counter 401.

[0102] Subsequently, the above process is repeated: when the first counter reaches the first threshold, it outputs a carry signal to start the second counter 403; when the second counter 403 reaches the threshold, it outputs a carry signal to start the third counter 405; the third counter 405 is set with a negative ramp. At this point, this process can be stopped, or the second set of trapezoidal pulses can be started again.

[0103] In the following figures, the performance of the fluxonium single-qubit gate is analyzed using the oscillation of a triangular pulse (i.e., a trapezoidal pulse with a plateau duration of zero) as an example. This quantum gate is implemented by rapidly detuning the magnetic flux passing through the superinductor loop (qubit), wherein... Figure 9 Two identical trapezoidal pulses of the type shown are separated from each other by a variable delay time.

[0104] Each pulse is a step size of magnetic flux change. The implemented stepped structure, in which, These are the parameters for the magnetic flux coupling model between the controller and the qubit. This refers to the magnetic flux quantum. The interval between each step of magnetic flux change is determined by the period. The external clock is determined. Accordingly, after the pulse is continuously applied until the first half of the image is formed, wait... One clock cycle; in another After one idle cycle, the magnetic flux is This step is progressively longer.

[0105] Figures 11 to 14 The diagram shows the combination. Figure 9 A set of results for Yπ / 2 (Y90 degrees) quantum gates formed by double trapezoidal pulses of the aforementioned type. Figures 11 to 14 In the diagram, the following parameters are used (except for those marked as variables):

[0106] fluxonium parameters:

[0107] E L / h=1.0GHz;

[0108] E C / h=1.2GHz;

[0109] E J / h=5.6GHz

[0110] (h is Planck's constant).

[0111] The above parameters are used to form Figure 1B The parameters of the fluxonium energy level diagram shown.

[0112] In all cases, each triangle has 16 fluctuating pulses. The clock period of the double-triangle pulse is 0.046 ns and can be varied for a single triangle pulse. The triangle pulse is a trapezoidal pulse with a plateau duration of zero.

[0113] Figure 11 Quantum gate error and Josephson energy E J Relationship diagram. It can be seen that up to 10 can be achieved. -4 And down to nearly 10 -6 Quantum gate error.

[0114] Figure 12 The graph shows the relationship between quantum gate error and waiting time (the time between two triangles, in ns).

[0115] Figure 13 Quantum gate error and clock period (other parameters and) Figure 11 (Similar) Relationship diagram. Figure 14 For fidelity and flux coupling (other parameters and) Figure 11 (Same) Relationship diagram. Flux coupling is the percentage of magnetic flux in each SFQ.

[0116] Although the above description uses magnetic flux curves with one or two trapezoids as examples, other magnetic flux curve shapes can also be used. (As described above...) Figures 6A to 6E As mentioned, magnetic flux alters the precession velocity of a quantum state on a Bloch sphere. Therefore, different shapes can be used to cause the quantum state to precess at different velocities. This allows for greater freedom in quantum gate optimization. The optimization refers to 2... N Discrete optimization of the structure.

[0117] Figure 15 As shown Figure 5 A variant of the trapezoid, this shape is a triangle with multiple platform sections. Although Figure 15 The magnetic flux curve shown is a symmetrical curve, but it does not necessarily have to be a symmetrical curve.

[0118] Figure 16 The graph shows the relationship between quantum gate error and pulse integral when the waiting time is 3.0 and the pulse time difference is 0.045.

[0119] The above describes the impact of some fluxonium parameters on quantum gate fidelity. One implementation aims to achieve a fidelity of less than 10 for various parameters that are difficult to achieve precisely due to differences in manufacturing processes. -3 Quantum gate fidelity. These parameters include the fluxonium Josephson energy E. J And decision The flux coupling between the traditional loop and the super flux inductor loop is shown in the graph above. This demonstrates that acceptable fidelity can be achieved even with imprecise parameters.

[0120] As mentioned above, other shapes besides those described can also be used. In one embodiment, a trapezoidal pulse is used as the initial shape, and additional pulses are added to its top to explore various shapes between a triangle (completely without a platform) and the original trapezoid (without additional pulses). Figure 7A In this embodiment, the basic trapezoid is composed of eight undulating pulses, resulting in a top edge length of 16. These 16 clock pulses are divided into: eight pulses for increasing the magnetic flux; and another eight pulses for symmetrically decreasing the magnetic flux. Thus, there are a total of 2 8 =256 combinations, and select the combination with the highest fidelity from them.

[0121] In the above text, fidelity is expressed as a function of the flux integral of the pulse sequence. Although this integral cannot be used to determine the quantum gate fidelity, based on the above relationship diagram, we can conclude that this integral can serve as a good estimation measure in the initial selection of a satisfactory pulse sequence.

[0122] As described above, the controller is used for inductive coupling with the qubit. Although the fluxonium qubit was used as an example above, other types of qubits with inductance can also be used. This inductance can be implemented either by a specific inductor integrated into the qubit or by the inherent inductance of the qubit.

[0123] To enable its use in quantum computers, multiple qubits are configured as follows: Figure 17 The qubit array 301 is shown. Control of the qubits is achieved through a digital qubit manager (DQM) 303. The DQM is used to implement qubit readout, control, and some data processing functions. In one embodiment, the controller is located within the DQM 303. Each qubit in the qubit array 301 is equipped with a controller.

[0124] In one implementation, in addition to the DQM 303 and the qubit array 301, a high-speed digital SFQ controller and a quantum error correction controller 305 are provided, which communicate with the DQM 303 to control the DQM 303 and provide conventional collaborative processing and quantum error correction functions.

[0125] In addition, in one embodiment, an interface 307 is provided as a high-speed digital SFQ coprocessor and a low-temperature CMOS storage and coprocessor, which provides conventional coprocessing and deep storage functions and serves as an interface for connecting to external computers and networks.

[0126] In one embodiment, the above four layers (i.e., quantum bit array 301, DQM 303, DQM control and error correction 305, and interface 307) are located in a low-temperature environment such as a cryostat or a dilution refrigerator. Figure 18 This is a schematic diagram of one possible structure of this type. The cryostat has multiple chambers maintained at different temperatures, with the innermost chamber 351 maintained at the lowest temperature. The innermost chamber 351 houses the qubit array 301 and the DQM 303. In one embodiment, the innermost chamber 351 is maintained at the lowest temperature. In the prior art, this temperature is approximately 20 mK. An intermediate chamber 353 houses the DQM control and error correction 305, which does not require the low temperatures required for the qubit array 301 and the DQM 303. The intermediate chamber 353 can be maintained at a temperature of approximately 600 mK. Accordingly, an interface 307 can be located in the outer chamber 355, which is maintained at a temperature of approximately 3 K.

[0127] Figure 19 This is a schematic diagram of the demultiplexing control of the Fluxonium qubit chip 501. Although this specific embodiment shows four qubits (503a~503d), any other number of qubits can be used. In conjunction with the above... Figure 7A As described above, each qubit 503a-503d is controlled by receiving an SFQ pulse applied from either the first side 507a (positive input terminal) to the inductor 511a inductively coupled to that qubit, or from the second side 507b (negative input terminal) to the inductor. The pulse applied from the first side is a positive pulse that increases the loop flux, and the pulse applied from the second side is a negative pulse that decreases the loop flux. The positive pulse generates a rising edge of a current pulse shape (such as a trapezoid), and the negative pulse generates a falling edge of a current pulse shape.

[0128] Positive input terminal 507a and negative input terminal 507b are connected to demultiplexing unit 505. Demultiplexing unit 505 is a digital unit that receives input pulse train 513 from generator 509, and receives demultiplexer load clock signal 517 or a signal from generator 509, as well as quantum bit selection signal 515.

[0129] The selection signal can be considered as providing a gating signal, which indicates which of the four qubits 503a-503d should be turned on (set to 1) between the positive input terminal 507a and the negative input terminal 507b; and which of the four qubits 503a-503d should be turned off (set to 0) between the positive input terminal 507a and the negative input terminal 507b. Each qubit has its own positive and negative input terminals.

[0130] For example, as shown in the figure, the selection signal is set to "10 00 00 00" in the first clock cycle, which means that the positive input terminal of the qubit 503d is turned on, and set to "01 00 00 00" in the second clock cycle, which means that the negative input terminal of the qubit 503d is turned on, and all other positive and negative input terminals are turned off.

[0131] Figure 20 This is one possible structure for the demultiplexer 505. The demultiplexer 505 includes an array of NDRO switches, each NDRO switch coupled to either the positive or negative input terminal of a qubit. Each NDRO element is further coupled to an input pulse train 513, such that each NDRO element acts as a switch, allowing or disallowing pulses in the pulse train 513 from being transmitted to the corresponding positive or negative input terminal coupled to that NDRO element. The dashed lines in the figure show the path of the input pulses to the positive or negative input terminal.

[0132] Whether an NDRO element allows pulses from pulse train 513 to be transmitted to the corresponding positive or negative input terminal is determined by a selection signal. Each NDRO element can be configured as a shift register, where the carry signal from each NDRO element in the register is used as an input signal to the "on" terminal of the next NDRO switch in the register; the "off" terminal of each NDRO element is connected to the clock line. Thus, the selection signal can be used to enable a "1" from an NDRO element coupled to the positive input terminal to be transmitted to an adjacent NDRO element coupled to the negative input terminal of the same qubit, thereby allowing the qubit to be controlled to achieve the aforementioned combination. Figure 10 The shape of the magnetic flux pulse.

[0133] The generator 509 used to generate the pulse train 513 is in some respects similar to Figure 10The circuit is similar, but the difference is that generator 509 only needs to generate the increasing (ramp) portion and plateau region of the flux pulse shape. Furthermore, since the flow direction of the pulse in the loop is controlled by the positive and negative inputs of the qubits coupled to the demultiplexer, generator 509 does not need to provide a pulse train to decrease the flux. In other words, generator 509 only needs to provide a pulse train of one polarity.

[0134] Figure 21 The diagram shows one structure of generator 509. This generator includes a first pulse counter nPC t1551, which outputs a pulse train and a carry signal, and can combine the above... Figure 8A The aforementioned type. After receiving the start-up signal, the first pulse counter begins outputting pulses provided to the demultiplexer. This forms a ramp signal transmitted to the demultiplexer, which allows the SFQ pulses to be added to the loop to increase the flux of the qubits within the quantum chip. The ramp signal can be provided to one or more qubits in the quantum chip, and the selection of which qubits(s) receive the ramp signal is set by the demultiplexer.

[0135] When the first counter 551 counts to its set number of pulses, it outputs a carry signal to the second counter t2 553. The second counter t2 553 is a combination of the above... Figure 8B The counter of this type. In addition, for qubits addressed to the negative input, a signal is sent to the demultiplexer to direct subsequent pulses to such qubits. Thus, for each addressed qubit, the signal between the positive and negative inputs can be changed from 10 to 01.

[0136] After a set number of clock cycles, a carry signal is output from the toggle flip-flop (TFF) 555. This TFF is used to restart the first counter and toggle itself with the carry signal. The counting time required for the second counter 553 is the aforementioned plateau duration. Subsequently, the carry signal from the first counter 551 sets the start of the first counter, causing it to begin generating SFQ pulses again. The difference is that the demultiplexer directs the pulse to the negative input this time to reduce the magnetic flux applied to the inductor coupled to the qubit. When the TFF 555 receives the input signal from the t2 counter 553 again, since the TFF has already toggled, it does not generate a start-up signal for nPC t1 551. Thus, only one trapezoidal waveform is generated.

[0137] Therefore, based on the above description, it is possible to understand how to... Figure 19 circuit with Figure 5 The trapezoidal magnetic flux of the type shown controls four qubits.

[0138] Figure 22 for Figure 19 A variant of the system. Among them, Figure 22 The circuitry is used to control the quantum chip with two trapezoids, rather than a single trapezoid.

[0139] Due to the structure of the 501 quantum bit chip combined with the above Figure 19 The chip is identical, so it will not be described again. Furthermore, the positive and negative inputs applied to the respective inductor loops 511a coupled to each qubit are also related to the above. Figure 19 The same applies. However, to achieve the generation and demultiplexing of the double trapezoidal pulses, the form of the demultiplexer used is combined with the above. Figure 19 The demultiplexers described are different.

[0140] Figure 23 The following is a list of available applications. Figure 22 One possible embodiment of the demultiplexer. This demultiplexer is similar in many respects to... Figure 20 The multiplexer shown differs in that its register is formed by pairs of dummy switches (DFFs) positioned between each pair of NDRO switches to hold the control data in the second trapezoidal shape. Due to the inherent characteristics of the shift register constituting the demultiplexer, the mode input to the demultiplexer is shifted along the register, thereby enabling channels for different qubits.

[0141] To form a double trapezoid, the demultiplexer needs to be programmed to produce a positive ramp, followed by a plateau, then a negative ramp, then a gap, then a second positive ramp, then a second plateau, and finally a second negative ramp. For this series of actions, the programming of the first two NDRO switches of the shift register does not require specific modification, but the programming of the subsequent NDRO switches in the register presents a greater challenge. To solve this problem, dummy flip-flops (DFFs) are placed between each pair of NDRO switches. Accordingly, to achieve the double trapezoidal programming, the following sequence can be applied to the DFF-DFF-NDRO-NDRO structure marked by the dashed box in the figure:

[0142] First trapezoid 1010 0101

[0144] Second trapezoid 0010 0001

[0146] Furthermore, the form of the generator varies depending on the type of double trapezoid. Figure 24 A further detailed view of the generator is shown. The structure of the first pulse counter nPC t1 601 is combined with the above. Figure 8AThe counter is similar and can output a pulse train. Upon receiving an oscillation signal, the counter starts an oscillation pulse ramp. When the first pulse counter 601 reaches its counting limit (first limit), it outputs a first carry signal to indicate that the demultiplexer switches to the above combination. Figure 19 The aforementioned negative ramp. Furthermore, the carry signal is passed to the first TFF 603, which is configured to first directly route the carry signal to the second counter t2 605. The second counter t2 605 is combined with the above. Figure 21 The second counter t2 553 is the same as described above. Furthermore, the structure of the second counter 605 is in conjunction with the above. Figure 8B The counters described above are similar. During the counting process of the second counter 605, a plateau is formed because the magnetic flux applied to the inductor loop remains constant. When the second counter 605 reaches its counting limit (second limit), it outputs a carry signal, which restarts the first counter 601, causing it to start outputting pulses. However, as mentioned above, since the demultiplexer has switched from positive to negative at this time, the output pulses generate a negative ramp, reducing the magnetic flux applied to the inductor loop.

[0147] When the first threshold is reached, the first pulse counter 601 outputs a carry signal again, and this carry signal is again routed to the first TFF 603. However, in this case, the first TFF 603 routes the carry signal to the third counter t4607. The structure of the third counter 607 is similar to that of the counter described above in conjunction with 8B, and it is also used to keep the loop flux constant. In this case, the interval between the first and second trapezoids is controlled by the third counter 607. When the third counter reaches the threshold (third limit), the third counter 607 outputs a carry signal, which switches the demultiplexer from the positive input to the negative input. In addition, this carry signal is further output through the second TFF 609 to restart the process of causing the first pulse counter 601 to oscillate and climb the pulse signal until it reaches the first limit. When the first limit is reached, the carry signal is output to the first TFF 603, and then routed to the second counter 605 and the demultiplexer to switch the demultiplexer to the negative input. When the second counter 605 reaches its second limit, it outputs a carry signal, which activates the first counter 601 to start counting again and outputs a pulse. This pulse forms a negative ramp, thereby completing the formation process of the second trapezoid.

[0148] While specific embodiments have been described above, these embodiments are merely illustrative and are not intended to limit the implementation and / or application scope of the technology disclosed herein. In fact, the new apparatus and methods described herein can be implemented in various other forms. Furthermore, based on the above disclosure or description, the apparatus, methods, and products described herein can also be simplified, replaced, and varied in form.

Claims

1. A controller for a superconducting qubit, characterized by, The controller comprises: an inductor for inductive coupling with a qubit; a pulse shaping circuit for applying a current pulse with a predetermined shape to the inductor, wherein the pulse shaping circuit comprises: a superconducting circuit for outputting single-flux quantum pulses; and a counting circuit for generating the shape of the current pulse by controlling the number of single-flux quantum pulses applied to the inductor in such a way that the current of the inductor is incremented or decremented by one single-flux quantum pulse at a time.

2. The controller of claim 1, wherein, The counting circuit is configured to generate the shape of the current pulse with positive single-flux quantum pulses having a positive polarity and negative single-flux quantum pulses having a negative polarity, wherein the counting circuit is configured to increment the current of the inductor by applying positive single-flux quantum pulses to the inductor, and the counter is configured to decrement the current of the inductor by applying negative single-flux quantum pulses to the inductor.

3. The controller of claim 2, wherein, The counting circuit is configured to generate a current pulse, wherein the shape of the current pulse comprises a rising edge in which positive single-flux quantum pulses are applied step by step, a plateau region in which the current applied to the inductor is fixed, and a falling edge in which the current applied to the inductor is decreased by applying negative single-flux quantum pulses step by step.

4. The controller of claim 3, wherein, The shape of the current pulse has a plurality of plateaus.

5. The controller of claim 2, wherein, The superconducting circuit comprises a Josephson junction and is configured to output single-flux quantum pulses by means of a 2π phase increment across the Josephson junction.

6. The controller of claim 5, wherein, The superconducting circuit is at least one of the following types: rapid single-flux quantum (RSFQ), ERSFQ, eSFQ, RQL, xSFQ, xeSFQ, DSFQ, bSFQ, PCL and variants thereof; and a quantum flux parameter (QFP) based circuit: AQFP, QFP, PQ and variants thereof.

7. The controller of claim 2, wherein, The counting circuit comprises a first counter for counting and limiting the number of positive single-flux quantum pulses, and a second counter for counting and limiting the number of negative single-flux quantum pulses.

8. The controller of claim 7, wherein, Further comprising a third counter, wherein the third counter is configured to control the length of time for which no pulse is output to the inductor.

9. The controller of claim 8, wherein, Each of the first counter, the second counter and the third counter comprises a register.

10. The controller of claim 9, wherein, Each register is configured to output a carry signal when a limit is reached, wherein the controller is configured such that the first counter, the second counter and the third counter are arranged in sequence, and the carry signals are arranged to be passed from a preceding counter to a following counter in sequence to activate the following counter in sequence.

11. The controller of claim 8, wherein, The controller is configured to generate a pulse shape with a repeating structure, wherein the controller further comprises a fourth counter for controlling the time between structures of the repeating pulse structure.

12. The controller of claim 1, wherein, The controller is configured to control a plurality of qubits by means of a demultiplexer.

13. The controller of claim 12, wherein, Further comprising a plurality of inductors, such that each inductor of the plurality of inductors is configured to be coupled with a respective qubit.

14. The controller of claim 13, wherein, Each inductor has a positive input and a negative input, wherein the positive input is configured to increase the magnetic flux of the inductor and the negative input is configured to decrease the magnetic flux of the inductor, and wherein the demultiplexer is connected to the positive input and the negative input of each inductor.

15. The controller of claim 14, wherein, The demultiplexer is configured to receive a stream of pulses and a selection signal, wherein the selection signal controls which of the positive input and the negative input of each inductor receives the stream of pulses.

16. The controller of claim 15, wherein, The pulse shaping circuit comprises a single pulse counter configured to output a pulse to the positive input or the negative input.

17. The controller of claim 15, wherein, The demultiplexer comprises a shift register, wherein the selection signal is provided sequentially along the shift register.

18. The controller of claim 17, wherein, The shift register comprises non-destructive read elements arranged sequentially, wherein the non-destructive read elements are coupled to respective positive inputs or respective negative inputs.

19. The controller of claim 18, wherein, Further comprising dummy elements provided between the non-destructive read elements, wherein the dummy elements enable the selection signal to be stored before being passed sequentially to the next non-destructive read element.

20. The controller of claim 9, wherein, The register comprises a plurality of superconducting T-type flip-flops.

21. The controller of claim 1, wherein, The pulse shape is configured to enable a quantum bit coupled to the controller inductively to transition to a quantum superposition state.

22. The controller of claim 3, wherein, At least one of the following parameters is used to control the pulse shape: a size of the platform; a size of the rising edge; a size of the falling edge; a delay between sequentially generated magnetic flux pulses; a delay before the first magnetic flux pulse is initiated.

23. A qubit device having a controller, the qubit device comprising: The controller is a controller as claimed in claim 1 inductively coupled to a quantum bit device.

24. The qubit device with controller of claim 23, wherein, The quantum bit device is a magnetic flux quantum bit device having an inductance.

25. The qubit device with controller of claim 24, wherein, The quantum bit device is a magnetic fluxonium type quantum bit device.

26. The qubit device with controller of claim 23, wherein, The quantum bit device and the controller are provided in a cryogenic measurement system having a temperature below 1 K.

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