Pulse shaping circuit

Abstract

A pulse shaping circuit (1) for shaping detector pulses in a spectrometer comprises a circuit input for receiving detector pulses from an analog ion detector, a flip-flop (10) for receiving detector pulses from the circuit input, a delay unit (20) for receiving an output pulse from the flip-flop and feeding a delayed output pulse to a reset input of the flip-flop, and a circuit output for providing the output pulse or the delayed output pulse to a counter. A minimum duration of a duration of the output pulse and a spacing between the output pulses is determined by the delay unit (20). The pulse shaping circuit (1) can comprise at least one Schmitt trigger (40).

Description

Technical Field

[0001] This invention relates to pulse shaping circuits. More specifically, it relates to pulse shaping circuits for mass spectrometers having detectors such as electron detectors and / or ion detectors. The invention further relates to detector pulse processing units including pulse shaping circuits, and spectrometers, such as mass spectrometers, including pulse shaping circuits. Background Technology

[0002] In mass spectrometry, various detectors are known to detect ions. Detected ions are typically filtered and / or separated according to their mass-to-charge (m / z) ratios. In a typical multipole mass spectrometer, multiple poles (usually but not necessarily quadrupoles) can scan a range of m / z values, acting as filters. For each m / z value (or a subrange of m / z values), the number of ions is determined. Therefore, the number of ions with different m / z values ​​is temporally separated and sequentially determined. Examples of multipole mass spectrometers are disclosed in U.S. Patent 9,934,954 (Thermo Fisher Scientific), which is hereby incorporated herein by reference.

[0003] Fan-field mass spectrometers can separate ions in space, for example, by applying a magnetic field that causes the ions to follow a curved trajectory, the radius of which depends on their m / z value. Therefore, the number of ions with different m / z values ​​can be determined simultaneously. An example of a fan-field mass spectrometer including an ion multi-collector electrode is disclosed in U.S. Patent 10,867,780 (Thermo Fisher Scientific and the University of Bristol), which is hereby incorporated herein by reference.

[0004] Such mass spectrometers typically include: an ion source for generating an ion beam from a sample; a mass filter downstream of the ion source for selecting ions from the beam by their mass-to-charge ratio (m / z); a collision cell downstream of the mass filter for removing interfering ions; another mass filter downstream of the collision cell; and a detector unit downstream of the mass filter. The detector unit may include multiple ion detectors for detecting multiple different ionic substances in parallel and / or simultaneously.

[0005] Several types of ion detectors are known, such as Faraday cups, compact discrete dynodes (CDD), and secondary electron multipliers (SEM). In some mass spectrometers, multiple Faraday cups are used in combination with one or two other types of ion detectors, for Faraday cups for ions with high numbers of occurrences and other types of ion detectors for ions with low numbers of occurrences.

[0006] Ions impacting a Faraday cup may cause a small current to flow through a resistor that is typically high in resistance. The resulting voltage across the resistor is usually converted into a frequency, representing the voltage and therefore the number of ions, using a voltage-to-frequency converter (VFC). Thus, each Faraday cup generates an output signal consisting of pulses through its associated VFC, with the number of pulses per second representing the number of ions impacting a particular Faraday cup.

[0007] Other types of ion detectors may also generate pulses that need to be counted to determine the number of ions impacting the detector within a specific time period. For example, compact discrete dynodes (CDDs) and secondary electron multipliers (SEMs) generate pulses that represent ion avalanches, and the number or frequency of these pulses indicates the number of ions.

[0008] In order to count the number of pulses generated by, for example, a secondary ion multiplier, it is necessary to be able to clearly distinguish subsequent pulses and avoid counting artifacts, such as so-called reflected pulses. Therefore, in order to reliably count detector pulses, the actual pulses should have minimal height and duration, while artifacts should be suppressed. Summary of the Invention

[0009] The present invention aims to provide an electronic circuit capable of receiving detector pulses from an analog detector and providing shaped pulses to a counter. The electronic circuit is reliable, simple, economical and effective.

[0010] Therefore, the present invention provides a pulse shaping circuit for shaping detector pulses in a spectrometer, the pulse shaping circuit comprising:

[0011] - Circuit input terminal, used to receive detector pulses from the analog ion detector.

[0012] A trigger, which receives detector pulses from the circuit input and generates an output pulse.

[0013] A delay unit, configured to receive an output pulse from the trigger and feed a delayed output pulse to the reset input of the trigger, the delay unit being configured to determine the duration of the output pulse and a minimum duration of the interval between the output pulses.

[0014] - A circuit output terminal, which is used to provide the output pulse or the delayed output pulse to the counter.

[0015] By using a flip-flop and a delay unit, it is possible to provide an economical and reliable pulse shaping circuit with a small number of components. The flip-flop receives a detector pulse and outputs a pulse that can be fed to a counter. The inventive feature of the pulse shaping circuit is the delay unit, which is configured to delay the output pulse of the flip-flop and feed the output pulse to the reset input of the flip-flop. Therefore, each output pulse generated by the flip-flop resets the flip-flop after a certain time delay, the amount of which is determined by the delay unit. It should be understood that resetting the flip-flop ends its output pulse; that is, resetting the flip-flop changes its output level from logic high to logic low. Therefore, the duration of the flip-flop's output pulse is determined by the delay unit.

[0016] Resetting a flip-flop and thus changing its output level from high (logic 1) to low (logic 0) will cause the input level at the reset input to reach a low level after a certain time delay, the amount of which is determined by the delay unit. Typically, the time delay between the flip-flop's output level going high and the reset input level going high is approximately the same as the time delay between the flip-flop's output level going low and the reset input level going low, although this may not be the case in all embodiments.

[0017] The output pulse of the trigger is shaped by resetting the trigger and subsequently delaying its setting. That is, the output pulse has both a duration and a minimum interval between them, both of which are determined by the delay unit and therefore the output pulse is shaped by the pulse shaping circuit of the present invention.

[0018] The above discussion is provided under the assumption of positive logic; when negative logic is used, those skilled in the art will be able to easily make any necessary adjustments.

[0019] In the pulse shaping circuit of this invention, the output of the delay unit can be coupled to the reset input of the flip-flop via a component having two defined output states. By using a component with two defined output states, a stable voltage can be received at the reset input, ensuring that the flip-flop reset does not terminate at an undesirable time.

[0020] Components with two defined output states, such as digital components, may include comparators, i.e., components that compare two voltages (or currents) and output a digital signal indicating which one is larger. Preferably, components with two defined output states include Schmitt triggers.

[0021] The input of a pulse shaping circuit can be coupled to a flip-flop via a component that has two defined output states. That is, a component with two defined output states, such as a digital component, can be positioned between the input of the pulse shaping circuit and the flip-flop, thereby indirectly connecting the flip-flop to the input of the pulse shaping circuit. The advantage of this is that the input of the flip-flop can receive a more precisely defined input voltage.

[0022] The output of the flip-flop can be coupled to the circuit output via a component that has two defined output states. While this also helps to better shape the pulses output by the pulse shaping circuit, the primary purpose of this additional component is to act as a buffer between the flip-flop and any component other than the circuit output.

[0023] In this embodiment, the output of the delay unit can be coupled to the circuit output via a component having two defined output states. Specifically, when a capacitor is used in the delay unit, the output voltage of the delay unit may not exhibit a pulse with flat edges. In this case, a component with two defined output states—such as a digital component—can produce a better-defined pulse edge.

[0024] For example, a component having two defined output states may include digital components, such as a series arrangement of OR gates or NOT gates. In an embodiment, a component having two defined output states may include a comparator. Although conventional comparators can be used, Schmitt triggers are preferred because such components effectively reduce noise by suppressing small signal fluctuations.

[0025] In embodiments of the pulse shaping circuit, the delay unit includes a resistor and a capacitor. By using a resistor and a capacitor, a very simple, economical, and effective delay unit can be implemented. Preferably, the delay unit includes a series arrangement of a resistor and a capacitor. In some embodiments, the delay unit consists only of a series arrangement of a resistor and a capacitor, with one end of the capacitor preferably connected to ground.

[0026] In the pulse shaping circuit of the present invention, the flip-flop may include a D flip-flop, in which case the reset input of the flip-flop is a clear input. As is well known, a D flip-flop typically has an input labeled D, an output labeled Q, a reset input labeled clear or R (reset), and a clock input.

[0027] In this embodiment, the flip-flop is a D flip-flop, with its D input connected to a logic "1" level. D flip-flops are widely available and offer superior characteristics. When the flip-flop is constructed from D flip-flops, its clock input can be connected to the input of a pulse shaping circuit.

[0028] Other types of flip-flops can be used instead. In this embodiment, the flip-flop for the pulse shaping circuit is an SR flip-flop, and the reset input of the flip-flop is the R input. As is well known, an SR flip-flop has a set (S) input and a reset (R) input.

[0029] In embodiments where the trigger is an SR trigger, the pulse shaping circuit may further include an AND gate disposed between the circuit input and the trigger, the AND gate being configured to receive the inverted, delayed output pulse of the trigger. The pulse shaping circuit including the AND gate may further include an inverter disposed between the delay unit and the AND gate. This allows detector pulses to be selectively fed to the SR trigger; that is, if the voltage at the R input is low, the (positive or high) input pulse can be provided only to the S input of the trigger, thereby avoiding any undefined state of the trigger.

[0030] The present invention further provides a detector pulse processing unit, which includes the pulse shaping circuit as described above. In an embodiment, the detector pulse processing unit may include:

[0031] - Optional amplifier, used to amplify the analog detector pulse,

[0032] - As described above, the pulse shaping circuit is used to shape detector pulses that may or may not be amplified, and

[0033] - A counter used to count the shaped detector pulses.

[0034] The present invention also provides a spectrometer, such as a mass spectrometer, which includes a detector pulse processing unit as described above. The spectrometer may be an inductively coupled plasma (ICP) mass spectrometer. The spectrometer including the detector pulse processing unit as described above may further include at least one of an ion source, a beam focusing unit, a sector magnetic field unit, a multipole unit, a detector unit, and a detector signal processing unit, wherein the detector pulse processing unit may be part of the detector signal processing unit. Attached Figure Description

[0035] Figure 1 An exemplary embodiment of a mass spectrometer in which the present invention can be applied is illustrated schematically.

[0036] Figure 2 A more detailed schematic illustration is shown. Figure 1 The signal processing unit of the mass spectrometer.

[0037] Figure 3 A first embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0038] Figure 4A second embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0039] Figure 5 A third embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0040] Figure 6 A fourth embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0041] Figure 7 A fifth embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0042] Figure 8 A sixth embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0043] Figure 9 A seventh embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0044] Figure 10 An eighth embodiment of the pulse shaping circuit according to the present invention is illustrated schematically.

[0045] Figure 11 The pulses that may appear in an embodiment of the pulse shaping circuit according to the invention are schematically shown.

[0046] Figure 12 The pulses that may appear in an embodiment of the pulse shaping circuit according to the invention are also schematically shown. Detailed Implementation

[0047] This invention provides a pulse shaping circuit designed to suppress parasitic pulses generated by a detector—such as an electron detector or an ion detector. The pulse shaping circuit of this invention is further designed to generate pulses with a minimum pulse length to facilitate pulse counting. The pulse shaping circuit is described in reference to a spectrometer—such as a mass spectrometer, an electron spectrometer, or a spectrometer.

[0048] The mass spectrometer to which the present invention can be applied is illustrated by way of example. Figure 1The mass spectrometer 100 is shown as including an ion source 110, a beam focusing unit 120, a mass filter unit 130, a detector unit 140, and a signal processing unit 150. The ion source 110 may be a plasma source, such as an inductively coupled plasma (ICP) source. The ion source 110 is arranged to generate a raw ion beam A, which is focused by the beam focusing unit 120 into a focused ion beam B. The beam focusing unit 120 may include suitable ion optics that may be known per se. A collision / reaction cell may be selectively arranged between the beam focusing unit 120 and the mass filter unit 130, and / or between the mass filter unit 130 and the detector unit 140.

[0049] In the mass filter unit 130, ions contained in the ion beam B can be separated according to their respective masses. If the mass filter unit 130 includes a sector magnetic field unit, the single focused ion beam B entering the mass filter unit 130 is split into multiple ion beams C that can reach different detectors in the detector unit 140, thereby allowing the individual detection of ions with different masses. If the mass filter unit 130 includes a multi-pole unit, such as a quadrupole or hexapole unit, then within a certain time period, only ions with a selected range of mass / charge (m / z) values ​​will leave the mass filter unit 130 as beam C and reach the detector unit 140. In response to the detection of ions, the detector unit 140 generates an ion detection signal that can be amplified and further processed in the signal processing unit 150, thereby generating a data signal that can contain the average detection frequency per ion detector and therefore the range per ion mass.

[0050] Figure 1 A portion of the mass spectrometer 100 is shown in more detail. Figure 2 In China. Specifically, Figure 2 A portion of the detector unit 140 and a portion of the signal processing unit 150 are schematically shown.

[0051] Detector unit 140 is shown as including secondary electron multipliers (SEMs) 141, 142, and 143. Detector unit 140 may include more than three (or fewer than three) secondary electron multipliers (SEMs) and additional ion detectors, such as Faraday cups and / or compact discrete dynodes (CDDs).

[0052] As is well known, secondary electron multipliers (SEMs) and similar ion detector arrangements generate pulses with small voltages proportional to the number of impact ions. These small voltages, typically ranging from 1 mV to 10 mV, are converted into voltages ranging from 1 V to 10 V. For this purpose, signal processing unit 150 includes analog amplifier 152. It should be noted that amplifier 152 is only schematically illustrated herein, and amplifier 152 may include operational amplifiers with negative feedback loops and other components. It should also be noted that for the sake of simplicity, only a single amplifier 152 is shown herein, but it should be understood that each detector 141-143 of detector unit 140 may be connected to a separate amplifier 152. In some embodiments, two or more detectors may share an input resistor and an amplifier.

[0053] Amplifier 152 generates an output voltage V out The pulse, the output voltage can be significantly greater than the input voltage V. in For example, 10, 100, or 1000 times larger. This output voltage V... out The received pulses are then fed to a pulse processing unit 153, which processes the received pulses to generate pulses P with appropriate shape and duration for counting by a counter 154.

[0054] To determine the average frequency, the pulse processing circuit can count the number of pulses within a certain time period, determine the duration of the time period, and divide the number of pulses by the duration.

[0055] As described above, the pulse processing unit 153 includes circuitry for shaping pulses, particularly for eliminating spurious peaks between pulses, and for providing a minimum pulse duration to allow for reliable pulse counting.

[0056] An exemplary embodiment of the pulse shaping circuit according to the present invention is schematically shown in Figure 3 In the middle. It can be... Figure 2 A portion of the pulse processing unit 153, including a pulse shaping circuit 1, is shown comprising a trigger 10 and a delay unit 20. The pulse shaping circuit 1 is further shown including a pulse shaping circuit input In and a pulse shaping circuit output Out. The delay unit 20 is shown including a delay unit input 21 and a delay unit output 22.

[0057] In the illustrated example, delay unit 20 includes a series arrangement of resistor 25 and capacitor 26. A first end of resistor 25 is connected to the delay unit input 21, while a second end of resistor 25 is connected to the first end of capacitor 26 and the delay unit output 22. In the illustrated example, the second end of capacitor 26 is connected to ground. This embodiment of delay unit 20 is simple, economical, and effective. It should be understood that other embodiments of the delay unit can be used, such as other arrangements of one or more resistors and one or more capacitors, and / or arrangements including more digital elements such as delay lines, gates, and / or flip-flops.

[0058] exist Figure 3 In this embodiment, flip-flop 10 is a D flip-flop with a D input and a Q output (a D flip-flop can also have an inverted Q output, but this is not used in this embodiment). The D input of flip-flop 10 is connected to a voltage representing a logic "1" level, typically a relatively high voltage level, such as a positive power supply voltage. Therefore, a logic "1" is always present at the D input and is replicated at each pulse of the clock input to the Q output (in... Figure 3 (Represented by a triangle in Chinese).

[0059] The clock input of flip-flop 10 is connected to the circuit input In. Therefore, the state of the flip-flop can change at each received detector pulse. (See above reference.) Figure 2 As explained, this detector pulse can be generated by, for example, a detector of SEM detector 141 in response to the detection of ions, and can be amplified by, for example, an amplifier of amplifier 152. Therefore, each detector pulse causes a logic "1" to appear at the Q output. Since the Q output of flip-flop 10 is connected to the circuit output Out, this circuit output Out is at a (relatively) high voltage representing a logic "1".

[0060] The Q output of flip-flop 10 is also connected to the input 21 of the delay unit, while the output 22 of the delay unit is connected to the clear input CLR (note that some D flip-flops may alternatively or additionally have an inverting clear input; if this clear input is used, an inverter may be arranged between the output 22 of the delay unit and the clear input). The delay unit 20 may be arranged such that a high voltage appearing at the input 21 of the delay unit will appear at its output 22 after a predetermined delay. Alternatively or additionally, the delay unit 20 may be arranged such that a low voltage appearing at the input 21 of the delay unit will appear at its output 22 after a predetermined delay.

[0061] In the illustrated embodiment, a relatively high voltage (e.g., a positive supply voltage) applied to resistor 25 will charge capacitor 26. After a certain delay determined by the resistance of resistor 25 and the capacitance of capacitor 26, the output 22 of delay unit 20, and therefore the clear input CLR of the flip-flop, will also be at this high voltage. Therefore, the flip-flop will be cleared (i.e., reset), and the output Q of flip-flop 10 will present a low voltage (e.g., ground) representing logic "0". Then, the pulse shaping circuit output Out will also present a low voltage.

[0062] When the output terminal Q of flip-flop 10 presents a low voltage, Figure 3 In the illustrated embodiment, input 21 of delay unit 20 will also present a low voltage. Therefore, capacitor 26 will begin to discharge via resistor 25, thereby delaying the voltage at output 22 of the delay unit and thus causing the voltage at the clear input CLR of flip-flop 10 to begin to drop. Eventually, the voltage will drop sufficiently to make the clear input CLR present a logic "0", thus ending the flip-flop's clearing and allowing the flip-flop to resume copying the logic "1" at the D input to the Q output at the next pulse received at the clock input.

[0063] Therefore, it can be seen that the detector pulse fed to the clock input of the flip-flop will generate a high voltage at the output of the flip-flop and pulse shaping circuit 1, and thus generate a pulse. This pulse will have a duration determined by the delay unit 20, such that after a predetermined delay, the flip-flop will reset, thereby generating a low voltage and thus causing no pulse at the output of the flip-flop and pulse shaping circuit 1. This pulse is absent or the pulse interval has a duration also determined by the delay unit 20. It should be noted that during this pulse interval, no pulse may appear at the output of the pulse shaping circuit Out, because the flip-flop 10 is in a cleared state. Therefore, short parasitic pulses will be filtered by the pulse shaping circuit 1 and will not be transmitted. Instead, the transmitted pulse has a minimum duration determined by the delay unit 20, which allows the counter (e.g., Figure 2 The counter 154 in the middle reliably counts these pulses.

[0064] It should be noted that, Figure 3 In the illustrated embodiment, the duration of the pulse will be approximately equal to the duration of the pulse interval, but in other embodiments these durations may not necessarily be equal.

[0065] exist Figure 3 In this embodiment, the output terminal Out of the pulse shaping circuit is directly connected to the Q output terminal of the flip-flop 10. Figure 4 In this embodiment, the output terminal Out of the pulse shaping circuit is connected to the output terminal 22 of the delay unit. Therefore, the pulse that can be output in this embodiment will be delayed by the delay unit.

[0066] Another embodiment is shown in Figure 5 This embodiment is basically similar to... Figure 3 The embodiment also includes a trigger 10 and a delay unit 20. Additionally, Figure 5 The embodiment includes a first Schmitt trigger 30, a second Schmitt trigger 40, and a third Schmitt trigger 50. The first Schmitt trigger 30 is arranged between the input In and the clock input of the trigger 10, and is used to provide a well-defined pulse to the clock input. The second Schmitt trigger 40 is arranged between the output 22 of the delay unit 20 and the clear input CLR of the trigger 10, and is used to better define the timing at which the clear input receives a high (logic "1") voltage or a low (logic "0") voltage. The third Schmitt trigger 50 is arranged between the Q output of the trigger 10 and the output Out of the pulse shaping circuit, particularly between the input 21 of the delay unit and the output Out of the pulse shaping circuit, and primarily serves as a buffer between the pulse shaping circuit and any other circuitry, such as a counter circuit.

[0067] Although all three Schmitt triggers are optional, the presence of the second Schmitt trigger 40 is particularly advantageous because it better defines the pulse duration and the pulse interval duration. Therefore, embodiments with only the second Schmitt trigger 40 are generally superior to embodiments without Schmitt triggers, or superior to embodiments without the second Schmitt trigger 40 but with the first Schmitt trigger 30 or the third Schmitt trigger 50.

[0068] It should be noted that each Schmitt trigger is an instance of a component having two defined output states. This component preferably includes a comparator that compares the input voltage with a reference voltage and outputs one of two possible output voltages. The Schmitt trigger is a particularly advantageous instance of a comparator, specifically a comparator with a hysteresis effect, which prevents its output voltage from changing too rapidly with its input signal. However, in Figure 5 In some embodiments, either of the Schmitt triggers can be replaced by a series arrangement of two inverters or, for example, by another type of comparator.

[0069] Figure 6 The embodiments are similar to Figure 4 The embodiment is modified, but three Schmitt triggers 30, 40, and 50 are added. In the signal path between the delay unit 20 and the pulse shaping circuit output terminal Out, the second Schmitt trigger 40 and the third Schmitt trigger 50 are arranged in series. Here, the third Schmitt trigger 50 primarily serves as a buffer between the trigger 10 and the output terminal Out, and can be replaced by another component with two defined output states.

[0070] Figure 7 The embodiments are similar to Figure 6 The embodiment differs in that it uses inverting Schmitt triggers 30, 40, and 50. In this embodiment, the output of delay unit 20 should be connected to the inverting clear input NOT CLR of trigger 10 via a second Schmitt trigger 40.

[0071] In the above embodiments, a D flip-flop was used. However, the present invention is not limited to D flip-flops, and other flip-flops, such as SR flip-flops, can be used alternatively. Embodiments including SR flip-flops are schematically shown in... Figure 8-10 middle.

[0072] Figure 8 The embodiments are similar to Figure 3 The embodiment also includes a trigger 10 and a delay unit 20. Figure 8 In this embodiment, the D flip-flop has been replaced with an SR flip-flop having inputs S (set) and R (reset) and an output Q. For example... Figure 3 As shown, the flip-flop output Q is connected to the pulse shaping output Out and the delay unit input 21. However, the pulse shaping circuit input In is connected to the first flip-flop input S, while the delay unit output 22 is connected to the second flip-flop input R.

[0073] The detector pulse received at input S will set flip-flop 10, thereby generating a high voltage (logic "1") at output Q. The pulse shaping circuit 1 will therefore generate a pulse at its output Out. Figure 3 In this embodiment, the high voltage at input 21 of the delay unit will, after a certain delay, generate a high voltage at output 22 of the delay unit, which is coupled to the R (reset) input of the flip-flop. This will reset the flip-flop, so the output Q will present a low voltage. This will trigger another delay in the delay unit 20, after which the voltage at output 22 of the delay unit, and therefore the voltage at the R input, will again go low, thus ending the reset cycle. When the reset ends, the flip-flop is able to respond to the next pulse at its S input.

[0074] although Figure 8 This implementation can work in this way, but its drawback is that a situation may arise where both the S and R inputs carry a high voltage, thus providing a logic "1" to both the S and R inputs, i.e., S = R = "1". This can potentially cause the flip-flop to enter an undefined state. This situation can be avoided using additional components, such as... Figure 9 As shown. Figure 9 Implementation examples and Figure 8 The implementation is the same, except that an inverter 60 and an AND gate 70 are added.

[0075] AND gate 70 is positioned between the pulse shaping circuit input In and the S input of flip-flop 10. NOR gate 60 is coupled to the delay unit output 22 and therefore receives the reset signal when it is present (the delayed output pulse). NOR gate 60 inverts the reset signal and feeds the inverted reset signal to the AND gate. Therefore, if the R input receives a logic "1" (high voltage), inverter 60 provides a logic "0" to AND gate 70, effectively blocking the AND gate, so no logic "1" can be fed to the S input of the flip-flop. This eliminates the case where S = R = "1".

[0076] Figure 10 The embodiments are similar to Figure 9 The embodiment differs in that three Schmitt triggers 30, 40, and 50 are added. For example, these Schmitt triggers have the same... Figure 5 Its counterpart in [the text] has essentially the same function. It should be understood that [it can be derived from...] Figure 10 In the embodiment, any one of the three Schmitt triggers 30, 40 and 50 is omitted.

[0077] exist Figure 11 The diagram schematically illustrates various signals that may appear in embodiments of the pulse shaping circuit of the present invention. Figure 11 The signal shown is:

[0078] A. The signal at the input terminal of the pulse shaping circuit;

[0079] B. The signal at the (inverting) clear input of the flip-flop;

[0080] C. The signal at the output of the delay unit; and

[0081] D. The signal at the output terminal of the pulse shaping circuit.

[0082] Figure 11 The signal shown is especially likely to appear Figure 7 The illustrated embodiment.

[0083] It can be received by a pulse shaping circuit and can be amplified ( Figure 2 The detector pulse output in 152) is shown at point A. In the specific example shown, the received detector pulse P in A negative voltage relative to a fixed voltage: In the absence of a pulse, a positive voltage V exists at the input of the pulse shaping circuit, while in the presence of a detector pulse P... in In this case, a zero (or near-zero) voltage 0 exists at the input of the pulse shaping circuit. In the example shown, the flip-flop is a positive-edge triggered flip-flop and the pulse shaping circuit has an inverting element at its input, for example... Figure 7The inverting Schmitt trigger 30 in the embodiment.

[0084] When the first (inverting) detector pulse P arrives at the clock input of the trigger at time t1, the output Q presents a value "1" represented by a high voltage, and this output Q is provided to the delay unit. Figure 7 In the embodiment shown, this makes the capacitor ( Figure 6 26) in the middle is charged and the output of the delay unit is ( Figure 7 The voltage at point 22) increases, such as Figure 11 As shown in C. This output signal of the delay unit is provided to the clear input of the flip-flop, optionally via a Schmitt trigger ( Figure 7 (40) If this Schmitt trigger is an inverting Schmitt trigger, such as Figure 7 As shown, the inverted clear input (NOT CLR) of the flip-flop can be used. If this Schmitt trigger is a non-inverting Schmitt trigger, the normal (non-inverting) clear input (CLR) of the flip-flop can be used.

[0085] At time t2, the output of the delay unit ( Figure 7 The signal at point 22) reaches a value that resets the flip-flop. In other words, the rising voltage at the output of the delay unit, as shown in C, causes the inverting Schmitt trigger coupled to the output of the delay unit (…) to… Figure 7 The output signal of (40) switches from high voltage to low voltage, as shown in B. This low voltage at the output of the delay unit is provided to the inverting clear input of the flip-flop ( Figure 7 The NOT CLR signal in the flip-flop clears the flip-flop and causes its output signal (at its output terminal Q) to present a low voltage. Figure 11 As can be seen, this clearing (i.e., reset) of the trigger occurs after the delay Δ = (t2 - t1) determined by the delay unit.

[0086] While the specific delay used will vary depending on the application and the detector used, typical delays can range from 1 nanosecond to 1 millisecond, preferably from 1 nanosecond to 1 microsecond, more preferably from 1 nanosecond to 100 nanoseconds, and even more preferably from 10 nanoseconds to 50 nanoseconds. Those skilled in the art will recognize that when using delay units arranged in series including resistors and capacitors, the time constant τ can be approximately equal to the delay Δ, where τ = RC, where R is the resistance of the resistor and C is the capacitance of the capacitor.

[0087] It should be noted that, Figure 11 In examples, such as in Figure 12In this example, for clarity of illustration, any delay caused by the trigger or any Schmitt trigger is ignored. In reality, each of these elements introduces a delay of several nanoseconds (ns). Therefore, the total delay Δ will be greater than the delay caused by the delay unit, represented by the time constant τ. In practical embodiments, the total delay Δ can reach, for example, approximately 30 nanoseconds.

[0088] Due to the reset, the low voltage at the output terminal Q of the flip-flop is fed to the delay unit, which causes the output signal of the delay unit to decrease, as shown in C. At time t3, the output signal of the delay unit has reached a low voltage sufficient to cause the Schmitt trigger 40 to change its output voltage, thereby providing a high voltage to the inverting reset input of the flip-flop, as shown in B.

[0089] exist Figure 7 In this embodiment, the output signal of the pulse shaping circuit is essentially the inverted version of the signal provided to the inverted clear input of the flip-flop (due to...). Figure 7 The inverting Schmitt trigger (version 50) in the middle. The output signal of the pulse shaping circuit is as follows: Figure 11 As shown in D, the pulse shaping circuit provides a well-defined output pulse P. out It has a duration defined by the delay unit.

[0090] When the next detector pulse P is received in At time t4, the event described above is repeated. According to an important aspect of the invention, the pulse shaping circuit, in each detector pulse P... in After the start, a blanking interval BT is provided. Therefore, the first blanking interval starts at time t1 and ends at time t3, while the second blanking interval starts at time t4 and ends at time t6. That is, starting from time t1 or t4, when the detector pulse P... in When the output Q of the flip-flop is presented with a high voltage, the pulse shaping circuit is insensitive to additional pulses, such as the reflected pulse R. During the first part of the blanking time BT, for example from t4 to t5, the output Q already has a high voltage corresponding to logic "1", so additional pulses at the clock input of the flip-flop will not change this state. During the second part of the blanking time BT, for example from t5 to t6, the flip-flop is in a "cleared" state due to the (inverted) clear signal shown at B, so the state of the flip-flop cannot be changed.

[0091] Therefore, it can be seen that the pulse shaping circuit of the present invention provides a well-defined output signal that is insensitive to parasitic signals such as reflected and noise signals.

[0092] Figure 12 This illustrates what might be shown in embodiments of the invention, for example in Figure 7Another example of a signal appearing in the illustrated embodiment. In Figure 12 In the example, two reflections R occur during the first blanking time interval BT extending between time t1 and time t3, while one reflection R occurs during the second blanking time interval BT extending between time t4 and time t6. For example... Figure 11 As shown, the second blanking period begins with the detector pulse P received at time t4. in Confirmed. Note that t4 can exist after time t3, that is, at any time after the first blanking time BT has ended.

[0093] Those skilled in the art will be able to readily add or remove components from the above embodiments. For example, other types of flip-flops or latches, such as JK flip-flops, can be used instead of the D flip-flops and SR flip-flops shown. Additionally, delay cells or delay circuits can be arranged in different ways using one or more digital elements (e.g., so-called delay lines) or series arrangements of gates (e.g., an even number of series NOT gates).

[0094] As described above, embodiments having zero, one, two, three or more Schmitt triggers or equivalent components are possible.

[0095] Therefore, those skilled in the art will understand that the present invention is not limited to the embodiments described above, and many additions and modifications can be made without departing from the scope of the invention as described in the appended claims.

Claims

1. A pulse shaping circuit for shaping detector pulses in a spectrometer, the pulse shaping circuit comprising: - a circuit input for receiving detector pulses from an analog ion detector, - a flip-flop for receiving detector pulses from the circuit input and generating output pulses, - a delay unit for receiving the output pulses from the flip-flop and feeding delayed output pulses to a reset input of the flip-flop, the delay unit being configured for determining a minimum duration of a duration of the output pulses and an interval between the output pulses, and - a circuit output for providing the output pulses or the delayed output pulses to a counter.

2. The pulse shaping circuit according to claim 1, wherein an output of the delay unit is coupled to the reset input of the flip-flop via a component having two defined output states.

3. The pulse shaping circuit according to claim 2, wherein the component comprises a comparator.

4. The pulse shaping circuit according to claim 3, wherein the component comprises a Schmitt trigger.

5. The pulse shaping circuit according to claim 1 or 2, wherein the circuit input is coupled to the flip-flop via a component having two defined output states.

6. The pulse shaping circuit according to claim 1 or 2, wherein an output of the flip-flop is coupled to the circuit output via a component having two defined output states.

7. The pulse shaping circuit according to the preceding claim 1 or 2, wherein an output of the delay unit is coupled to the circuit output via a component having two defined output states.

8. The pulse shaping circuit according to claim 5, wherein the component having two defined output states comprises a comparator.

9. The pulse shaping circuit according to claim 8, wherein the component having two defined output states comprises a Schmitt trigger.

10. The pulse shaping circuit according to the preceding claim 1 or 2, wherein the delay unit comprises a resistor and a capacitor.

11. The pulse shaping circuit according to the preceding claim 10, wherein the delay unit comprises a series arrangement of a resistor and a capacitor.

12. The pulse shaping circuit according to the preceding claim 1 or 2, wherein the flip-flop is a D flip-flop, and wherein the reset input of the flip-flop is a clear input.

13. The pulse shaping circuit according to claim 12, wherein a D input of the flip-flop is connected to a logic "1" level.

14. The pulse shaping circuit according to claim 12, wherein a clock input of the flip-flop is connected to the circuit input.

15. The pulse shaping circuit according to claim 1 or 2, wherein the flip-flop is an SR flip-flop, and wherein the reset input of the flip-flop is an R input.

16. The pulse shaping circuit according to claim 15, further comprising an AND gate arranged between the circuit input and the flip-flop, the AND gate being arranged to receive an inverted delayed output pulse of the flip-flop.

17. The pulse shaping circuit according to claim 16, further comprising an inverter arranged between the delay unit and the AND gate.

18. A detector pulse processing unit, comprising: - a pulse shaping circuit according to any one of claims 1-17 for shaping a detector pulse, and - a counter for counting the shaped detector pulse.

19. The detector pulse processing unit according to claim 18, further comprising an amplifier for amplifying an analog detector pulse before providing the analog detector pulse to the pulse shaping circuit.

20. A spectrometer comprising a detector pulse processing unit according to claim 18 or 19.

21. The spectrometer according to claim 20, further comprising an ion source and a detector unit.

22. The spectrometer according to claim 20, being a mass spectrometer.

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