Sampling rate conversion device and method and electronic equipment
By working in concert with the data input/output FIFO module and the clock control module, the sampling rate conversion module can be started and stopped on demand, which solves the problem of high power consumption of traditional modules, extends product life and ensures the reliability of data processing.
Patent Information
- Application Number
- CN202511926716.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-03-20
AI Technical Summary
Traditional sampling rate conversion modules suffer from high power consumption and shortened product lifespan due to their always-on clock design, and lack an on-demand start/stop mechanism.
The sampling rate conversion module is started and stopped on demand by working in concert with the data input FIFO module, the data output FIFO module, the sampling rate conversion module, and the clock control module. The sampling rate conversion module can be started and stopped on demand by buffering and storing data and providing status signal feedback through the input/output FIFO module, combined with the dynamic clock adjustment of the clock control module.
It reduces the module's ineffective power consumption, extends the product's lifespan, ensures the reliability of data processing and transmission, reduces ineffective working time, and achieves stable and efficient sampling rate conversion.
Smart Images
Figure CN121704760A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of signal processing technology, and in particular to a sampling rate conversion device, method and electronic device. Background Technology
[0002] In most digital signal processing systems, data subsampling technology is one of the core modules. The core function of the sample rate converter (SRC) is to convert the sampling rate of the input signal to the specifications required by the terminal device. Since the SRC module usually occupies a large area in the system hardware architecture, its power consumption is also relatively prominent.
[0003] In embedded systems, power consumption is a key indicator of product performance, making the reduction of SRC module power consumption of significant practical importance. Traditional SRC modules employ a constantly-on clock design without an automatic start-stop mechanism. On the one hand, the continuously running clock directly increases the overall system power consumption; on the other hand, prolonged uninterrupted operation shortens the product's lifespan. Therefore, optimizing the SRC module's clock control logic to achieve on-demand start-stop, thereby reducing unnecessary power consumption and extending product lifespan, has become a pressing technical problem to be solved. Summary of the Invention
[0004] In view of the above-mentioned technical problems, this disclosure provides a sampling rate conversion device, method and electronic device.
[0005] In a first aspect, this disclosure provides a sampling rate conversion device, including: a data input FIFO module, a data output FIFO module, a sampling rate conversion module, and a clock control module; The data input FIFO module is used to store the data to be processed and outputs the input status signal to the sampling rate conversion module and the clock control module; The sampling rate conversion module is used to convert the sampling rate of the stored data to be processed and output the operation status signal to the clock control module; The data output FIFO module is used to store the converted data after the sampling rate conversion is completed, and outputs the output status signal to the sampling rate conversion module and the clock control module; The clock control module is used to determine whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal.
[0006] Furthermore, according to the apparatus of the first aspect of this disclosure, a method for determining whether to output a clock signal to a sampling rate conversion module based on an input state signal, an operation state signal, and an output state signal includes: If the input status signal indicates that the data input FIFO module is empty, and the operation status signal indicates that the sampling rate conversion module has completed the sampling rate conversion operation, then stop outputting the clock signal to the sampling rate conversion module.
[0007] Furthermore, the apparatus according to the first aspect of this disclosure also includes: When the input status signal changes from indicating that the data input FIFO module is empty to indicating that the data input FIFO module is not empty, or when the operation status signal changes from indicating that the sampling rate conversion module is in the state of completion of sampling rate conversion operation to indicating that the sampling rate conversion module is in the state of incomplete sampling rate conversion operation, a clock signal is output to the sampling rate conversion module.
[0008] Furthermore, according to the apparatus of the first aspect of this disclosure, a method for determining whether to output a clock signal to a sampling rate conversion module based on an input state signal, an operation state signal, and an output state signal includes: If the output status signal indicates that the data output FIFO module is full or about to be full, stop outputting the clock signal to the sampling rate conversion module.
[0009] Furthermore, according to the apparatus of the first aspect of this disclosure, the sampling rate conversion module is also used for: In response to the received output status signal, the sampling rate conversion is stopped, and the intermediate data and control signals of the current operation remain unchanged.
[0010] Furthermore, according to the apparatus of the first aspect of this disclosure, a method for determining whether to output a clock signal to a sampling rate conversion module based on an input state signal, an operation state signal, and an output state signal includes: If the output status signal indicates that the data output FIFO module is empty, and any of the following conditions are met, a clock signal is output to the sampling rate conversion module: The operation status signal indicates that the sampling rate conversion module is in a state where the sampling rate conversion operation has not been completed; or, The input status signal indicates that the data input FIFO module is in a non-empty state.
[0011] Furthermore, the apparatus according to the first aspect of this disclosure also includes: When the state of the clock control module switches between stopping the output clock signal and outputting the clock signal, the SRC module maintains its operation state and intermediate operation data unchanged.
[0012] Furthermore, the apparatus according to the first aspect of this disclosure also includes: The application processor is used to send the data to be processed to the data input FIFO module, receive the interrupt signal and input status signal from the data input FIFO module, and the interrupt signal and output status signal from the data output FIFO module. The terminal device is used to receive and use the converted data from the output FIFO module.
[0013] Secondly, this disclosure provides a sampling rate conversion method, including: a data input FIFO module, a data output FIFO module, a sampling rate conversion module, and a clock control module; The data input FIFO module stores the data to be processed, and the output input status signal is sent to the sampling rate conversion module and the clock control module. The sampling rate conversion module is used to convert the sampling rate of the stored data to be processed, and the operation status signal is output to the clock control module. The data output FIFO module stores the converted data after the sampling rate conversion is completed, and outputs the status signal to the sampling rate conversion module and the clock control module; The clock control module uses the input status signal, operation status signal, and output status signal to determine whether to output a clock signal to the sampling rate conversion module.
[0014] Thirdly, this disclosure provides an electronic device, including: a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions, causing the electronic device to perform the method as described in the second aspect.
[0015] This disclosure provides a sampling rate conversion device, method, and electronic device. The sampling rate conversion device of this disclosure achieves on-demand start and stop of the sampling rate conversion module's clock through the division of labor and cooperation of a data input FIFO module, a data output FIFO module, a sampling rate conversion module, and a clock control module. With the help of the buffer storage and status signal feedback of the input / output FIFO module, the core conversion operation of the sampling rate conversion module, and the dynamic clock adjustment of the clock control module based on three types of status signals, it can fundamentally eliminate the invalid power consumption caused by traditional normally open clocks, meeting the low power consumption requirements of embedded systems. It also reduces the invalid working time of the core components of the module to delay component aging and extend product lifespan, achieving stable and efficient operation of sampling rate conversion. At the same time, it avoids data loss and read / write conflicts, ensuring the reliability of data processing and transmission.
[0016] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description
[0017] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.
[0018] Figure 1 This is a schematic diagram of a sampling rate conversion device provided in an embodiment of the present disclosure; Figure 2 A schematic flowchart illustrating a sampling rate conversion method provided in an embodiment of this disclosure; Figure 3 This is a hardware block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation To make the objectives, technical solutions, and advantages of this disclosure more apparent, exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments of this disclosure. It should be understood that this disclosure is not limited to the exemplary embodiments described herein.
[0019] Figure 1 This is a schematic diagram of a sampling rate conversion device provided in an embodiment of the present disclosure.
[0020] like Figure 1 As shown, the sampling rate conversion device includes an application processor 101, a bus controller 102, a sampling rate conversion SRC module 103, a data input FIFO module 104, a clock control module 105, a data output FIFO module 106, and a terminal device 107.
[0021] Furthermore, the data input FIFO module 104 is used to store the data to be processed and output the input status signal to the sampling rate conversion module and the clock control module.
[0022] Specifically, the data to be processed refers to the raw data stored in the data input FIFO (First Input First Output) module 104, which needs to undergo sampling rate conversion by the SRC module 103. This includes, but is not limited to, audio data and sensor data. The raw data (i.e., the aforementioned data to be processed) from external devices (such as microphones, sensors, video, and audio) is sent to the data input FIFO module for storage by the application processor 101 via the bus controller 102. The input status signal describes the current data storage status of the data input FIFO module, typically including, but not limited to, empty and non-empty states. The states are as follows: an empty state indicates that there is no data to be processed in the data input FIFO module 104 and the SRC module 103 has no data to read; a non-empty state indicates all states where there is data to be processed in the data input FIFO module 104, including an almost empty state, a full state, and an almost full state. An almost empty state indicates that there is still a small amount of data to be processed in the data input FIFO module 104, but the amount of data is lower than the "almost empty threshold" (the almost empty threshold can be set according to the maximum capacity of the input FIFO module 104, such as 10% of the maximum capacity, and the specific setting method can be determined according to actual needs); a full state means that the data input FIFO module 104 has stored the maximum capacity of data to be processed and can no longer receive new data; an almost full state means that the amount of data stored in the data input FIFO module 104 is close to the maximum capacity, and receiving a small amount of data will fill it up.
[0023] Furthermore, the sampling rate conversion module 103 is used to convert the sampling rate of the stored data to be processed and output the operation status signal to the clock control module.
[0024] Specifically, the sampling rate conversion module 103 acquires the data to be processed through the input FIFO module 104 and performs sampling rate conversion on the data. The "operation status signal" refers to the progress of the operation fed back by the SRC module 103 to the clock control module 105. For example, the operation status signal can be the src_cal_end signal. When the src_cal_end signal is set to 1, it indicates that the sampling rate conversion operation in the SRC module 103 has ended. Simultaneously, the SRC module 103 requests the data to be processed from the input FIFO module 104.
[0025] Furthermore, the data output FIFO module 106 is used to store the converted data after the sampling rate conversion is completed, and outputs the output status signal to the sampling rate conversion module and the clock control module; Specifically, the converted data refers to the data generated by the sampling rate conversion module 103 after converting the data to be processed by sampling rate conversion. The output status signal is used to describe the current data storage status of the data output FIFO module 106, which typically includes, but is not limited to, empty and non-empty states. An empty state indicates that there is no converted data in the data output FIFO module 106, and the terminal device 107 has no data to read. A nearly empty state indicates that there is still a small amount of converted data in the data output FIFO module 106, but the amount of data is below the "nearly empty threshold" (the nearly empty threshold can be set according to the maximum capacity of the data output FIFO module 106, such as 10% of the maximum capacity; the specific setting method can be determined according to actual needs). A non-empty state represents all situations where there is converted data to be output in the data output FIFO module 106, including nearly empty, full, and nearly full states. A full state means that the data output FIFO module 106 has stored the maximum capacity of converted data and cannot receive any more new data; a nearly full state means that the amount of data stored in the data output FIFO module 106 is close to the maximum capacity, and receiving a small amount of more data will fill it up. SRC module 103 sends the sampled rate converted data to data output FIFO module 106 for storage. Terminal device 107, through communication with data output FIFO module 106, can read the converted data for actual business applications on the terminal side (such as signal analysis, playback, further processing, etc.). Alternatively, application processor 101, through communication with data output FIFO module 106, can read the converted data and perform further processing, including but not limited to data format conversion and signal analysis based on business requirements.
[0026] Furthermore, the clock control module 105 is used to determine whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal.
[0027] Specifically, the clock control module 105 is used to provide a clock signal to the sampling rate conversion module 106. It determines the input data supply through the input status signal, the processing capability of the sampling rate conversion module through the operation status signal, and the storage status of the output data through the output status signal, and dynamically decides whether to output a clock signal to the sampling rate conversion module 103. In turn, it dynamically controls the working state of the SRC module.
[0028] In summary, according to the technical solution provided in the embodiments of this disclosure, the sampling rate conversion device of this disclosure, through the division of labor and cooperation of the data input FIFO module, the data output FIFO module, the sampling rate conversion module and the clock control module, and with the help of the buffer storage and status signal feedback of the input / output FIFO module, the core conversion operation of the sampling rate conversion module, and the dynamic clock adjustment of the clock control module based on three types of status signals, can realize the on-demand start and stop of the clock of the sampling rate conversion module. This not only eliminates the invalid power consumption caused by the traditional normally open clock from the root, meeting the low power consumption requirements of embedded systems, but also reduces the invalid working time of the core components of the module to delay component aging and extend the product lifespan, thus achieving stable and efficient operation of sampling rate conversion, while avoiding data loss and read / write conflicts, and ensuring the reliability of data processing and transmission.
[0029] Furthermore, the method for determining whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal includes: If the input status signal indicates that the data input FIFO module is empty, and the operation status signal indicates that the sampling rate conversion module has completed the sampling rate conversion operation, then stop outputting the clock signal to the sampling rate conversion module.
[0030] Specifically, when the current amount of stored data in the data input FIFO module is empty, it sends an input status signal to the clock control module 105, indicating that the data input FIFO module 104 is empty. Simultaneously, if all the data to be processed in the sampling rate conversion module 103 has completed sampling rate conversion (i.e., the sampling rate conversion operation is complete), the sampling rate conversion module 103 sends a src_cal_end signal to the clock control module 105. At this time, the signal is set to 1, indicating that the sampling rate conversion operation in the SRC module 103 is complete. Then, the clock empty control module 105 stops outputting clock signals to the sampling rate conversion module 103 based on the received input status signal and operation status signal.
[0031] In summary, according to the technical solution provided by the embodiments of this disclosure, by combining the empty state of the data input FIFO module with the operation completion state of the sampling rate conversion module, when there is insufficient input data and the module has completed all current conversion tasks, the clock signal output to the sampling rate conversion module is stopped in a timely manner. This can accurately cut off the invalid clock supply when the module has no data to process, reduce unnecessary power consumption from the hardware level, and avoid invalid operation of the module in the idle state. Thus, while ensuring the continuity of data processing, the system achieves low power consumption optimization and extends the working life of the core module.
[0032] Furthermore, it also includes: When the input status signal changes from indicating that the data input FIFO module is empty to indicating that the data input FIFO module is not empty, or when the operation status signal changes from indicating that the sampling rate conversion module is in the state of completion of sampling rate conversion operation to indicating that the sampling rate conversion module is in the state of incomplete sampling rate conversion operation, a clock signal is output to the sampling rate conversion module.
[0033] Specifically, when the input status signal indicates that the data input FIFO module 104 is empty, and the clock control module 105 has therefore stopped outputting clock signals to the SRC module 103, if the state of the input FIFO module 104 changes from empty to non-empty, the input status signal sent by the data input FIFO module 104 to the clock control module will change to indicate that the data input FIFO module 104 is in a non-empty state. Upon receiving the input status signal, the clock control module 105 will detect this state change and resume outputting clock signals to the SRC module. The purpose of this logic is to promptly drive the SRC module 103 to start working when new input data is written to the data input FIFO module 104, while simultaneously replenishing the converted data in the output FIFO. When the operation status signal indicates that SRC module 103 has completed all conversion operations (src_cal_end signal set to 1), and the clock control module has therefore stopped outputting the clock, if the state of SRC module 103 changes from "operation completed" to "operation not completed" (for example, SRC module 103 re-obtains the data to be processed from data input FIFO module 104 and starts a new conversion, at which point src_cal_end signal is set to 0), the clock control module will detect this change and re-output the clock signal. The purpose of this logic is to ensure a continuous clock supply when the SRC module has started a new conversion operation, ensuring that the operation process is not interrupted and avoiding data processing abnormalities or loss of intermediate results due to clock loss.
[0034] In summary, according to the technical solution provided by the embodiments of this disclosure, this disclosure dynamically restores the clock signal output to the SRC module by monitoring the transition of the data input FIFO module from empty to non-empty state and the transition of the SRC module from the end of operation to the beginning of operation. This not only drives the clock control module 105 to output a clock signal to the SRC module 103 in a timely manner when new data is written to the data input FIFO module 104, but also ensures a continuous clock supply to maintain processing continuity when the SRC module 103 starts a new operation. Ultimately, this achieves on-demand allocation of clock resources, which eliminates unnecessary power consumption and avoids data loss or operation interruption by accurately responding to state changes, thereby improving the reliability and energy efficiency of the system data processing.
[0035] Furthermore, the method for determining whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal includes: If the output status signal indicates that the data output FIFO module is full or about to be full, stop outputting the clock signal to the sampling rate conversion module.
[0036] Specifically, when the current stored data volume in the data output FIFO module is full or nearly full, it sends an output status signal to the clock control module 105. This signal indicates that the data output FIFO module is full or nearly full. For example, the signal `output_fifo_full` indicates a full state, and the signal `output_fifo_almost_full` indicates a nearly full state. Upon receiving this output status signal, the clock control module 105 stops outputting clock signals to the SRC module 103.
[0037] In summary, according to the technical solution provided by the embodiments of this disclosure, this disclosure controls whether the clock control module 105 outputs a clock signal to the SRC module 103 by outputting a status signal. When the output status signal indicates that the data output FIFO module is full or about to be full, the clock control module 105 outputs a clock signal to the SRC module 103. This can promptly pause the operation of the sampling rate conversion module, avoid its continuous output of converted data causing data overflow in the data output FIFO module, reduce the invalid power consumption of the module when the output channel is blocked, ensure the reliability of data storage and transmission, and achieve a balance between power consumption and data processing stability.
[0038] Furthermore, the sampling rate conversion module is also used for: In response to the received output status signal, the sampling rate conversion is stopped, and the intermediate data and control signals of the current operation remain unchanged.
[0039] Specifically, when the current stored data volume in the data output FIFO module is full or nearly full, it sends an output status signal to the SRC module 103. This signal indicates that the data output FIFO module is full or nearly full. For example, the signal output_fifo_full indicates a full state, and the signal output_fifo_almost_full indicates a nearly full state. When the SRC module 103 receives this output status signal, it immediately stops the sampling rate conversion, and during the stop period, it keeps the intermediate data and control signals of the current operation unchanged, without resetting or losing the processed state.
[0040] Furthermore, when the current amount of stored data in the data output FIFO module is lower than or close to full, the SRC module 103 will restore the current operation state and continue the operation in the current operation state (i.e., perform sampling rate conversion).
[0041] In summary, according to the technical solution provided in the embodiments of this disclosure, the sampling rate conversion module of this disclosure stops the conversion operation in a timely manner and maintains the current operation state by responding to the full state / near full state signal of the output FIFO. This can not only avoid the loss of data overflow after conversion due to insufficient capacity of the output FIFO module, but also directly resume the calculation from the pause point when the output channel is available again without re-initialization. Thus, while ensuring data integrity, it reduces the invalid power consumption and time overhead caused by repeated calculations, and improves the reliability and efficiency of system data processing.
[0042] Furthermore, the method for determining whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal includes: If the output status signal indicates that the data output FIFO module is empty, and any of the following conditions are met, a clock signal is output to the sampling rate conversion module: The operation status signal indicates that the sampling rate conversion module is in a state where the sampling rate conversion operation has not been completed; or, The input status signal indicates that the data input FIFO module is in a non-empty state.
[0043] Specifically, when the current amount of stored data in the data output FIFO module 106 is almost empty, it sends an output status signal to the clock control module 105. This signal indicates that the data output FIFO module is almost empty. For example, the `output_fifo_almost_empty` signal indicates an almost empty state. Based on the above premise, the clock control module 105 will output a clock signal to the SRC module 103 as long as any of the following conditions are met: 1. If there is unfinished data in the SRC module 103, the operation status signal sent to the clock control module 105 (such as setting the src_cal_end signal to 0) indicates that the SRC module 103 is in an unfinished sampling rate conversion operation state.
[0044] 2. If the current amount of stored data in the data input FIFO module is not empty, it will send an input status signal to the clock control module 105. This signal indicates that the data input FIFO module 104 is not empty.
[0045] In summary, according to the technical solution provided by the embodiments of this disclosure, this disclosure, by taking the empty state of the data output FIFO module as a premise, and combining any condition of the SRC module not finishing its operation or the non-empty state of the data input FIFO module, triggers the clock control module to output a clock signal to the SRC module. This ensures that the SRC module can continue to complete its current operation to replenish the output data when the output data is about to be exhausted, and also promptly starts the SRC module 103 to perform sampling rate conversion operation when there is data to be processed in the data input FIFO module 104 (i.e., non-empty state). This balances the continuity of output data with the efficiency of system operation, ultimately achieving the continuity of output data supply and the security of input data storage. At the same time, precise clock supply control reduces ineffective power consumption and improves the overall data processing efficiency and reliability of the system.
[0046] Furthermore, it also includes: When the state of the clock control module switches between stopping the output clock signal and outputting the clock signal, the SRC module maintains its operation state and intermediate operation data unchanged.
[0047] Specifically, when the clock control module 105 stops outputting the clock signal due to the data input FIFO module 104 being empty and the SRC module 103 having finished its operation, or the data output FIFO module being full / about to be full, or when the clock control module 105 resumes outputting the clock signal due to the data input FIFO module 104 changing from empty to non-empty, the SRC module 103 changing from finished to not finished, or the data output FIFO module 106 being about to be empty and meeting any of the start conditions, the SRC module will maintain its operation state, that is, it will continuously store intermediate operation data and keep control signals (such as operation configuration signals, status and timing control signals, etc.) unchanged. It will not lose existing operation progress and intermediate state data, nor will it tamper with configuration and timing logic, ensuring that the operation state is consistent before and after the clock signal switch. When the clock is restored later, it can seamlessly continue the calculation from the paused node without re-initialization.
[0048] In summary, according to the technical solution provided in the embodiments of this disclosure, this disclosure achieves seamless connection of the operation state by stabilizing and preserving the control signals such as intermediate operation data, operation configuration, and status timing of the SRC module 103 during clock switching. This avoids loss of operation progress and tampering with configuration logic caused by clock start and stop, ensures the continuity of sampling rate conversion and data reliability, and allows the calculation to resume from the paused node without re-initialization, reducing invalid power consumption and time overhead, and further improving the energy efficiency ratio and working stability of the device.
[0049] Furthermore, since the clock control module 105 can automatically switch the output and stop of the clock signal according to the actual operating status of the sampling rate conversion device (the amount of data in the input FIFO module, the storage status of the output FIFO module, and the operation progress of the SRC module), it drives the SRC module to automatically start and stop. During the switching process of starting and stopping, the SRC module always maintains its operation status, ultimately realizing the intelligent, low-power and high-reliability coordination of the device.
[0050] Furthermore, the SRC module 103 supports sampling rate conversion function bypass. When the sampling rate conversion function is bypassed, it is equivalent to the data sampling rate before input and after output remaining unchanged. At this time, all functions in the sampling rate conversion device still work normally, which makes the application scope of this disclosure wider and its use more flexible.
[0051] Furthermore, the sampling rate conversion device also includes: The application processor 101 is used to send the data to be processed to the data input FIFO module 104, receive the interrupt signal and input status signal of the data input FIFO module 104, and the interrupt signal and output status signal of the data output FIFO module 106.
[0052] Specifically, the core function of the application processor 101 is as the data transmission and status monitoring center of the sampling rate conversion device. Specifically, it sends the raw data to be processed (audio data, sensor data, etc.) collected by external devices (such as microphones, sensors) to the data input FIFO module 104 for subsequent sampling rate conversion. At the same time, it also receives interrupt signals (such as reminder signals triggered when the data is full or about to be empty) and input status signals (signals describing the data storage status within the module, including empty, about to be empty, full, and about to be full) from the data input FIFO module 104 in real time, as well as interrupt signals (such as reminder signals triggered when the data is full or about to be empty) and output status signals (signals describing the data storage status after conversion within the module, including empty, about to be empty, full, and about to be full) from the data output FIFO module. Through these signals, it comprehensively grasps the data storage status of the input and output FIFO modules, thereby realizing the overall scheduling and abnormal response of the entire data processing flow.
[0053] Furthermore, it is also used to further process the data output by the data output FIFO module, such as standardizing the format of the converted data (to adapt to the interface data format requirements of the terminal device), optimizing noise reduction filtering (to remove weak interference signals that may be introduced during the sampling rate conversion process), data compression / decompression (to reduce data transmission and storage overhead), multi-channel data synchronization (to achieve timing alignment of data in each channel if it is a multi-channel signal conversion), data verification and error correction (to verify data integrity and repair minor errors), or performing signal feature extraction (such as extracting frequency features from audio data and extracting changing trends from sensor data) and data fusion (combining with the output data of other modules to generate comprehensive results) in combination with specific business scenarios, so as to adapt to the actual application needs of the terminal device (such as playback, display, analysis and decision-making).
[0054] Terminal device 107 is used to receive and use the converted data in the output FIFO module.
[0055] Specifically, the terminal device is the "end user" of the sampling rate conversion device's processing results. Specifically, it directly reads the processed data (i.e., converted data) from the data output FIFO module and then uses this data according to its actual business scenario. For example, if it's an audio terminal (such as a speaker or headphones), it will use the converted audio data for playback; if it's a sensor data processing terminal (such as industrial monitoring equipment or smart wearable devices), it will use this data for signal analysis, status monitoring, or data display; if it's a communication terminal (such as a router or IoT device), it may use the data for signal transmission or further communication interaction. Essentially, it receives and utilizes the converted, valid data to realize the device's practical application value.
[0056] The bus controller 102 is a key communication hub that enables data transmission between the application processor 101 and the data input FIFO module 104 and the data output FIFO module 106.
[0057] Furthermore, based on actual business needs, the aforementioned clock control module 105 can also selectively provide clock signals to the SRC module 103 by receiving the enable signal and the normally open clock signal from the SRC module 103 (e.g., when the enable signal is set to 1 and the normally open clock signal is set to 1), without being affected by the dynamic adjustment of the input / output FIFO state and operation state signals mentioned above.
[0058] Figure 2 This is a schematic flowchart of a sampling rate conversion method provided in an embodiment of the present disclosure.
[0059] like Figure 2 As shown, this sampling rate conversion method is applicable to the aforementioned sampling rate conversion device. The sampling rate conversion method specifically includes the following steps: Step 201: Use the data input FIFO module to store the data to be processed, and output the input status signal to the sampling rate conversion module and the clock control module.
[0060] Step 202: Use the sampling rate conversion module to convert the sampling rate of the stored data to be processed, and output the operation status signal to the clock control module.
[0061] Step 203: Use the data output FIFO module to store the converted data after the sampling rate conversion is completed, and output the status signal to the sampling rate conversion module and the clock control module.
[0062] Step 204: Using the clock control module, determine whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal.
[0063] Specifically, the data input FIFO module 104 stores the raw data to be processed issued by the application processor 101, and synchronously outputs the input status signal reflecting its own data storage status (empty, almost empty, full, almost full, etc.) to the sampling rate conversion module 103 and the clock control module 105. Then, based on the clock signal provided by the clock control module 105, the sampling rate conversion module 103 performs a sampling rate conversion operation on the data to be processed stored in the data input FIFO module 104, and feeds back the operation status signal of its own operation progress (such as operation in progress, operation completed) to the clock control module 105. The data output FIFO module 106 stores the converted data after the sampling rate conversion is completed, and outputs the output status signal reflecting its own converted data storage status to the sampling rate conversion module 103 and the clock control module 105. The clock control module 105 comprehensively receives the input status signal from the data input FIFO module, the operation status signal from the sampling rate conversion module, and the data output FIFO. The module's output status signal determines whether to output a clock signal to the sampling rate conversion module according to preset logic (such as stopping clock supply when the input FIFO is empty / about to be empty and the SRC operation is finished, stopping clock supply when the output FIFO is full / about to be full, changing the input FIFO from empty to non-empty, and resuming clock supply when the SRC module changes from the end of operation to not yet finished, etc.), thereby realizing the dynamic start and stop of the clock and the efficient collaborative work of the SRC module.
[0064] In summary, according to the technical solution provided in the embodiments of this disclosure, this disclosure, through the division of labor and cooperation of the data input FIFO module, the data output FIFO module, the sampling rate conversion module, and the clock control module, and by leveraging the buffer storage and status signal feedback of the input / output FIFO module, the core conversion operation of the sampling rate conversion module, and the dynamic clock adjustment of the clock control module based on three types of status signals, can realize the on-demand start and stop of the clock of the sampling rate conversion module. This not only eliminates the invalid power consumption caused by the traditional normally open clock from the root, meeting the low power consumption requirements of embedded systems, but also reduces the invalid working time of the core components of the module to delay component aging and extend product lifespan, achieving stable and efficient operation of the sampling rate conversion, while avoiding data loss and read / write conflicts, and ensuring the reliability of data processing and transmission.
[0065] For the above, please refer to the appendix. Figure 1 To be continued Figure 2 This disclosure describes in detail a sampling rate conversion device and scheme provided by the present disclosure. Compared with the prior art, the present disclosure has the following technical advantages: 1. Traditional devices containing sampling rate conversion modules lack automatic stop or start functionality for the processing module, requiring the processor to control data transfer in the output FIFO. In this disclosure, the data in the output FIFO can be directly output to the data-consuming terminal device, or the processor can be used to remove the data from the output FIFO. Furthermore, during the process of the output FIFO changing from full to almost empty, the entire device, except for the data-consuming terminal device which is active, remains in an idle state, significantly reducing overall power consumption.
[0066] 2. Traditional devices containing sampling rate conversion modules are relatively complex to control, requiring processor participation and interaction in each process. In this disclosure, because a clock signal is output on demand, the processor only needs to move data to the input FIFO; the rest of the process does not require processor participation, allowing the processor to remain in a sleep state for extended periods.
[0067] Figure 3 This is a hardware block diagram of an electronic device provided according to an embodiment of the present disclosure. The electronic device 300 according to an embodiment of the present disclosure includes at least a processor; and a memory for storing computer-readable instructions. When the computer-readable instructions are loaded and executed by the processor, the processor performs the sampling rate conversion method described in the foregoing embodiments of the present disclosure.
[0068] Figure 3The illustrated electronic device 300 specifically includes a central processing unit (CPU) 301, a graphics processing unit (GPU) 302, and a memory 303. These units are interconnected via a bus 304. The CPU 301 and / or GPU 302 can function as the aforementioned processor, and the memory 303 can function as the aforementioned memory storing computer-readable instructions. Furthermore, the electronic device 300 may also include a communication unit 305, a storage unit 306, an output unit 307, an input unit 308, and an external device 309, all of which are also connected to the bus 304.
[0069] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.
[0070] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0071] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.
[0072] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.
[0073] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.
[0074] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.
[0075] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.
[0076] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.
Claims
1. A sampling rate conversion device, characterized in that, include: Data input FIFO module, data output FIFO module, sampling rate conversion (SRC) module, and clock control module; The data input FIFO module is used to store the data to be processed and output the input status signal to the sampling rate conversion module and the clock control module; The sampling rate conversion module is used to convert the sampling rate of the stored data to be processed and output the operation status signal to the clock control module; The data output FIFO module is used to store the converted data after the sampling rate conversion is completed, and outputs the output status signal to the sampling rate conversion module and the clock control module. The clock control module is used to determine whether to output a clock signal to the sampling rate conversion module based on the input status signal, the operation status signal, and the output status signal.
2. The sampling rate conversion device according to claim 1, characterized in that, The method for determining whether to output a clock signal to the sampling rate conversion module based on the input state signal, the operation state signal, and the output state signal includes: If the input status signal indicates that the data input FIFO module is empty, and the operation status signal indicates that the sampling rate conversion module is in the sampling rate conversion operation completion state, then stop outputting the clock signal to the sampling rate conversion module.
3. The sampling rate conversion device according to claim 2, characterized in that, Also includes: When the input status signal changes from indicating that the data input FIFO module is empty to indicating that the data input FIFO module is not empty, or when the operation status signal changes from indicating that the sampling rate conversion module is in the state of having completed the sampling rate conversion operation to indicating that the sampling rate conversion module is in the state of not having completed the sampling rate conversion operation, a clock signal is output to the sampling rate conversion module.
4. The sampling rate conversion device according to claim 1, characterized in that, The method for determining whether to output a clock signal to the sampling rate conversion module based on the input state signal, the operation state signal, and the output state signal includes: If the output status signal indicates that the data output FIFO module is full or about to be full, stop outputting the clock signal to the sampling rate conversion module.
5. The sampling rate conversion device according to claim 4, characterized in that, The sampling rate conversion module is also used for: In response to the received output status signal, the sampling rate conversion is stopped, and the intermediate data and control signals of the current operation remain unchanged.
6. The sampling rate conversion device according to claim 1, characterized in that, The method for determining whether to output a clock signal to the sampling rate conversion module based on the input state signal, the operation state signal, and the output state signal includes: If the output status signal indicates that the data output FIFO module is empty, and any of the following conditions are met, a clock signal is output to the sampling rate conversion module: The operation status signal indicates that the sampling rate conversion module is in a state where the sampling rate conversion operation has not been completed; or, The input status signal indicates that the data input FIFO module is in a non-empty state.
7. The sampling rate conversion device according to claim 1, characterized in that, Also includes: When the state of the clock control module switches between stopping the output clock signal and outputting the clock signal, the SRC module maintains the operation state and the intermediate state data of the operation unchanged.
8. The sampling rate conversion device according to claim 1, characterized in that, Also includes: An application processor is configured to send the data to be processed to the data input FIFO module, receive an interrupt signal and an input status signal from the data input FIFO module, and an interrupt signal and an output status signal from the data output FIFO module. A terminal device for receiving and using the converted data from the output FIFO module.
9. A sampling rate conversion method, characterized in that, include: Data input FIFO module, data output FIFO module, sampling rate conversion module, and clock control module; The data input FIFO module is used to store the data to be processed, and the input status signal is output to the sampling rate conversion module and the clock control module. The sampling rate conversion module is used to convert the sampling rate of the stored data to be processed, and the operation status signal is output to the clock control module. The data output FIFO module is used to store the converted data after the sampling rate conversion is completed, and the output status signal is output to the sampling rate conversion module and the clock control module. The clock control module uses the input status signal, the operation status signal, and the output status signal to determine whether to output a clock signal to the sampling rate conversion module.
10. An electronic device, characterized in that, include: Memory, used to store computer-readable instructions; as well as A processor for executing the computer-readable instructions, causing the electronic device to perform the sampling rate conversion method as described in claim 9.