Fractional sampling rate converter and phase locked loop

Abstract

A fractional sample rate converter and phase locked loop are provided, including a first-in-first-out (FIFO) buffer, write logic, read logic, and a fractional interpolator. The write logic is configured to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and configured to generate corresponding interpolated data samples as output of the fractional sample rate converter at a second rate. The read logic is configured to transfer the input data samples in the FIFO buffer to the fractional interpolator. A ratio of the second rate to the first rate is a fraction greater than one.

Description

[0001] CLAIM OF PRIORITY

[0002] This patent application claims priority to and incorporates by reference in its entirety the content of pending provisional Indian Patent Application No. 202141012418, filed on March 23, 2021, entitled “Method for Hardware Efficient Fractional Interpolator and Rate Converter Design for Multi Rate Signal Processing,” and claims priority to and incorporates by reference in its entirety U.S. Patent Application No. 17 / 543,762, filed on December 7, 2021. TECHNICAL FIELD

[0003] Embodiments of the present application relate generally to multi-rate signal processing, and more specifically, to a fractional sample rate converter for generating output samples at a higher rate from input samples. BACKGROUND

[0004] A sample rate converter provides output samples at a different rate (output rate) compared to the rate at which the input samples are generated (input rate). As is well known in the relevant art, sample rate converters are applied in digital signal processing environments such as audio codecs, image processing systems, phase-locked loops (PLLs), etc.

[0005] It is often required that the sample rate converter is able to provide samples at an output rate that is higher than the input rate. The output rate needs to be a (non-integer) fraction of the input rate, which in practice means that the output rate is a higher fractional multiple of the input rate compared to the input rate. SUMMARY

[0006] Aspects of the present application are directed to providing a fractional sample rate converter for generating output samples at a higher rate from input samples.

[0007] Some embodiments of the present application provide a fractional sample rate converter comprising: a first-in-first-out (FIFO) buffer; write logic to write input data samples into the FIFO buffer at a first rate; a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating corresponding interpolated data samples at a second rate Fhi as an output of the fractional sample rate converter; and read logic to transfer input data samples in the FIFO buffer to the fractional interpolator, wherein a ratio of the second rate to the first rate is a fraction greater than 1.

[0008] In some embodiments, the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and wherein the read logic is to transfer the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency averaging constituting the first rate.

[0009] In some embodiments, the fractional interpolator employs linear interpolation to generate the interpolated data samples from the input data samples.

[0010] In some embodiments, the write logic comprises: a register to receive each of a plurality of input data samples from a source at the first rate, the register to store the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at an output of the register within one cycle of the low frequency clock, the output of the register being coupled to an input data port of the FIFO buffer; a flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to toggle at each active edge of the low frequency clock; a clock domain crossing synchronizer having an input coupled to the output of the flip-flop, the clock domain crossing synchronizer receiving a high frequency clock Fxo having a frequency equal to Fhi*Lint, where Lint is an integer, and storing the output of the flip-flop at active edges of the high frequency clock Fxo, the stored output of the flip-flop being used as a synchronization signal at a second output of the clock domain crossing synchronizer; and an edge detector coupled to receive the synchronization signal, the edge detector to generate a pulse at a third output of the edge detector from the synchronization signal at a rate equal to the first rate,

[0011] wherein the third output is coupled to a write enable of the FIFO buffer to cause input data samples to be written to the FIFO buffer at the first rate synchronized with the high frequency clock.

[0012] In some embodiments, the edge detector comprises: a delay element coupled to the second output, the delay element to delay the synchronization signal by a duration equal to one clock period of the high frequency clock and to generate a delayed synchronization signal at a fourth output of the delay element; and an exclusive OR (XOR) gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

[0013] In some embodiments, the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

[0014] In some embodiments, the fractional interpolator is configured to compute a current interpolation sample according to the following equation:

[0015]

[0016] where Xhi[m] represents the current interpolation data sample, Xlo[k] and Xlo[k-1] represent input data samples used to compute the current interpolation sample, Llin represents the ratio of the second rate and the first rate, and 'r' is equal to the expression {m - (k - 1) * Llin}, where m and k are sample indices of the interpolation sample and input data sample; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter computing the value of 'r' to be used by the fractional interpolator to obtain each interpolation data sample including the current interpolation data sample, the real counter forwarding the value of 'r' to the fractional interpolator, the real counter further operating as the read logic; wherein the real counter is configured to: initialize r to zero when the fractional sample rate converter is reset; increment r by one at the second rate based on an active edge of an intermediate frequency clock having a rate equal to Fhi, where the intermediate frequency clock is derived from and synchronized with the high frequency clock Fxo; and if the incremented value of r is greater than or equal to Llin, set r equal to (r - Llin) and cause the next data sample in the FIFO buffer to be transferred to the fractional interpolator.

[0017] In some embodiments, the fractional interpolator is configured to compute a current interpolation sample according to the following equation:

[0018]

[0019] where Xhi[m] represents the current interpolated data sample, Xlo[k] and Xlo[k-1] represent input data samples used to compute the current interpolated sample, Llin represents a ratio of the second rate to the first rate, and 'r' is equal to the expression {m - (k - 1) * Llin}, where m and k are sample indices of the interpolated sample and the input data sample; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter computes a value of 'r / Llin', the real counter computes a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwards the 'r / Llin' value to the fractional interpolator, the real counter further operates as the read logic, wherein the real counter is to: initialize r / Llin to zero when the fractional sample rate converter is reset; increment r / Llin by 1 / Llin at the second rate; and if the increment value of r / Llin is greater than or equal to 1.0, set the increment value to equal (r / Llin - 1.0) and cause the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting indicates a rollover condition occurs.

[0020] In some embodiments, the fractional sample rate converter further comprises: a computation engine to compute the value 1 / Llin, the computation engine provides the value 1 / Llin to the real counter.

[0021] In some embodiments, the computation engine updates the value 1 / Llin from time to time to compensate for frequency drifts of the high frequency clock and the low frequency clock, wherein the real counter applies the updated 1 / Llin value when the rollover condition occurs.

[0022] In some embodiments, when an overflow condition occurs in the FIFO buffer, logic in the FIFO buffer is to replace a last sample in the FIFO buffer with an arithmetic average of a next input data sample and the last sample received from the write logic.

[0023] In some embodiments, when an underflow condition occurs, the fractional interpolator is to compute a next input data sample Xlo[k-2] to compute a next interpolated sample according to the equation: Xlo[k-2] = (2 * Xlo[k]) - Xlo[k-1], where Xlo[k] and Xlo[k-1] are the last two samples currently available in the fractional interpolator.

[0024] Part embodiments of the application also provide a phase-locked loop (PLL) comprising: a data selector (MUX) coupled to receive a first clock and a second clock, the MUX forwarding the first clock as a selected clock if a select signal has a first value, and forwarding the second clock as the selected clock if the select signal has a second value; a phase detector coupled to receive the selected clock and a feedback clock, the phase detector generating an error signal in the form of a stream of error data samples, the error signal representing a phase difference between the selected clock and the feedback clock; a digital filter for generating a stream of filtered error data samples by filtering the error data samples; an oscillator coupled to receive the filtered error data samples and to generate an output clock, wherein a frequency of the output clock is determined by a magnitude of the filtered error data samples; and a feedback divider generating each successive cycle of the feedback clock upon counting a predetermined number of cycles of the output clock, wherein the filtered error data samples have a higher rate than the error data samples, wherein the digital filter comprises a digital low-pass filter and a fractional sample rate converter, the fractional sample rate converter receiving the error data samples as input data samples, the fractional sample rate converter generating interpolated data samples from the input data samples by interpolation, and providing the interpolated data samples to the digital low-pass filter, the digital low-pass filter low-pass filtering the interpolated data samples and providing filtered interpolated data samples as the filtered error data samples; wherein the fractional sample rate converter comprises: a first-in-first-out (FIFO) buffer; write logic to write the error input data samples into the FIFO buffer at a first rate; a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating corresponding interpolated data samples as output of the fractional sample rate converter at a second rate Fhi; and read logic to transfer the input data samples in the FIFO buffer to the fractional interpolator, wherein a ratio of the second rate to the first rate is a fraction greater than 1.

[0025] In some embodiments, the write logic writes the input data samples into the FIFO buffer at a first constant frequency constituting the first rate Flo, and wherein the read logic is to transfer the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency averaging constituting the first rate.

[0026] In some embodiments, the fractional interpolator generates the interpolated data samples from the input data samples using linear interpolation.

[0027] In some embodiments, the write logic comprises: a register to receive each of a plurality of input data samples from a source at the first rate, the register to store the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at an output of the register within one cycle of the low frequency clock, the output of the register coupled to an input data port of the FIFO buffer; a flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to toggle at each active edge of the low frequency clock; a cross-clock-domain synchronizer having an input coupled to the output of the flip-flop, the cross-clock-domain synchronizer to receive a high frequency clock Fxo having a frequency equal to Fhi*Lint, where Lint is an integer, and to store the output of the flip-flop at active edges of the high frequency clock Fxo, the stored output of the flip-flop to serve as a synchronization signal at a second output of the cross-clock-domain synchronizer; and an edge detector coupled to receive the synchronization signal, the edge detector to generate a pulse at a third output of the edge detector from the synchronization signal at a rate equal to the first rate, wherein the third output is coupled to a write enable terminal of the FIFO buffer to cause input data samples to be written to the FIFO buffer at the first rate synchronized with the high frequency clock.

[0028] In some embodiments, the edge detector comprises: a delay element coupled to the second output, the delay element to delay the synchronization signal by a duration equal to one clock period of the high frequency clock and to generate a delayed synchronization signal at a fourth output of the delay element; and an exclusive OR (XOR) gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

[0029] In some embodiments, the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

[0030] In some embodiments, the fractional interpolator is to compute a current interpolation sample according to the following equation: where Xhi[m] represents the current interpolated data sample, Xlo[k] and Xlo[k-1] represent input data samples used to compute the current interpolated sample, Llin represents the ratio of the second rate to the first rate, and 'r' is equal to the expression {m - (k - 1) * Llin}, where m and k are sample indices of the interpolated sample and the input data samples; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter computes a value of 'r / Llin', the real counter computes a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwards the 'r / Llin' value to the fractional interpolator, the real counter further operates as the read logic; wherein the real counter is to: initialize r / Llin to zero when the fractional sample rate converter is reset; increment r / Llin by 1 / Llin at the second rate; and if the increment value of r / Llin is greater than or equal to 1.0, set the increment value to equal (r / Llin - 1.0) and cause the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting represents a rollover condition.

[0031] In some embodiments, the fractional sample rate converter further comprises a computation engine to compute a value of 1 / Llin, the computation engine provides the value of 1 / Llin to the real counter, wherein the computation engine updates the value of 1 / Llin from time to time to compensate for frequency drifts of the high frequency clock and the low frequency clock, wherein the real counter applies the updated value of 1 / Llin when the rollover condition occurs, wherein when an overflow condition occurs in the FIFO buffer, logic in the FIFO buffer is to replace the last sample in the FIFO buffer with an arithmetic average of the next input data sample received from the write logic and the last sample, and wherein when an underflow condition occurs, the fractional interpolator is to compute a next input data sample Xlo[k-2] to compute a next interpolated sample according to the equation: Xlo[k-2] = (2*Xlo[k]) - Xlo[k-1], where Xlo[k] and Xlo[k-1] are the last two samples currently available in the fractional interpolator. BRIEF DESCRIPTION OF DRAWINGS

[0032] Example embodiments of the present application will be described with reference to the following figures briefly described below.

[0033] Figure 1 A block diagram of an example device that can implement aspects of the present application is shown.

[0034] Figure 2A block diagram showing a low pass filter block used in a phase locked loop (PLL) in embodiments of the application is shown.

[0035] Figure 3A A block diagram showing a fractional sample rate converter in embodiments of the application is shown.

[0036] Figure 3B A block diagram showing implementation details of a synchronizer and edge detector used in a fractional sample rate converter in embodiments of the application is shown.

[0037] Figure 4A A block diagram showing relevant details of a FIFO used in a fractional sample rate converter in embodiments of the application is shown.

[0038] Figure 4B A block diagram showing relevant details of a FIFO used in a fractional sample rate converter in embodiments of the application to support an overflow condition is shown.

[0039] Figure 5 A timing diagram showing the signal timing at various nodes of a synchronizer and edge detector used in a fractional sample rate converter in embodiments of the application is shown.

[0040] Figure 6 A schematic diagram showing a linear interpolation approach used in a fractional interpolator provided in embodiments of the application is shown.

[0041] Figure 7A and 7B Schematic diagrams showing an ideal case and an overflow case, respectively, of a FIFO used in a fractional sample rate converter in embodiments of the application are shown.

[0042] Figure 8 A schematic diagram showing an underflow case of a FIFO used in a fractional sample rate converter in embodiments of the application is shown.

[0043] In the drawings, like reference numerals are generally used to refer to same, similar, and / or corresponding elements throughout the drawing figures and illustrative embodiments. The numerical references, in the drawings, are designed to further illustrate embodiments of the present application. DETAILED DESCRIPTION

[0044] 1. SUMMARY

[0045] According to one aspect of the application, a fractional sample rate converter includes a first-in-first-out (FIFO) buffer, write logic, read logic, and a fractional interpolator. The write logic is configured to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and configured to generate corresponding interpolated data samples as output of the fractional sample rate converter at a second rate. The read logic is configured to transfer the input data samples in the FIFO buffer to the fractional interpolator. A ratio of the second rate to the first rate is a fraction greater than one.

[0046] In one embodiment, the write logic writes input data samples into the FIFO buffer at a first constant frequency constituting the first rate (Flo), and the read logic transfers the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency averaging to constitute the first rate.

[0047] Several aspects of the application are described below with reference to examples to illustrate. However, those skilled in the art will recognize that the application can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the application. Further, for the sake of simplicity, only some combinations of features / aspects are described herein, but the described features / aspects can be implemented in various combinations.

[0048] 2. Example device

[0049] Figure 1 A block diagram of an example device in which several aspects of the application can be implemented is shown, and implementation details of a phase-locked loop (PLL) are illustrated. The shown PLL 100 includes input clock dividers 110 and 160, a data selector (MUX) 115, a phase digital converter 121, a digital filter 130, a digitally controlled oscillator (DCO) 140, an output clock divider (DIVo) 150, a feedback clock divider 185, a clock switching controller 170, and a reference clock generator 195. The specific blocks / components of the PLL 100 are shown by way of illustration only. Those skilled in the relevant art, upon reading the disclosure provided herein, will readily recognize that other embodiments of the PLL 100 can be implemented with other blocks / components. For example, the phase digital converter 121 can be replaced by a time-to-digital converter (TDC), with corresponding changes to the PLL 100. Further, while the feedback clock divider 185 is shown as a combination of a fractional (frac-N) feedback divider 180 and a delta sigma modulator (DSM) 190, the feedback clock divider 185 can also be implemented as an integer divider if fractional division is not required.

[0050] Input clock divider 110 receives an input clock fin-1 on path 108, divides fin-1 to produce a desired frequency, and provides the divided input clock as an output (fin-1d) on path 111. Input clock divider 160 receives an input clock fin-2 on path 109, divides fin-2 to produce a desired frequency, and provides the divided input clock as an output (fin-2d) on path 161. The values of the division ratios used by input clock divider 110 and input clock 160 are such that clocks fin-1d and fin-2d have the same frequency (possibly within some error range).

[0051] MUX 115 receives fin-1d and fin-2d, and forwards one of fin-1d and fin-2d on path 112 as an output (MUX output / selected clock) based on the logic value of selection signal 171.

[0052] Phase-to-digital converter 121 receives MUX output 112 and feedback clock 182 (fb), generates an (internal) error signal whose value is proportional to the (current) phase difference between signal 112 and signal 182, and provides the error signal in digital form to path 123. Path 123 can represent one or more digital paths, each path being used to digitize a corresponding bit of the error signal. Phase-to-digital converter 121 receives a sampling clock Flo (122), and generates the digital error signal to path 123 at a rate of Flo. Clock Flo (122) can be generated internally to PLL 100.

[0053] In an alternative embodiment, component / block 121 can be implemented as a time-to-digital converter (TDC) in a known manner, while the implementation of other blocks of PLL 100 is modified accordingly, as will be apparent to those skilled in the art. In general, component 121 functions as a phase detector, receives signals 112 and 182 (fb), and generates an error signal in digital form to path 123, the digital error signal representing the phase error between signals 112 and 182 (fb).

[0054] Digital filter 130 provides data samples to path 134 at a higher rate (Fxo) based on input samples received from path 123 at a lower rate Flo. The output samples on path 134 can be generated based on interpolation. As described below, digital filter 130 also receives clocks Flo (122) and Fxo (131) to enable internal operations. Clock Fxo (131) can be generated internally in PLL 100. In one embodiment, digital filter 130 can additionally operate as a digital low-pass filter, and further, can introduce any desired delay to the received or generated data samples. Thus, the output samples on path 134 represent a low-pass filtered version of the input samples on path 123.

[0055] Digital controlled oscillator (DCO) 140 receives samples from path 134. DCO 140 generates a periodic signal fout (148) whose frequency is determined by the size of the data samples currently received as input. DIVO 150 divides the frequency of fout by a desired number to generate fout-d (151).

[0056] Feedback clock divider 185 receives fout (148) and divides the frequency of fout by a desired value. Typically, feedback clock divider 185 provides a division ratio such that fout is generated at a multiple of the frequency of the selected one of input clock fin-1 and input clock fin-2. DSM 190 can be programmed by a user (by means not shown) to cause feedback clock divider 185 to use a fractional division ratio. Depending on the particular division ratio, DSM 190 generates a corresponding set of division values (which are repeatedly provided to fractional feedback divider 180 to cause the frequency of feedback clock fb (182) to average to the desired fraction of the fout frequency). An integer divider can also be used in place of component 185. Alternatively, DSM 190 can be programmed to cause fractional feedback divider 180 to also divide fout by an integer divisor.

[0057] Clock switching controller 170 receives clocks fin-1 d and fin-2 d. Clock switching controller 170 includes circuitry to determine whether a clock is valid / operating properly. In addition, clock switching controller receives sampling clock Flo (122) to enable operations (including counting). In one embodiment, such circuitry is implemented as one or more counters that count the number of cycles of a received clock (in a predetermined duration) to determine whether the corresponding clock is operating properly. Clock switching controller 170 can require a non-zero length of time to determine whether the currently used input clock is not operating properly. In embodiments of the present application, clock switching controller 170 requires a count of two cycles to determine whether the corresponding clock is operating properly.

[0058] The clock switching controller 170 can be pre-programmed to consider fin-1 / fin-1d as the master clock and fin-2 / fin-2d as the slave clock / redundant clock. Thus, by default (e.g., upon power-up of the PLL 100), the clock switching controller 170 can program the binary value of the select signal 171 to cause the MUX 115 to forward fin-1d to the path 112. The clock switching controller 170 continues to check whether fin-1d is functioning properly. Upon determining that fin-1d has failed (invalid / non-functional) or if an explicit command (e.g., based on user input or from an external device) is received on the path 179 to switch to the slave clock, the clock switching controller 170 implements the glitchless switch to fin-2d by controlling components in the digital filter 130 and the feedback clock divider 185. The clock switching controller 170 can require a non-zero length of time to react to the explicit command received on the path 179 to switch to the slave clock. The clock switching controller 170 can similarly operate to switch from using the slave clock to using the master clock if the slave clock fails or if an explicit command is received on the path 179 to switch back to the master clock.

[0059] The reference clock generator 195 generates a (high-precision and high-stability) reference clock 197. Typically, the ratio of the frequency of the reference clock 197 to the (ideal / desired) frequency of fin-1d and fin-2d is fixed and known (the ratio can be fractional or integer). The reference clock 197 is used to estimate the frequency error of the (actual) frequency of fin-1d and / or fin-2d with respect to the ideal / desired frequency and to correct for such error in the PLL 100 output. The clock switching controller 170 generates a reset signal RST-sync (178) to release the feedback clock divider 185 from a reset that is synchronized with respect to the clock fin-2d (161). The clock switching controller 170 can be implemented in a known manner.

[0060] As mentioned above, the sampling rate of the input data samples provided to the digital filter 130 through the path 123 is Flo, which is lower than the sampling rate Fxo of the output data on the path 134. In the example of Fig. 1, the DCO 140 is implemented as another PLL (embedded PLL) and runs at the rate Fxo, i.e., the reference clock of the embedded PLL is the clock Fxo and several other blocks of the embedded PLL also run using Fxo. Several corrections (in case of a malfunctioning input clock or switching) are applied in the digital filter 130 and combined with various other corrections (not shown or described as being unrelated) and provided as input to the DCO 140 on the path 134. Such input to the DCO 140 also needs to run at the rate Fxo. Figure 1

[0061] ​Therefore, PLL 100 represents an example of a multi-sampling-rate device or system. See below for reference. Figure 2 Implementation details of the digital filter block 130 in the embodiments of this application are provided.

[0062] 3. Digital filter block

[0063] Figure 2 Examples illustrating this application are shown. Figure 1 A detailed block diagram of the digital filter 130 is shown. The digital filter 130 is shown as comprising a fractional sampling rate converter 210, a digital low-pass (DLP) filter 220, and a cascaded integrator comb (CIC) filter 230. For simplicity, the aforementioned delay block is not shown separately and can be assumed to be provided within 220. It is only necessary to note here that the delay provided by the delay block allows the PLL 100 to switch between input clocks without causing transients in the output clock fout (148) due to non-zero time, which the clock switching controller 170 requires to switch the PLL 100 from the currently used input clock to a different input clock.

[0064] exist Figure 2 In the diagram, each data sample on paths 123, 212, 223, and 134 can be several bits wide, even though these paths are shown as single lines.

[0065] The fractional sample rate converter 210 receives data samples from path 123 at rate Flo and increments the sampling rate by a fraction greater than 1 (Llin) to generate output data samples to path 212 at rate Fhi using interpolation. The ratio of rate Fhi to Flo, Llin, is a fraction greater than 1. In one embodiment, this ratio is 1.66, although other fractional ratios are also possible. The fractional sample rate converter 210 receives clocks Flo and Fxo. Rate Fhi is equal to rate Fxo / Lint, where Lint is an integer.

[0066] DLP filter 220 operates at a rate Fxo / Lint (based on a clock with a frequency Fxo / Lint generated internally or typically within PLL 100). Therefore, DLP filter 220 is shown as receiving clock Fxo / Lint (221). DLP filter 220 includes one or more digital filters (operating at Fxo / Lint) to provide low-pass filtering of samples on path 212 (or equivalently) path 123. DLP filter 220 forwards the low-pass filtered samples to path 223 at a rate Fxo / Lint.

[0067] The CIC filter 230 increases the sample rate of the samples of the path 223 by an integer value Lintto the rate Fxo, and is shown as receiving clocks Fxo / Lintand Fxo. The CIC filter 230 provides samples to the path 134 at the rate Fxo. The DLP filter 220 and the CIC filter 230 can be implemented in a known manner. It can be appreciated that the overall increase in sample rate from the samples on the path 123 to the samples on the path 134 is the product of the fractional sample rate factor (Llin) provided by the fractional sample rate converter 210 and the integer sample rate factor (Lint) provided by the CIC filter 230. The specific value of the product L of Llinand Lint(i.e., Fxo / Flo) can be selected according to the specific design requirements of the PLL 100.

[0068] Figure 2 The order of the blocks in the middle is for illustration only. In alternative embodiments, the location / order of the blocks can change with corresponding changes to the design details thereof. For example, the location of the fractional sample rate converter 210 and the DLP filter 220 can be interchanged, with the DLP filter 220 being connected directly to the path 123, and the converter 210 can be connected to the path 212. In other embodiments, the CIC filter 230 can not be implemented.

[0069] The implementation details and operation of the fractional sample rate converter 210 are next provided as shown in FIG. 4. Figure 2

[0070] 4. Fractional Sample Rate Converter

[0071] Figure 3A A block diagram of the fractional sample rate converter in the embodiments of the present application is shown. The fractional sample rate converter 210 is shown as including a register 310, a flip-flop 340, a cross-clock domain synchronizer 350 (synchronizer 350), an edge detector 360, a first-in-first-out buffer (FIFO) 320, a fractional interpolator 330, a counter 370, and a 1 / Llincomputation engine 380. In Figure 3A The paths including the plurality of bit lines are marked with a forward slash ( / ) and all include the same number of bit lines. The register 310 and the flip-flop 340 operate based on (synchronize with) the clock Flo(122). Figure 3A The remaining blocks operate based on (synchronize with) the clock Fxo(351). The use of the higher frequency clock Fxo(equal to Fhi*Lint) instead of Fhi simplifies the implementation and operation of these modules. In the following description, for ease of illustration and description, it is assumed that the data sample 301 corresponds to the data sample 123 in (of Figure 1 and Figure 2 and the interpolated sample 331 corresponds to the interpolated sample 331 in (of Figure 1 and Figure 2 ​data samples 134 in the stream of data samples 134.

[0072] Register 310 receives multi-bit (N bits, where N can be, for example, 32) input data samples Xlo[k] on path 310, where k represents an index or sample number, and stores a sample on an active edge (e.g., a rising edge) of a clock Flo (122) applied to the clock terminal of register 310. The input sample is available at the output (Q) of the register until the next active edge of Flo, at which time the next input data sample is stored and available at the output. The output (Q) is connected through path 312 to the input (IN) of FIFO 320.

[0073] Flip-flop (FF) 340 and inverter 341 operate together to divide the frequency of clock Flo (122) applied to the clock terminal of FF 340 by two. The single bit output (Q) of FF 340 is connected through inverter 341 to the D input of FF 340. The divided frequency clock is provided through path 345 to the input of synchronizer 350.

[0074] Synchronizer 350 minimizes or eliminates the possibility of metastability when the divided frequency clock 345 crosses from the domain of clock Flo to the domain of clock Fxo. Clock Flo and clock Fxo are asynchronous to each other, except for having different frequencies. From the perspective of clock Fxo, the divided frequency clock 345 is a clock signal that is derived from clock Flo. The divided frequency clock 345 is derived from clock Flo, and thus is in the domain of clock Flo. Clock Fxo is in the domain of clock Fxo. The divided frequency clock 345 is in the domain of clock Flo, and thus is in the domain of clock Fxo. Clock Fxo is in the domain of clock Fxo. Figure 3A It can be seen that blocks 310 and 340 operate in the domain of Flo (122), while the other blocks operate in the domain of Fxo (351). Synchronizer 350 operates in the domain of Fxo (351), as does the rest of the circuitry in FIG. 3. Figure 3B As shown, synchronizer 350 is implemented as a pair of flip-flops 355A and 355B connected in series, such that signal 345 passes through both flip-flops (each flip-flop clocked by Fxo) to provide a synchronized divided frequency clock to path 356. Although only a pair of flip-flops in series is shown for synchronizer 350, as is well known in the relevant art, depending on the frequency of Fxo, for example, more than two flip-flops in series can be employed for synchronization operation, for example, when Fxo is very high. Synchronizer 350 provides the synchronized divided frequency clock 356 as an input to edge detector 360.

[0075] Referring again to FIG. 3, Figure 3A Edge detector 360 receives clock Fxo (351) and generates a pulse at each edge of the synchronized divided frequency clock 356. Figure 3BAn implementation of the edge detector 360 in one embodiment is shown in which the edge detector 360 is implemented using a flip-flop 365 and an exclusive OR (XOR) gate 390. The FF 365 delays the divided clock 356 by one period of Fxo (received on the clock input of the FF 365) and provides the delayed clock to path 369. The XOR gate generates the result of the XOR operation of inputs 356 and 369 to generate a pulse on output 362 at each clock edge of clock 356.

[0076] Figure 5 A timing diagram showing the generation of pulses on path 362 is shown, showing several periods of clock Flo (122), input data samples Xlo (on path 301), divided clock 345, synchronized clock 356, delayed clock 369, and pulses 362. Figure 5 Four input data samples Xlo[k], Xlo[k+1], Xlo[k+2], and Xlo[k+3] are also shown, sampled at rate Flo. Time interval t51-t52 is equal to two periods of Fxo, and time interval t52-t53 is equal to one period of Fxo. The pulses on path 362 are also generated at rate Flo, synchronized with Fxo, and at or corresponding to every edge (rising and falling) of the synchronized and divided clock 356, and thus at or corresponding to every active (here, rising) edge of Flo.

[0077] Referring again to Figure 3A , the pulses on path 362 are applied to the write enable (WREN) of FIFO 320 as a write enable (WR) signal. Thus, the input data samples Xlo provided by path 312 are written to the FIFO at Flo rate in a synchronized manner (with respect to clock Fxo). As Figure 5 shown in the timing diagram, the combination of register 310, FF 340, synchronizer 350, and edge detector 360 can be viewed as "write logic" that writes the input data samples Xlo to the FIFO at a constant frequency that constitutes the first rate (Flo). Specifically, if we ignore the one Fxo period of uncertainty of the synchronizer 350 (i.e., the duration between pulses can have an error of 0 or 1 period of the Fxo clock), the duration between the rising edges of the pulses is the same / constant. The frequency can then be considered constant.

[0078] As mentioned above, FIFO 320 is a synchronous FIFO and buffers input data samples written therein via IN input. Among other operations, counter 370 generates a read enable signal (applied at the RD terminal of FIFO 320) to cause the input data samples stored in FIFO 320 to be provided as output (through the OUT terminal) at a rate that varies, but whose average value equals the rate Flo, as described below.

[0079] Figure 4A Internal details of FIFO 320 are shown, wherein FIFO 320 is shown to include write control 410, write pointer 415, input register 420, flag logic 430, dual port random access memory (DPRAM) 450, output register 470, read control 475, and read pointer 480. The specific details of synchronous FIFO 320 are for illustration only. Synchronous FIFO 320 can be implemented to include more or fewer blocks, as is well known in the relevant art. Writing to and reading from synchronous FIFO 320 are both synchronous with respect to clock Fxo. FIFO 320 can be implemented in a known manner, whose internal details are described only briefly below.

[0080] DPRAM 450 represents a memory array. Writing to and reading from the memory array can be performed simultaneously. Input register 420 is connected to path 312 (IN terminal of FIFO 320, as shown in Figure 3A Input register 420 is connected to path 312 (IN terminal of FIFO 320, as shown in Figure 5 Input register 420 is connected to path 312 (IN terminal of FIFO 320, as shown in

[0081] The read pointer 480 includes the current address of the memory cell in the DPRAM 450 to be read. The output register 470 receives a sample of stored data from the memory cell (in the DPRAM 450) on the active edge of signal 477, the address of which is currently included in the read pointer 480. The data sample is located at path 323 (the OUT terminal of FIFO 320, as shown below). Figure 3A Available on (as shown). Signal 477 is a pulse generated synchronously with Fxo when RDEN 372 is activated. As described below, RDEN 372 is generated by counter 370 (e.g., in the form of a pulse). After a read, assuming the FIFO (or DPRAM 450) is not empty, the read pointer 480 increments to the next address in the array, or, if the read pointer 480 points to the highest memory address, it is reset to the lowest address (the address of the first cell in FIFO 320). However, if the FIFO is empty, the read pointer does not increment, and the data sample on path 323 will be invalid / indeterminate.

[0082] The flag logic is connected to the write pointer 415 and the read pointer 480, and includes multiple flags indicating the state of the FIFO 320 based on the addresses in the current write pointer 415 and read pointer 480. Figure 4A Only two flags, 321(E) and 322(F), are shown. Flag 321 is asserted (e.g., binary 1) when FIFO 320 is empty, and flag 322 is asserted when FIFO 320 is full. Flags 321 and 322 are connected to the E (empty) and F (full) terminals of interpolator 330, respectively. Upon reset / power-on, the read pointer 480 and write pointer 415 are initialized to the lowest memory address (zero). The flags are then reset to their appropriate values.

[0083] It is important to note that although labeled as a synchronous FIFO, FIFO 320 can also be implemented as an asynchronous FIFO in other embodiments, as will be apparent to those skilled in the art. In an asynchronous FIFO, the read and write pointers operate in (separate / different) read and write clock domains. To detect conditions such as a full or empty FIFO, the read and write pointers must be compared using the read / write logic implemented in the asynchronous FIFO. Before performing any such comparison, one pointer needs to be transferred to the clock domain of the other. Understandably, such a transfer is not required in the synchronous FIFO 320. Generally, it is worth noting that synchronous FIFOs are typically simpler, smaller, faster, and consume less power than asynchronous FIFOs.

[0084] Continue to refer to Figure 3AThe non-integer (fractional) interpolator 330 receives input data samples (at a sampling rate of Flo) from path 323, which are controlled by the RDEN signal from the ROL terminal of counter 370. The fractional interpolator 330 generates an Llin interpolated data sample for each input data sample received, where Llin is a fraction greater than 1. The fractional interpolator 330 provides the interpolated data samples Xhi[m] to path 331 at a rate of Fhi, where "m" is an index or sample number. As noted above, the ratio of the frequency Fhi to the frequency Flo is equal to Llin, a fraction greater than 1. An example value of Llin is 1.66.

[0085] The operation of the counter 370, which causes input data samples to be read, and the fractional interpolator 330, which causes interpolated data samples to be generated at a rate of Fhi, is next briefly described.

[0086] 5. Fractional Interpolation

[0087] In embodiments of the present application, the fractional interpolator 330 employs linear interpolation. However, the techniques described herein can also use other types (e.g., higher order) interpolation techniques. Figure 6 is a graph illustrating several samples of Xlo and Xhi. Label 600 represents the envelope of the sampled input signal. Two samples of Xlo are used to obtain a linearly interpolated sample of Xhi. Time instances t61, t62, t63, t64, and t65 correspond to (m-1)*Thi, (k-1)*Tlo, m*Thi, k*Tlo, and (m+1)*Thi, respectively, where m and k are indices of the interpolated data sample Xhi and the input data sample Xlo, respectively, and Thi and Tlo are the reciprocals of the sampling rates Fhi and Flo, respectively. At time 0, indices k and m are each 0. Labels 650 and 670 indicate the amplitudes Xlo[k] and Xlo[k-1] of the input data samples at (k)*Tlo and (k-1)*Tlo, respectively. Label 660 represents the interpolated amplitude Xhi[m] of the interpolated (i.e., output) data sample at m*Thi, which is generated by the fractional interpolator 330 using a pair of input data samples Xlo[k] and Xlo[k-1] using a straight line approximation. Label 601 represents the straight line formed by samples Xlo[k] and Xlo[k-1]. Label 605 represents the time interval equal to {m-(k-1)*Llin}*Thi, which is equal to r*Thi. For clarity, input data samples (k-1)*Tlo and k*Tlo are not shown in FIG. 6. Figure 6are represented by dashed lines. In the following description, Xlo[k] represents the current input data sample, Xlo[k-1] represents the next input data sample, and so on. Similarly, Xhi[m] represents the current interpolated data sample, Xhi[m-1] represents the next interpolated data sample, and so on.

[0088] Using the straight line equation in two-point form, xhi[m] can be evaluated based on the following mathematical relationship:

[0089]

[0090] where,

[0091] m and k are the time indices of samples Xhi and Xlo, respectively, and

[0092] Llin is the fractional interpolation ratio Fhi / Flo.

[0093] Rearranging Equation 1 provides an expression for xhi[m] as follows:

[0094]

[0095] It can be appreciated that implementing Equation 2 directly can present some difficulties. For example, the discrete time indices m and k need to be tracked. Index m needs to be incremented for each period of the output clock Fhi, and k needs to be incremented for each period of the input clock Flo. For each output sample Xhi, r, i.e., {m - (k - 1)*Llin}, needs to be evaluated. Such an implementation is impractical because the counters used to generate indices m and k need to have infinite width. Furthermore, there are corresponding difficulties in implementation for the input sample Xlo[k] in clock domain Flo and the interpolated sample Xhi[m] in clock domain Fhi.

[0096] The present application recognizes the following relationships related to indices m and k and variable r:

[0097] 1. At every tick of Fhi, m ≥ (k - 1)*Llin

[0098] 2. The value of r = m - (k - 1)*Llin always falls in the range [0, Llin)

[0099] 3. If r + 1 < Llin, the next value of r is r + 1

[0100] 4. If r + 1 ≥ Llin, the next value of r is r + 1 - Llin

[0101] (As used herein, ‘≥’ represents a greater than or equal to condition,

[0102] ‘<’ denotes a less than condition, and

[0103] ‘*’ denotes a multiplication operation.

[0104] Based on the above description, the variable r is generated using a real counter. Figure 3A The counter 370 in FIG. 11 represents such a counter. The counter 370 receives the clock Fhi (at a rate of Fxo / Lint, thus synchronized with the clock Fxo) on input ‘INCR’ (371), and implements the following logic:

[0105] a. Initialize r to 0 at reset / power-up of the sample rate converter 210.

[0106] b. At the next tick of Fhi (active edge), increment r by 1. If the incremented value of r is greater than or equal to Llin (point 4 above), set r to r+1-Llin (case of roll-over of the counter 370).

[0107] c. Whenever r+1≥Llin (i.e. a roll-over case of the counter 370 occurs), read the FIFO 320 by pulsing RDEN 372, and the next sample Xlo in the FIFO 320 is provided to the fractional interpolator 330.

[0108] d. Repeat from b.

[0109] The counter 370 provides the current value of r to the fractional interpolator 330 through an output named ‘r’ and path 374.

[0110] In one embodiment of the application, the fractional interpolator 330 receives as input the value of ‘r’ as computed by the counter 370 through path 374 (labeled r on the input and also on the output of the counter 370) as described above. The fractional interpolator 330 computes the “current” interpolated sample Xhi[m] according to equation 2. The fractional interpolator 330 provides the computed sample Xhi[m] to path 331. The fractional interpolator 330 internally comprises one or more multiplication units, division units, and addition / subtraction units to implement equation 2.

[0111] Due to the fractional (non-integer) nature of Llin, the number of active edges of Fhi between two roll-over events of the counter 370 averages Llin. However, in terms of actual number, the fractional interpolator 330 generates floor(Llin) or ceil(Llin) interpolated samples for each input data sample. floor(Llin) and ceil(Llin) denote the largest integer less than or equal to Llin and the smallest integer greater than or equal to Llin, respectively.

[0112] The samples Xlo[k] are read from the FIFO 320 at a non-uniform rate (i.e., non-constant rate). If a fixed-size buffer is used instead of the FIFO 320, there can be a situation of insufficient input data samples or loss of input data samples. Using a FIFO (in this case 320) instead of a fixed-delay buffer allows the buffer to expand or shrink as needed. If enough samples have been buffered in the FIFO 320, the problem of synchronization uncertainty (due to the non-synchronized nature of the clocks Flo and Fhi) and the r rollover condition in floor(Llin) Fhi periods will be handled. If there is enough space to accommodate more samples, the r rollover condition in ceil(Llin) Fhi periods will be handled. In one embodiment, the ratio Fxo / Flo is greater than or equal to 6, and the depth of the FIFO 320 is 5. Upon reset, the FIFO 320 is initialized to include three zero-valued input data samples to prevent the r (or equivalently, the counter 370) rollover condition from occurring in floor(Llin) Fhi periods before the first sample of Xlo is written to the FIFO 320.

[0113] Thus, for each sample of input Xlo, on average, the fractional interpolator 330 generates Llin interpolation samples to path 331. Thus, the fractional interpolator 330 "averages" to consume input samples at a rate of Fhi / Llin. Since Fhi / Llin is equal to Flo, the counter 370 causes the input data samples in the FIFO 320 to be transferred (on path 323) to the fractional interpolator 330 at an "variable frequency" that averages to a rate of Flo.

[0114] According to another aspect of the application, in an alternative embodiment, instead of the fractional interpolator 330 computing r / Llin to generate each interpolation sample Xhi, the counter 370 computes and provides the value r / Llin itself (rather than just r) at each active edge of Fhi (371) on terminal "COUNT" and provides it to the fractional interpolator 330 through path 373, which receives the value on terminal r / Llin. The fractional interpolator 330 computes Xhi[m] according to equation 2. In an embodiment, the counter 370 increments by 1 / Llin at each active edge of Fhi. Correspondingly, the rollover condition for the counter 370 is when r / Llin evaluates to greater than or equal to 1.0, in which case r / Llin is set to (r / Llin - 1.0). The increment of 1 / Llin and the rollover condition r / Llin >= 1.0 can be derived from the relationships in points 2, 3, and 4 above.

[0115] Counter 370 receives value 1 / Llin from 1 / Llin computation engine 380. In an embodiment, 1 / Llin computation engine 380 is additionally implemented to compute 1 / Llin and provide 1 / Llin to counter 370 over path 387. In Figure 1 In the example environment of PLL 100, engine 380 computes Llin according to the following equation:

[0116] Llin = Fhi / Flo = (I2+P2 / Q2) / (I1+P1 / Q1) / Nadc_p4 / Nadc_down… Equation 3

[0117] where parameters I1, P1, Q1, I2, P2, Q2, Nadc_p4, and Nadc_down are internal parameters (381) of PLL 100 (380) that can be obtained / implemented in known manners. Figure 1

[0118] However, in other environments, Llin can be determined based on other considerations based on requirements of the environment. Engine 380 receives each of the above-mentioned parameters and computes 1 / Llin based on Equation 3 above. The frequencies of clocks Fxo (from which Fhi is derived) and Flo can drift over time. Thus, engine 380 computes 1 / Llin from time to time (e.g., periodically). If the computed value is different from the current value of 1 / Llin, engine 380 forwards the new value of 1 / Llin to counter 370, which applies the new value when counter 370 rolls over to determine r / Llin (sent over path 373).

[0119] Due to rounding errors in the register (within engine 380, and in one embodiment 32 bits wide) that stores 1 / Llin, and due to drifts in one or both of clocks Flo and Fxo being very large, FIFO 320 can overflow or underflow before the new value 1 / Llin is computed and applied as described above. According to another aspect of the present application, such overflow or underflow of FIFO 320 is detected by fractional sampling rate converter 210 and corrective measures are taken accordingly. Thus, in the example embodiment of Figure 3A FIFO 320 provides empty (E) and full (F) flags to fractional interpolator 330 over paths 321 and 322, respectively. An asserted empty (E) flag indicates underflow, while an asserted full (F) flag indicates overflow. Flag logic 430 Figure 4A ) can use the values in the write and read pointers in FIFO 320 and the depth (size) of FIFO 320 to determine whether an underflow or overflow condition has occurred.

[0120] ​From the above description, it can be understood that the fractional interpolator 330 always has the last two samples Xlo[k] and Xlo[k-1], assuming no overflow or underflow condition occurs. When an overflow occurs, the next sample that should have been fetched from the FIFO 320 is overwritten by the next subsequent sample. Figure 7A and 7B illustrate the ideal case and the overflow case, respectively, for the “current” time instant, assuming a depth of 3 for the FIFO 320 for illustrative purposes only. With respect to Figure 7A , Xlo[k-1] and Xlo[k] are available within the fractional interpolator 330 and have been used to compute the latest interpolated sample Xhi[m]. The cells 710, 711 and 712 of the FIFO 320 are shown to include the samples Xlo[k-2], Xlo[k-3] and Xlo[k-4], respectively, and no overflow has occurred. To compute the next value of the interpolated sample (and the counter 370 has flipped, the fractional interpolator 330 obtains Xlo[k-2]), Xlo[k-1] becomes Xlo[k], Xlo[k-2] becomes Xlo[k-1], the fractional interpolator uses the “current” Xlo[k] and Xlo[k-1] to compute Xhi[m], which is now the current interpolated sample.

[0121] However, if an overflow condition occurs, additional logic included in the FIFO 320 (as shown in Figure 4B ) replaces the last sample in the FIFO with an arithmetic average of the next sample Xlo[k-5] (received on path 312 and available, for example, in the input register 420 of FIG. 4) and the last sample Xlo[k-4], as shown in Figure 7B , i.e.:

[0122] Xlo[k-4] = (Xlo[k-4] + Xlo[k-5]) / 2 … Equation 4

[0123] As described herein, the fractional interpolator 330 will eventually receive the sample value (Xlo[k-4] + Xlo[k-5]) / 2 and use the sample value in the process of computing the interpolated sample.

[0124] Figure 4B shows the changes to the FIFO buffer 320 of Figure 4A to support the above-described operations in the case of an overflow. The FIFO buffer 320B of Figure 4B includes Figure 4AThe FIFO buffer 320B comprises all blocks, an additional block named overflow logic 490, and corresponding connections to / from overflow logic 490 and modifications to the corresponding blocks, such as write control 410, read control 475, etc. It should be noted that the specific details of the FIFO buffer 320B are provided for illustrative purposes only, and there are other ways to implement the additional logic shown. In operation, when overflow flag 322 indicates an overflow condition, overflow logic 490 signals write control 410 via bidirectional path 491 to send a signal back via path 491 when the next input data sample (Xlo[k-5]) has been written to input register 420. When an indication that the next input data sample has been written to input register 420 is received via path 491, overflow logic 490 retrieves the data sample (Xlo[k-5]) from input register 420 via bidirectional path 429. Overflow logic 490 signals read control 475 via bidirectional path 497 to retrieve the previous sample Xlo[k-4] (in dual-port RAM 450). Read control 475 and read pointer 480 retrieve the previous sample Xlo[k-4], which is available at output 457 of DPRAM 450. Read control 475 signals overflow logic 490 via path 497, making the previous sample Xlo[k-4] available at output 457 of DPRAM 450. Overflow logic 490 then reads the previous sample Xlo[k-4] from output 457. Internally, overflow logic includes logic for generating the arithmetic mean of the next sample Xlo[k-5] and the previous sample Xlo[k-4]. These operations can be performed simultaneously, consecutively, or in combination. Overflow logic 490 then writes the calculated arithmetic mean back to input register 420 via path 429, and sends a signal to write control 410 via path 491 to write the current content of input register 420 to the position of the previous sample. The combination of write control 410 and write pointer 415 writes the arithmetic mean to the position of the previous sample.

[0125] like Figure 8 As shown, when underflow occurs, FIFO 320 does not include any valid samples. Cells 810, 811, 812, and other cells of the FIFO contain invalid data. Fractional interpolator 330 "currently" includes Xlo[k-1] and Xlo[k]. Since there is no valid Xlo[k-2] in FIFO 320, the fractional interpolator calculates Xlo[k-2] according to the following equation:

[0126] Xlo[k-2]=(2*Xlo[k])–Xlo[k–1]…Equation 5

[0127] Xlo[k - 1] becomes Xlo[k], the computed Xlo[k - 2] becomes Xlo[k - 1], and the fractional interpolator uses the "current" Xlo[k] and Xlo[k - 1] to compute Xhi[m].

[0128] As can be seen from Equations 4 and 5, the fractional interpolator applies linear techniques to obtain the correct value of the next input sample to use in the case of overflow and underflow.

[0129] 6. Conclusion

[0130] Throughout this specification, reference has been made to "one embodiment" or "an embodiment" meaning that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, appearances of the phrases "in one embodiment" or "in an embodiment" or similar phrases

[0131] While in Figure 1 , 2 , 3A, 3B, 4A, and 4B, although the ends / nodes / blocks are shown as directly connected (i.e., "connected to") various other ends / nodes / blocks, it should be understood that additional components / blocks (as appropriate to a particular environment) can also be present in the path, and thus the connections can be considered "electrically coupled" to the same connected ends / nodes / blocks.

[0132] While various embodiments of the application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Therefore, the breadth and scope of the application should not be limited by any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A fractional sampling rate converter, comprising: A first-in-first-out (FIFO) buffer with an output node; The write logic writes input data samples to the FIFO buffer at a first rate, wherein the input data samples represent a phase difference sequence between a first clock signal and a second clock signal; A fractional interpolator, coupled to the output node, receives the input data samples from the FIFO buffer. The fractional interpolator generates corresponding interpolated data samples at a second rate Fhi as the output of the fractional sampling rate converter. The read logic transmits the input data samples in the FIFO buffer to the fractional interpolator. Wherein, the ratio of the second rate to the first rate is a fraction greater than 1. The write logic writes the input data samples into the FIFO buffer at a first constant frequency that constitutes the first rate Flo, and The read logic is used to transmit the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency that averages the first rate.

2. The fractional sampling rate converter according to claim 1, wherein, The first clock signal is a reference clock signal of the phase-locked loop (PPL) including the fractional sampling rate converter, and the second clock signal is a feedback clock signal of the frequency divider of the PPL.

3. The fractional sampling rate converter according to claim 1, wherein, The fractional interpolator generates the interpolated data sample from the input data sample using linear interpolation.

4. The fractional sampling rate converter according to claim 3, wherein, The write logic includes: A register is configured to receive each of a plurality of input data samples from a source at the first rate, the register being configured to store the input data sample at the corresponding active edge of a low-frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at the output of the register during one cycle of the low-frequency clock, the output of the register being coupled to the input data port of the FIFO buffer. A trigger having a divide-2 configuration timed by the low-frequency clock, the output of the trigger being used to switch on each active edge of the low-frequency clock; A cross-clock-domain synchronizer, the input of which is coupled to the output of the flip-flop, the cross-clock-domain synchronizer receiving a high-frequency clock Fxo with a frequency equal to Fhi × Lint, where Lint is an integer, and storing the output of the flip-flop on the active edge of the high-frequency clock Fxo, the stored output of the flip-flop being used as a synchronization signal at a second output of the cross-clock-domain synchronizer; and An edge detector, coupled to receive the synchronization signal, generates pulses from the synchronization signal at a rate equal to the first rate at its third output. The third output is coupled to the write enable terminal of the FIFO buffer, enabling input data samples to be written to the FIFO buffer at the first rate synchronized with the high-frequency clock.

5. The fractional sampling rate converter according to claim 4, wherein, The edge detector includes: A delay element, coupled to the second output, delays the synchronization signal for a duration equal to one clock cycle of the high-frequency clock, and generates a delayed synchronization signal at the fourth output of the delay element; and An XOR gate is coupled to receive the synchronization signal and the delayed synchronization signal, and generates the pulse as a result of the XOR operation of the synchronization signal and the delayed synchronization signal.

6. The fractional sampling rate converter according to claim 4, wherein, The FIFO buffer is a synchronous FIFO buffer and operates based on the high-frequency clock.

7. The fractional sampling rate converter according to claim 6, wherein, The fractional interpolator is used to calculate the current interpolated data sample according to the following equation: in, Xhi[m] represents the current interpolated data sample. Xlo[k] and Xlo[k-1] represent the input data samples used to calculate the current interpolated data sample. Llin represents the ratio of the second rate to the first rate, and r equals the expression {m – (k – 1) × Llin}, where m and k are the sample indices of the interpolated data sample and the input data sample, respectively. The fractional sampling rate converter further includes a real counter timed by the high-frequency clock, which calculates the value of r to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample. The real counter forwards the value of r to the fractional interpolator and also operates as the read logic. The real number counter is used for: When the fractional sampling rate converter is reset, r is initialized to zero; Based on the active edge of an intermediate frequency clock with a rate equal to Fhi, r is incremented by 1 at the second rate, wherein the intermediate frequency clock originates from and is synchronized with the high-frequency clock Fxo; and If the increment value of r is greater than or equal to Llin, then r is set to equal to (r-Llin), and the next data sample in the FIFO buffer is transmitted to the fractional interpolator.

8. The fractional sampling rate converter of claim 6, wherein the fractional interpolator is used to calculate the current interpolated data sample according to the following equation: in, Xhi[m] represents the current interpolated data sample. Xlo[k] and Xlo[k-1] represent the input data samples used to calculate the current interpolated data sample. Llin represents the ratio of the second rate to the first rate, and r equals the expression {m – (k – 1) × Llin}, where m and k are the sample indices of the interpolated data sample and the input data sample, respectively. The fractional sampling rate converter further includes a real counter timed by the high-frequency clock, the real counter calculating the value of 'r / Llin', the real counter calculating the value of r to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the 'r / Llin' value to the fractional interpolator, and the real counter also operating as the read logic. The real number counter is used for: When the fractional sampling rate converter is reset, r / Llin is initialized to zero; Increase r / Llin by 1 / Llin at the second rate; and If the increment value of r / Llin is greater than or equal to 1.0, then the increment value is set to equal to (r / Llin-1.0), and the next data sample in the FIFO buffer is transmitted to the fractional interpolator, wherein the setting indicates that a flip has occurred.

9. The fractional sampling rate converter according to claim 8, further comprising: A calculation engine is used to calculate 1 / Llin, and the calculation engine provides 1 / Llin to the real number counter.

10. The fractional sampling rate converter of claim 9, wherein the computing engine updates the 1 / Llin from time to time to compensate for frequency drift of the high-frequency clock and the low-frequency clock, wherein the real number counter applies the updated 1 / Llin when the flip-over occurs.

11. The fractional sampling rate converter of claim 8, wherein when an overflow occurs in the FIFO buffer, the logic in the FIFO buffer is configured to: replace the previous sample in the FIFO buffer with the arithmetic mean of the next input data sample received from the write logic and the previous sample.

12. The fractional sampling rate converter according to claim 11, wherein, In the event of underflow, the fractional interpolator is used to calculate the next input data sample Xlo[k-2] to calculate the next interpolated data sample according to the following equation: Xlo[k-2] = (2×Xlo[k]) – Xlo[k – 1], in, Xlo[k] and Xlo[k-1] are the last two samples currently available in the fractional interpolator.

13. A phase-locked loop (PLL), comprising: A data selector MUX is coupled to receive a first clock and a second clock. If the selection signal has a first value, the MUX forwards the first clock as the selected clock; if the selection signal has a second value, the MUX forwards the second clock as the selected clock. A phase detector, coupled to receive the selected clock and the feedback clock, generates an error signal in the form of an error data sample stream, the error signal representing the phase difference between the selected clock and the feedback clock; A digital filter is used to generate filtered error data samples by filtering the error data samples. An oscillator is coupled to receive the filtered error data samples and generate an output clock, wherein the frequency of the output clock is determined by the magnitude of the filtered error data samples; and A feedback divider generates each consecutive cycle of the feedback clock while counting a predetermined number of cycles of the output clock. Compared to the error data sample, the filtered error data sample has a higher rate. The digital filter includes a digital low-pass filter and a fractional sampling rate converter. The fractional sampling rate converter receives the error data sample as an input data sample, generates interpolated data samples from the input data samples through interpolation, and provides the interpolated data samples to the digital low-pass filter. The digital low-pass filter filters the interpolated data samples and provides the filtered interpolated data samples as the filtered error data sample. The fractional sampling rate converter includes: First-In-First-Out (FIFO) buffer; The write logic writes the error data sample to the FIFO buffer at a first rate. A fractional interpolator, coupled to receive the input data samples from the FIFO buffer, generates corresponding interpolated data samples at a second rate Fhi as the output of the fractional sampling rate converter; and The read logic transmits the input data samples in the FIFO buffer to the fractional interpolator. The ratio of the second rate to the first rate is a fraction greater than 1.

14. The PLL of claim 13, wherein the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and in, The read logic is used to transmit the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency that averages the first rate.

15. The PLL of claim 14, wherein the fractional interpolator generates the interpolated data sample from the input data sample using linear interpolation.

16. The PLL of claim 15, wherein the write logic comprises: A register for receiving each of a plurality of input data samples from a source at the first rate, the register for storing the input data sample at the corresponding active edge of a low-frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at the output of the register during one cycle of the low-frequency clock, the output of the register being coupled to the input data port of the FIFO buffer. A trigger having a divide-2 configuration timed by the low-frequency clock, the output of the trigger being used to switch on each active edge of the low-frequency clock; A cross-clock domain synchronizer, the input of which is coupled to the output of the flip-flop, the cross-clock domain synchronizer receiving a high-frequency clock Fxo with a frequency equal to Fhi × Lint, where Lint is an integer, and storing the output of the flip-flop on the active edge of the high-frequency clock Fxo, the output of the flip-flop being used as a synchronization signal at a second output of the cross-clock domain synchronizer; and An edge detector, coupled to receive the synchronization signal, generates pulses from the synchronization signal at a rate equal to the first rate at its third output. The third output is coupled to the write enable terminal of the FIFO buffer, enabling input data samples to be written to the FIFO buffer at the first rate synchronized with the high-frequency clock.

17. The PLL according to claim 16, wherein, The edge detector includes: A delay element, coupled to the second output, delays the synchronization signal for a duration equal to one clock cycle of the high-frequency clock, and generates a delayed synchronization signal at the fourth output of the delay element; and An XOR gate is coupled to receive the synchronization signal and the delayed synchronization signal, and generates the pulse as a result of the XOR operation of the synchronization signal and the delayed synchronization signal.

18. The PLL according to claim 16, wherein, The FIFO buffer is a synchronous FIFO buffer and operates based on the high-frequency clock.

19. The PLL of claim 18, wherein the fractional interpolator is used to calculate the current interpolated data sample according to the following equation: in, Xhi[m] represents the current interpolated data sample. Xlo[k] and Xlo[k-1] represent the input data samples used to calculate the current interpolated data sample. Llin represents the ratio of the second rate to the first rate, and r equals the expression {m – (k – 1) × Llin}, where m and k are the sample indices of the interpolated data sample and the input data sample, respectively. The fractional sampling rate converter further includes a real counter timed by the high-frequency clock, the real counter calculating the value of 'r / Llin', the real counter calculating the value of r to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the 'r / Llin' value to the fractional interpolator, and the real counter also operating as the read logic. The real number counter is used for: When the fractional sampling rate converter is reset, r / Llin is initialized to zero; Increase r / Llin by 1 / Llin at the second rate; and If the increment value of r / Llin is greater than or equal to 1.0, then the increment value is set to equal to (r / Llin-1.0), and the next data sample in the FIFO buffer is transmitted to the fractional interpolator, wherein the setting indicates that a flip has occurred.

20. The PLL of claim 19, wherein the fractional sampling rate converter further comprises a calculation engine for calculating the 1 / Llin, the calculation engine providing the 1 / Llin to the real number counter. in, The computing engine periodically updates 1 / Llin to compensate for frequency drift between the high-frequency clock and the low-frequency clock, wherein the real number counter applies the updated 1 / Llin when the flip-over occurs. When an overflow occurs in the FIFO buffer, the logic in the FIFO buffer is used to: replace the previous sample in the FIFO buffer with the arithmetic mean of the next input data sample received from the write logic and the previous sample, and In the event of underflow, the fractional interpolator is used to calculate the next input data sample Xlo[k-2], to calculate the next interpolated data sample according to the following equation: Xlo[k-2] = (2×Xlo[k]) – Xlo[k – 1], in, Xlo[k] and Xlo[k-1] are the last two samples currently available in the fractional interpolator.

21. A fractional sampling rate converter, comprising: First-In-First-Out (FIFO) buffer; The write logic writes the input data samples to the FIFO buffer at a first rate. A fractional interpolator, coupled to receive the input data samples from the FIFO buffer, generates corresponding interpolated data samples at a second rate Fhi as the output of the fractional sampling rate converter; and The read logic transmits the input data samples in the FIFO buffer to the fractional interpolator. Wherein, the ratio of the second rate to the first rate is a fraction greater than 1. The fractional interpolator is used to calculate the current interpolated data sample according to the following equation: in, Xhi[m] represents the current interpolated data sample. Xlo[k] and Xlo[k-1] represent the input data samples used to calculate the current interpolated data sample. Llin represents the ratio of the second rate to the first rate, and r equals the expression {m – (k – 1) × Llin}, where m and k are the sample indices of the interpolated data sample and the input data sample, respectively. The fractional sampling rate converter further includes a real counter timed by a high-frequency clock Fxo, the high-frequency clock Fxo having a frequency equal to Fhi × Lint, where Lint is an integer and Fhi is the frequency of an intermediate clock. The real counter calculates the value of r to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample. The real counter forwards the value of r to the fractional interpolator. The real counter also operates as the read logic.

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