Trench gate mosfet and method of forming

Abstract

The application provides a trench gate MOSFET and a forming method, which comprises the following steps: forming a first trench in an epitaxial layer of a cell region and forming a second trench in an epitaxial layer of a gate lead-out region; forming a first gate dielectric layer and a first control gate in the first trench and the second trench; forming a third trench on both sides of the first control gate in the cell region and forming a fourth trench on both sides of the first control gate in the gate lead-out region; forming a second gate dielectric layer and a second control gate in the third trench and the fourth trench, the second control gate is separated from the first control gate by the second gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; forming a well region in the epitaxial layer close to the surface of the epitaxial layer; forming a source-drain terminal in the well region close to the surface of the epitaxial layer in the cell region; forming an interlayer dielectric layer on the surface of the epitaxial layer; forming a first contact hole in the cell region and forming a second contact hole in the gate lead-out region, and the first control gate and the second control gate are communicated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a trench gate MOSFET and a method for forming it. Background Technology

[0002] Trench gate MOSFETs represent the most advanced power MOSFET technology currently available, offering advantages such as lower on-resistance and faster switching speeds. In system applications, they exhibit lower conduction losses and lower switching losses, resulting in higher conversion and transmission efficiency.

[0003] Please refer to Figure 1 The prior art trench gate MOSFET includes: an epitaxial layer 101, which includes a cell region 101A and a gate lead-out region 101B. A well region 102 is formed in the epitaxial layer 101, which is a portion of its thickness near the surface of the epitaxial layer 101. A trench is formed in the well region 102 and the epitaxial layer 101, and a gate dielectric layer 103 is formed on the inner wall of the trench, extending to the surface of the epitaxial layer 101. A control gate 104 is also formed in the trench, and the control gate 104 is separated from the inner wall of the trench by the gate dielectric layer 103. A source / drain terminal 105 is formed in the well region 102 of the cell region 101A, and a first contact hole 106 passes through the gate dielectric layer 103 and the source / drain terminal 105 and stops in the well region 102. The first contact hole 106 connects to the first metal layer 107, which is separated from the gate dielectric layer 103 on the surface of the epitaxial layer 101 by an interlayer dielectric layer 108. In the gate lead-out region 101B, the second contact hole 109 connects the control gate 104 to the second metal layer 110, which is also separated from the gate dielectric layer 103 on the surface of the epitaxial layer 101 by an interlayer dielectric layer 108. All control gates 104 in cell region 101A are connected to the control gates 104 in gate lead-out region 101B, and the second contact hole 109 leads out the control gates 104.

[0004] However, in conventional trench-gate MOSFET devices, the gate dielectric layer 103 on the inner wall of the trench has a uniform thickness, and the electric field strength is strongest at the bottom of the trench. Increasing the thickness of the bottom gate dielectric layer can reduce the strength of the bottom electric field and improve the breakdown voltage. However, if the thickness of the gate dielectric layer is also increased, the threshold voltage will also be affected by the change in the thickness of the gate dielectric layer, leading to an increase in the threshold voltage, which in turn increases the on-resistance of the device and reduces the performance of the device. Summary of the Invention

[0005] The purpose of this invention is to provide a trench gate MOSFET and a method for forming it, which can reduce the on-resistance of the device and improve its performance.

[0006] To achieve the above objectives, the present invention provides a method for forming a trench gate MOSFET, comprising:

[0007] An epitaxial layer is provided, the epitaxial layer including a cell region and a gate lead-out region disposed adjacently;

[0008] A first trench is formed in the epitaxial layer of the cell region, and a second trench is formed in the epitaxial layer of the gate lead-out region, wherein the first trench and the second trench are spaced apart.

[0009] A first gate dielectric layer and a first control gate are formed in both the first trench and the second trench. The first control gate is separated from the inner walls of both the first trench and the second trench by the first gate dielectric layer.

[0010] A third trench is formed on both sides of the upper portion of the first control gate in the cell region, and a fourth trench is formed on both sides of the upper portion of the first control gate located in the gate lead-out region.

[0011] A second gate dielectric layer and a second control gate are formed in both the third and fourth trenches. The second control gate is separated from the inner walls of the third and fourth trenches and the first control gate by the second gate dielectric layer. The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer.

[0012] A well region is formed in the epitaxial layer near the surface of the epitaxial layer, the well region being located on the upper portion of the first control gate;

[0013] Source and drain terminals are formed in the well region near the surface of the epitaxial layer in the cell region;

[0014] An interlayer dielectric layer is formed on the surface of the epitaxial layer;

[0015] A first contact hole is formed in the cell region, the first contact hole passes through the interlayer dielectric layer and the source / drain terminals and stops at the well region, and a second contact hole is formed in the gate lead-out region, the second contact hole stops at the surface of the first control gate and the second control gate, connecting the first control gate and the second control gate.

[0016] Optionally, in the method for forming the trench gate MOSFET, a first trench is formed in the epitaxial layer of the cell region, and a second trench is formed in the epitaxial layer of the gate lead-out region, wherein the method for spacing the first trench and the second trench includes:

[0017] A hard mask layer is formed on the surface of the epitaxial layer;

[0018] Etch a portion of the hard mask layer and a portion of the epitaxial layer to form a first trench in the epitaxial layer of the cell region and a second trench in the epitaxial layer of the gate lead-out region;

[0019] Remove the hard mask layer.

[0020] Optionally, in the method for forming the trench gate MOSFET, the thickness of the first gate dielectric layer is 600 angstroms to 3000 angstroms.

[0021] Optionally, in the method for forming the trench gate MOSFET, the thickness of the second gate dielectric layer is 150 angstroms to 500 angstroms.

[0022] Optionally, in the method for forming the trench gate MOSFET, ions are implanted into the epitaxial layer to form a well region in the epitaxial layer near the surface of the epitaxial layer.

[0023] Optionally, in the method for forming the trench gate MOSFET, the concentration of implanted ions is 8.0e16cm. -3 ~1.36e17 cm -3 .

[0024] Optionally, in the method for forming the trench gate MOSFET, ions are implanted into the well region of the cell region to form source and drain terminals in the well region of the cell region near the surface of the epitaxial layer.

[0025] Optionally, the method for forming the trench gate MOSFET further includes: forming a first metal layer and a second metal layer spaced apart on the surface of the interlayer dielectric layer, wherein the first metal layer is connected to a first contact hole, and the second metal layer is connected to a second control contact hole.

[0026] The present invention also provides a trench gate MOSFET, comprising:

[0027] Epitaxial layer, the epitaxial layer including adjacent cell regions and gate lead-out regions;

[0028] A first trench located in the epitaxial layer of the cell region, and a second trench located in the epitaxial layer of the gate lead-out region;

[0029] The first gate dielectric layer and the first control gate are both located in the first trench and the second trench, and the first control gate is separated from the inner walls of the first trench and the second trench by the first gate dielectric layer.

[0030] The third trench is located on both sides of the upper portion of the first control gate in the cell region, and the fourth trench is located on both sides of the upper portion of the first control gate in the gate lead-out region.

[0031] The second gate dielectric layer and the second control gate are both located within the third trench and the fourth trench. The second control gate is separated from the inner walls of the third trench and the fourth trench and the first control gate by the second gate dielectric layer.

[0032] A well region located within the epitaxial layer near the surface of the epitaxial layer, the well region being located on the upper portion of the first control gate;

[0033] The source / drain terminals are located in the well region within the cell region and close to the surface of the epitaxial layer;

[0034] Interlayer dielectric layer located on the surface of the epitaxial layer;

[0035] A first contact hole is located within the cell region, passing through the interlayer dielectric layer and the source / drain terminals and ending in the well region. A second contact hole is located within the gate lead-out region, ending on the surfaces of the first control gate and the second control gate, thus connecting the first control gate and the second control gate.

[0036] Optionally, the trench gate MOSFET further includes: a first metal layer and a second metal layer located on the surface of the interlayer dielectric layer and spaced apart, wherein the first metal layer is in communication with a first contact hole, and the second metal layer is in communication with a second control contact hole.

[0037] The trench gate MOSFET and its formation method provided by the present invention include: providing an epitaxial layer, the epitaxial layer including a cell region and a gate lead-out region adjacent to each other; forming a first trench in the epitaxial layer of the cell region, and forming a second trench in the epitaxial layer of the gate lead-out region, the first trench and the second trench being spaced apart; forming a first gate dielectric layer and a first control gate in both the first trench and the second trench, the first control gate being separated from the inner walls of both the first trench and the second trench by the first gate dielectric layer; forming a third trench on both sides of the upper portion of the first control gate in the cell region, and forming a fourth trench on both sides of the upper portion of the first control gate located in the gate lead-out region; and forming a second gate dielectric in both the third trench and the fourth trench. The device comprises a first control gate and a second control gate. The second control gate is separated from the inner walls of the third and fourth trenches and the first control gate by a second gate dielectric layer. The thickness of the second gate dielectric layer is less than that of the first gate dielectric layer. A well region is formed in the epitaxial layer near the surface of the epitaxial layer, located in the upper portion of the first control gate. A source / drain terminal is formed in the well region near the surface of the epitaxial layer in the cell region. An interlayer dielectric layer is formed on the surface of the epitaxial layer. A first contact hole is formed in the cell region, passing through the interlayer dielectric layer and the source / drain terminal and ending in the well region. A second contact hole is formed in the gate lead-out region, ending on the surfaces of the first and second control gates, connecting the first and second control gates. This invention increases the thickness of the gate dielectric layer in the lower portion of the first control gate, improving the breakdown voltage. It reduces the thickness of the gate dielectric layer in the upper portion, lowering the on-resistance of the device and improving its performance. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a trench gate MOSFET in the prior art;

[0039] Figure 2 This is a flowchart of a method for forming a trench gate MOSFET according to an embodiment of the present invention;

[0040] Figures 3 to 6 This is a schematic diagram of the structure during the formation process of a trench gate MOSFET according to an embodiment of the present invention;

[0041] In the diagram: 101-Epiaxial layer, 101A-Cell region, 101B-Gate lead-out region, 102-Well region, 103-Gate dielectric layer, 104-Control gate, 105-Source / drain terminals, 106-First contact hole, 107-First metal layer, 108-Interlayer dielectric layer, 109-Second contact hole, 110-Second metal layer, Epitaxial layer 201, 201A-Cell region, 201B-Gate lead-out region, 202-Hard layer Mask layer, 203-first trench, 204-second trench, 205-first dielectric layer, 206-first control gate, 207-third trench, 208-fourth trench, 209-second gate dielectric layer, 210-second control gate, 211-well region, 212-source / drain terminals, 213-interlayer dielectric layer, 214-first contact hole, 215-second contact hole, 216-first metal layer, 217-second metal layer. Detailed Implementation

[0042] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0043] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0044] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0045] Please refer to Figure 2The present invention provides a method for forming a trench gate MOSFET, comprising:

[0046] S11: Provides an epitaxial layer, which includes adjacent cell regions and gate lead-out regions;

[0047] S12: A first trench is formed in the epitaxial layer of the cell region, and a second trench is formed in the epitaxial layer of the gate lead-out region, with the first trench and the second trench spaced apart.

[0048] S13: A first gate dielectric layer and a first control gate are formed in both the first trench and the second trench. The first control gate is separated from the inner walls of both the first trench and the second trench by the first gate dielectric layer.

[0049] S14: A third trench is formed on both sides of the upper portion of the first control gate in the cell region, and a fourth trench is formed on both sides of the upper portion of the first control gate in the gate lead-out region.

[0050] S15: A second gate dielectric layer and a second control gate are formed in both the third and fourth trenches. The second control gate is separated from the inner walls of the third and fourth trenches and the first control gate by the second gate dielectric layer. The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer.

[0051] S16: A well region is formed in the epitaxial layer near the surface of the epitaxial layer, and the well region is located on the upper part of the first control gate;

[0052] S17: Source and drain terminals are formed in the well region near the surface of the epitaxial layer in the cell region;

[0053] S18: An interlayer dielectric layer is formed on the surface of the epitaxial layer;

[0054] S19: A first contact hole is formed in the cell region. The first contact hole passes through the interlayer dielectric layer and the source / drain terminals and stops at the well region. A second contact hole is formed in the gate lead-out region. The second contact hole stops at the surface of the first control gate and the second control gate, connecting the first control gate and the second control gate.

[0055] First, please refer to... Figure 3 A substrate is provided, and an epitaxial layer 201 is formed on the surface of the substrate. The epitaxial layer 201 includes a cell region 201A and a gate lead-out region 201B adjacent to each other. A hard mask layer 202, which may be silicon nitride, is formed on the surface of the epitaxial layer 201. A portion of the hard mask layer 202 and a portion of the thickness of the epitaxial layer 201 are etched to form a first trench 203 in the hard mask layer 202 and the epitaxial layer 201 in the cell region 201A, and a second trench 204 in the hard mask layer 202 and the epitaxial layer 201 in the gate lead-out region 201B. The first trench 203 and the second trench 204 are spaced apart. Then the hard mask layer 202 is removed to expose the surface of the epitaxial layer 201.

[0056] Next, please refer to Figure 4 A first gate dielectric layer 205 is formed on the inner walls of both the first trench 203 and the second trench 204, and the first gate dielectric layer 205 extends to the surface of the epitaxial layer 201. The thickness of the first gate dielectric layer 205 is relatively thick, ranging from 600 angstroms to 3000 angstroms. Polysilicon is then filled into the first trench 203 and the second trench 204 to form a first control gate 206 in both trenches. Next, both the first trench and the second trench are divided into a lower portion and an upper portion according to the direction from the bottom of the epitaxial layer to the surface of the epitaxial layer. The first dielectric layer 205 in the upper portion of the first trench and the upper portion of the second trench is etched, leaving gaps on both sides of the first control gate, thereby forming a third trench 207 on both sides of the upper portion of the first control gate 206 in the cell region 201A, and a fourth trench 208 on both sides of the upper portion of the first control gate 206 in the gate lead-out region 201B. Next, a second gate dielectric layer 209 is formed on the inner wall of both the third trench 207 and the fourth trench 208. The thickness of the second gate dielectric layer 209 is less than the thickness of the first gate dielectric layer 205. The thickness of the second gate dielectric layer 209 can be 150 angstroms to 500 angstroms.

[0057] Next, please refer to Figure 5 Polysilicon is then filled into the third and fourth trenches to form a second control gate 210 in each trench. The second control gate 210 is separated from the inner walls of the third and fourth trenches by a second gate dielectric layer 209, and the second control gate 210 and the first control gate 206 are separated by the second gate dielectric layer 209. Next, ions are implanted into the epitaxial layer 201 starting from its surface to form a well region 211 in the epitaxial layer 201 near its surface. The well region 211 is located above the first control gate. The implanted ion concentration is 8.0e16cm⁻¹. -3 ~1.36e17 cm -3 Compared to the case where the thickness of the first gate dielectric layer 205 and the second gate dielectric layer 209 are the same, this embodiment of the invention reduces the thickness of the gate dielectric layer in the upper part of the first trench. Therefore, without affecting the lower electric field, the concentration of implanted ions in the upper part of the first control gate, i.e., the well region, can be increased by about 70%. Increasing the ion concentration in the drift region can reduce the drift resistance, thereby reducing the on-resistance. Next, ions are implanted into the well region 211 of the cell region 201A to form source / drain terminals 212 in the well region 211 of the cell region 201A near the surface of the epitaxial layer 201.

[0058] Next, please refer to Figure 6An interlayer dielectric layer 213 is formed on the surface of the epitaxial layer 201. Next, a portion of the interlayer dielectric layer 213, the source / drain terminals 212, and a portion of the well region 211 are etched and filled with a metallic material to form a first contact hole 214 within the cell region 201A. The first contact hole 214 passes through the interlayer dielectric layer 213 and the source / drain terminals 212 and terminates within the well region 211. (This process is repeated three times in the original text.) Simultaneously, a portion of the interlayer dielectric layer 213, a portion of the first control gate 206, a portion of the second control gate 210, and a portion of the second gate dielectric layer 209 are etched and filled with metal material to form a second contact hole 215 within the gate lead-out region 201B. The second contact hole 215 stops at the surfaces of the first control gate 206 and the second control gate 210, connecting the first control gate 206 and the second control gate 210. Since the first control gate 206 of the entire cell region 201A and the entire gate lead-out region 201B are both connected, and the second control gate 210 of the entire cell region 201A and the entire gate lead-out region 201B is also connected, the second contact hole 215 connecting the first control gate 206 and the second control gate 210 allows the first control gate 206 and the second control gate 210 of the entire cell region 201A and the entire gate lead-out region 201B to be connected. Next, a first metal layer 216 and a second metal layer 217 are formed on the surface of the interlayer dielectric layer 213 at intervals. The first metal layer 216 is connected to the first contact hole 214, and the second metal layer 217 is connected to the second contact hole 215.

[0059] The present invention also provides a trench gate MOSFET, comprising: an epitaxial layer including a cell region and a gate lead-out region adjacent to each other; a first trench located in the epitaxial layer within the cell region, and a second trench located in the epitaxial layer within the gate lead-out region; a first gate dielectric layer and a first control gate both located in the first trench and the second trench, the first control gate being separated from the inner walls of both the first trench and the second trench by the first gate dielectric layer; a third trench located on both sides of the upper portion of the first control gate in the cell region, and a fourth trench located on both sides of the upper portion of the first control gate in the gate lead-out region; and a second gate dielectric layer both located in the third trench and the fourth trench. The system comprises a dielectric layer and a second control gate, the second control gate being separated from the inner walls of the third and fourth trenches and the first control gate by a second gate dielectric layer; a well region located in the epitaxial layer near the surface of the epitaxial layer, the well region being located on the upper portion of the first control gate; source and drain terminals located in the well region within the cell region and near the surface of the epitaxial layer; an interlayer dielectric layer located on the surface of the epitaxial layer; a first contact hole located in the cell region, the first contact hole passing through the interlayer dielectric layer and the source and drain terminals and ending in the well region; and a second contact hole located in the gate lead-out region, the second contact hole ending on the surface of the first and second control gates, connecting the first and second control gates. It also includes a first metal layer and a second metal layer located on the surface of the interlayer dielectric layer and spaced apart, the first metal layer communicating with the first contact hole, and the second metal layer communicating with the second control contact hole.

[0060] In summary, the trench gate MOSFET and its formation method provided in this embodiment of the invention include: providing an epitaxial layer, the epitaxial layer including a cell region and a gate lead-out region adjacent to each other; forming a first trench in the epitaxial layer of the cell region, and forming a second trench in the epitaxial layer of the gate lead-out region, the first trench and the second trench being spaced apart; forming a first gate dielectric layer and a first control gate in both the first trench and the second trench, the first control gate being spaced apart from the inner walls of both the first trench and the second trench through the first gate dielectric layer; forming a third trench on both sides of the upper portion of the first control gate in the cell region, and forming a fourth trench on both sides of the upper portion of the first control gate located in the gate lead-out region; forming a second gate dielectric layer in both the third trench and the fourth trench. The invention comprises a gate dielectric layer and a second control gate. The second control gate is separated from the inner walls of the third and fourth trenches and the first control gate by the second gate dielectric layer. The thickness of the second gate dielectric layer is less than that of the first gate dielectric layer. A well region is formed in the epitaxial layer near the surface of the epitaxial layer, and the well region is located in the upper portion of the first control gate. A source / drain terminal is formed in the well region near the surface of the epitaxial layer in the cell region. An interlayer dielectric layer is formed on the surface of the epitaxial layer. A first contact hole is formed in the cell region, passing through the interlayer dielectric layer and the source / drain terminal and ending in the well region. A second contact hole is formed in the gate lead-out region, ending on the surfaces of the first and second control gates, connecting the first and second control gates. This invention increases the thickness of the gate dielectric layer in the lower portion of the first control gate, improving the breakdown voltage. It reduces the thickness of the gate dielectric layer in the upper portion, lowering the on-resistance of the device and improving the device performance.

[0061] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for forming a trench gate MOSFET, characterized in that, include: An epitaxial layer is provided, the epitaxial layer including a cell region and a gate lead-out region disposed adjacently; A first trench is formed in the epitaxial layer of the cell region, and a second trench is formed in the epitaxial layer of the gate lead-out region, wherein the first trench and the second trench are spaced apart. A first gate dielectric layer and a first control gate are formed in both the first trench and the second trench. The first control gate is separated from the inner walls of both the first trench and the second trench by the first gate dielectric layer. A third trench is formed on both sides of the upper portion of the first control gate in the cell region, and a fourth trench is formed on both sides of the upper portion of the first control gate located in the gate lead-out region. A second gate dielectric layer and a second control gate are formed in both the third and fourth trenches. The second control gate is separated from the inner walls of the third and fourth trenches and the first control gate by the second gate dielectric layer. The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer. A well region is formed in the epitaxial layer near the surface of the epitaxial layer, the well region being located on the upper portion of the first control gate; Source and drain terminals are formed in the well region near the surface of the epitaxial layer in the cell region; An interlayer dielectric layer is formed on the surface of the epitaxial layer; A first contact hole is formed in the cell region, the first contact hole passes through the interlayer dielectric layer and the source / drain terminals and stops at the well region, and a second contact hole is formed in the gate lead-out region, the second contact hole stops at the surface of the first control gate and the second control gate, connecting the first control gate and the second control gate.

2. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, A first trench is formed in the epitaxial layer of the cell region, and a second trench is formed in the epitaxial layer of the gate lead-out region, wherein the first trench and the second trench are spaced apart by: A hard mask layer is formed on the surface of the epitaxial layer; Etch a portion of the hard mask layer and a portion of the epitaxial layer to form a first trench in the epitaxial layer of the cell region and a second trench in the epitaxial layer of the gate lead-out region; Remove the hard mask layer.

3. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, The thickness of the first gate dielectric layer is 600 angstroms to 3000 angstroms.

4. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, The thickness of the second gate dielectric layer is 150 angstroms to 500 angstroms.

5. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, Ions are implanted into the epitaxial layer to form a trap region within the epitaxial layer near the surface of the epitaxial layer.

6. The method for forming a trench gate MOSFET as described in claim 5, characterized in that, The concentration of implanted ions was 8.0e16cm. -3 ~1.36e17 cm -3 .

7. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, Ions are injected into the well region of the cell region to form source / drain terminals in the well region of the cell region near the surface of the epitaxial layer.

8. The method for forming a trench gate MOSFET as described in claim 1, characterized in that, Also includes: A first metal layer and a second metal layer are formed at intervals on the surface of the interlayer dielectric layer. The first metal layer is connected to a first contact hole, and the second metal layer is connected to a second contact hole.

9. A trench gate MOSFET formed using the method for forming a trench gate MOSFET according to any one of claims 1 to 8, characterized in that, include: Epitaxial layer, the epitaxial layer including adjacent cell regions and gate lead-out regions; A first trench located in the epitaxial layer of the cell region, and a second trench located in the epitaxial layer of the gate lead-out region; The first gate dielectric layer and the first control gate are both located in the first trench and the second trench, and the first control gate is separated from the inner walls of the first trench and the second trench by the first gate dielectric layer. The third trench is located on both sides of the upper portion of the first control gate in the cell region, and the fourth trench is located on both sides of the upper portion of the first control gate in the gate lead-out region. The second gate dielectric layer and the second control gate are both located within the third trench and the fourth trench. The second control gate is separated from the inner walls of the third trench and the fourth trench and the first control gate by the second gate dielectric layer. A well region located within the epitaxial layer near the surface of the epitaxial layer, the well region being located on the upper portion of the first control gate; The source / drain terminals are located in the well region within the cell region and close to the surface of the epitaxial layer; Interlayer dielectric layer located on the surface of the epitaxial layer; A first contact hole is located within the cell region, passing through the interlayer dielectric layer and the source / drain terminals and ending in the well region. A second contact hole is located within the gate lead-out region, ending on the surfaces of the first control gate and the second control gate, thus connecting the first control gate and the second control gate.

10. The trench gate MOSFET as claimed in claim 9, characterized in that, Also includes: A first metal layer and a second metal layer are located on the surface of the interlayer dielectric layer and are spaced apart. The first metal layer is connected to a first contact hole, and the second metal layer is connected to a second control contact hole.

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