A method and device for LDPC iterative decoding based on cross-layer sensing and system timing

Abstract

The application provides an LDPC iterative decoding method and device based on cross-layer sensing and system timing, and belongs to the technical field of wireless communication. The total time length of a current OFDM data packet and the total number of LDPC code blocks contained are obtained, and the core parameters of LDPC decoding are preset. Based on a system timing sensing mechanism, the real-time available time margin of the current LDPC code block is calculated in combination with the synchronization information of the OFDM data packet, the real-time state of the memory and the protocol timing constraint. The decoding state of the MAC layer data packet to which the current LDPC code block belongs is determined based on a cross-layer sensing mechanism, the real-time available time margin obtained is combined, the adaptive iteration number of the current LDPC code block is dynamically calculated in different scenes, and LDPC iterative decoding is performed. Therefore, through the fusion of the cross-layer sensing mechanism and the receiver system timing sensing mechanism, the fine and dynamic scheduling of iteration resources is realized, and the high-speed transmission requirement of the 802.11 protocol is adapted.

Description

Technical Field

[0001] This application belongs to the field of wireless communication technology, and specifically relates to an LDPC iterative decoding method and apparatus based on cross-layer sensing and system timing. Background Technology

[0002] With the evolution of the IEEE 802.11 protocol to Wi-Fi 6 / Wi-Fi 7 and even the future Wi-Fi 8 standard, its physical layer transmission rate has seen a leapfrog increase. For example, Wi-Fi 7 supports 4096-QAM high-order modulation, 320MHz channel bandwidth, and up to 16 spatial streams, with a theoretical peak rate of 46.1Gbps. To ensure transmission reliability at such high speeds, since the Wi-Fi 5 standard, Low-Density Parity-Check (LDPC) codes, due to their excellent performance approaching the Shannon limit, have become a mandatory channel coding scheme. However, LDPC decoders, especially their core iterative decoding process, are among the most computationally complex, power-consuming, and area-intensive modules in Wi-Fi chips. Traditional LDPC decoding generally uses sum-product algorithms or minimum-sum algorithms, and ensures error correction performance through a fixed number of iterations (usually set to 7 to 12). This fixed-iteration strategy poses a severe hardware implementation challenge in high-throughput Wi-Fi 7 / 8 scenarios. (1) The contradiction between high throughput requirements and fixed timing: In order to meet the throughput requirements specified in the standard, the decoding time window allocated to each LDPC code block is extremely limited. Taking the full configuration mode of Wi-Fi 7 as an example, nearly 400 LDPC code blocks need to be processed in a single symbol period, resulting in an average decoding time of only about 35ns (nanoseconds) for each code block. If 7 iterations are forced to be completed, each iteration must be completed within 5ns, which directly forces designers to adopt higher clock frequencies or larger parallel computing architectures. (2) Huge hardware overhead and power consumption: The above-mentioned high frequency and high parallelism implementation method results in the LDPC decoding module accounting for 1 / 4 to 1 / 3 of the area in the physical layer chip, and the power consumption in the receiving mode is even close to 50%, which has become the core bottleneck restricting the miniaturization and low power consumption of terminal devices.

[0003] Existing optimizations of LDPC primarily focus on minor improvements at the algorithm level (such as approximate calculations of the check node update algorithm). However, since the core LDPC algorithm is quite mature, the performance gains from such optimizations are increasingly limited and cannot fundamentally solve the systemic resource utilization problem caused by the fixed iteration strategy. Existing fixed iteration strategies suffer from the following two fundamental flaws:

[0004] At the packet level, the system fails to adapt to the packet characteristics of the upper-layer protocol (MAC). In practical communication systems, the packet length generated by upper-layer protocols (such as TCP / IP / UDP) is usually relatively fixed. The upper-layer packet of the 802.11 protocol corresponds to the MAC layer packet. Taking a typical 1680-byte MAC layer packet as an example, it will be divided into about 10 to 20 more LDPC code blocks for encoding and transmission. From the perspective of system reliability, if the decoding of one LDPC code block fails, the entire MAC layer packet will be declared a transmission failure, and the remaining successfully decoded LDPC code blocks will also become ineffective. The fixed iteration strategy ignores this "one mistake, all mistakes" packet-level correlation characteristic, allocating fixed and sufficient iteration resources to all code blocks within a single packet. This results in a pure waste of resources for iterating subsequent code blocks of the packet after the decoding of the first code block fails. At the code block level, the system fails to utilize the idle time slots of the data processing pipeline for global optimization. The fixed strategy rigidly separates the processing timing between different LDPC code blocks and even different data packets. Memory buffer structures (such as time-domain or frequency-domain memory) in Wi-Fi receivers create variable time margins for the system. Traditional methods fail to treat the entire decoding process as a dynamically schedulable whole in time, making it impossible to achieve iterative resource scheduling across LDPC code blocks and across layers. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide an LDPC iterative decoding method and apparatus based on cross-layer sensing and system timing, which can realize fine-grained and dynamic scheduling of iterative resources and adapt to the high-speed transmission requirements of the 802.11 protocol.

[0006] In a first aspect, this application provides an LDPC iterative decoding method based on cross-layer sensing and system timing, the method comprising the following steps:

[0007] Obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding;

[0008] Based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory and the protocol timing constraints, the real-time available time margin of the current LDPC code block is calculated.

[0009] Based on the cross-layer perception mechanism, the decoding status of the MAC layer data packet to which the current LDPC code block belongs is determined. Combined with the obtained real-time available time margin, the number of iterations for the current LDPC code block is dynamically calculated according to the scenario, and LDPC iterative decoding is performed.

[0010] In some embodiments, the core parameters of LDPC decoding include the maximum number of iterations, the minimum number of iterations, the system's expected average number of iterations, resource fine-tuning parameters, and the time consumed in a single LDPC iteration.

[0011] In some embodiments, the calculation of the real-time available time margin of the current LDPC code block based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory, and protocol timing constraints, includes the following steps:

[0012] The arrival time of the maximum energy path component within an OFDM data packet is located using a synchronization algorithm and used as a time reference.

[0013] Calculate the elapsed processing time from the time base to the current time, and combine it with the total time length of the OFDM data packet to obtain the remaining packet time when processing the current LDPC code block;

[0014] Based on the real-time monitoring of the data backlog status of all buffer memories in the receiver system, the available buffer time is determined.

[0015] Based on the remaining packet time, available memory buffer time, fixed delay, and protocol response time margin, calculate the real-time available time margin of the current LDPC code block and determine the latest completion time for decoding the code block.

[0016] In some embodiments, the number of adaptation iterations is dynamically calculated as follows, including the following steps:

[0017] Extract the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs, and determine whether the MAC layer data packet has been marked as decoding failure;

[0018] If the MAC layer data packet has been marked as decoding failure, the iterative decoding process of the current LDPC code block is terminated, and the iteration time resources saved by this termination are calculated and carried over to the system iteration resource pool for subsequent LDPC decoding of MAC layer data packets that have not been marked as decoding failure.

[0019] If the MAC layer data packet is not marked as decoding failure, the final iteration number of the current LDPC code block is dynamically calculated according to the code block position characteristics, real-time available time margin and preset core parameters, depending on the scenario.

[0020] LDPC iterative decoding is performed on the current LDPC code block according to the final iteration number. The checksum status and checksum improvement rate after each iteration are monitored in real time to determine the decoding result. The decoding status flag of the MAC layer data packet to which the current LDPC code block belongs is updated according to the decoding result. If the decoding fails, the MAC layer data packet is marked as decoding failed. If the decoding is successful in advance, the remaining iteration time resources are carried over to the subsequent LDPC code block of the MAC layer data packet.

[0021] In some embodiments, the dynamic calculation of the final iteration number of the current LDPC code block under different scenarios includes the following steps:

[0022] If the current LDPC block is the first block of its MAC layer data packet and the last LDPC block of its OFDM data packet, the final number of iterations is:

[0023]

[0024] If the current LDPC block is the first block of its MAC layer data packet and not the last LDPC block of the OFDM data packet, the final number of iterations is:

[0025]

[0026] in, For LDPC code block index; This represents the total number of LDPC code blocks contained in the current OFDM data packet; The maximum number of iterations; , , , The maximum number of iterations, minimum number of iterations, expected average number of iterations, and resource fine-tuning parameters are preset respectively.

[0027] In some embodiments, the maximum number of iterations is calculated using the following formula:

[0028]

[0029] in, This provides a margin of time for real-time availability. This is the preset time for a single LDPC iteration.

[0030] In some embodiments, the decoding result is determined as follows:

[0031] If the checksum is zero after a certain iteration, the decoding is considered successful, and the iteration is terminated.

[0032] If the checksum improvement rate is lower than the preset convergence threshold during the iteration process, or if the checksum is not zero when the number of iterations reaches the maximum number of iterations, the decoding is deemed to have failed.

[0033] Secondly, this application also provides an LDPC iterative decoding device based on cross-layer sensing and system timing, the device comprising:

[0034] The parameter initialization module is used to obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding.

[0035] The time margin calculation module is used to calculate the real-time available time margin of the current LDPC code block based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory, and the protocol timing constraints.

[0036] The iteration count calculation module is used to determine the decoding status of the MAC layer data packet to which the current LDPC code block belongs based on the cross-layer perception mechanism. Combined with the obtained real-time available time margin, it dynamically calculates the appropriate iteration count for the current LDPC code block according to the scenario and performs LDPC iterative decoding.

[0037] Thirdly, this application also provides an electronic device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the steps of the LDPC iterative decoding method based on cross-layer sensing and system timing described in any of the first aspects are executed.

[0038] Fourthly, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the LDPC iterative decoding method based on cross-layer sensing and system timing as described in any one of the first aspects.

[0039] This application describes an LDPC iterative decoding method and apparatus based on cross-layer perception and system timing. It obtains the total duration and total number of LDPC code blocks contained in the current OFDM data packet, as well as preset core parameters for LDPC decoding. Based on a system timing perception mechanism, and combining the synchronization information of the OFDM data packet, the real-time status of the memory, and protocol timing constraints, it calculates the real-time available time margin of the current LDPC code block. Based on the cross-layer perception mechanism, it determines the decoding status of the MAC layer data packet to which the current LDPC code block belongs. Combining the obtained real-time available time margin, it dynamically calculates the appropriate number of iterations for the current LDPC code block according to different scenarios and performs LDPC iterative decoding. By integrating the MAC layer-physical layer cross-layer sensing mechanism with the receiver system timing sensing mechanism, dynamic allocation of LDPC iterations, rapid termination of invalid iterations, and cross-code block and cross-MAC packet scheduling of iteration resources are achieved. This solves the problems of resource waste, layer fragmentation, and timing mismatch in traditional fixed iteration methods. While ensuring decoding accuracy, it reduces the consumption of invalid system resources, improves resource utilization, and adapts to the low latency and high throughput transmission requirements of high-speed wireless LANs. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart of the LDPC iterative decoding method based on cross-layer sensing and system timing described in an embodiment of this application is shown;

[0042] Figure 2 A schematic diagram of the architecture of the receiver system according to an embodiment of this application is shown;

[0043] Figure 3 This document illustrates a flowchart of the calculation of the real-time available time margin of the current LDPC code block as described in an embodiment of this application.

[0044] Figure 4 A flowchart illustrating the dynamic calculation of the number of adaptation iterations as described in an embodiment of this application is shown;

[0045] Figure 5 This diagram illustrates the distribution of the number of iterations required for successful decoding in simulation testing according to an embodiment of this application.

[0046] Figure 6 This paper shows a schematic diagram of the structure of the LDPC iterative decoding device based on cross-layer sensing and system timing described in an embodiment of this application;

[0047] Figure 7 A schematic diagram of the structure of the electronic device described in an embodiment of this application is shown. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0049] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0050] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0051] In view of the technical problems raised in the background art, this application provides an LDPC iterative decoding method and apparatus based on cross-layer sensing and system timing, which can realize fine-grained and dynamic scheduling of iterative resources and adapt to the high-speed transmission requirements of the 802.11 protocol.

[0052] See the instruction manual appendix Figure 1 This application provides an LDPC iterative decoding method based on cross-layer sensing and system timing, the method comprising the following steps:

[0053] S1. Obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding;

[0054] S2. Based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory and the protocol timing constraints, calculate the real-time available time margin of the current LDPC code block.

[0055] S3. Based on the cross-layer perception mechanism, determine the decoding status of the MAC layer data packet to which the current LDPC code block belongs. Combined with the obtained real-time available time margin, dynamically calculate the number of iterations for the current LDPC code block according to the scenario and perform LDPC iterative decoding.

[0056] To clearly understand the technical solutions of the embodiments of the present invention, an exemplary application scenario can be provided first. This application provides an LDPC iterative decoding method based on cross-layer sensing and system timing, applied to a receiver system. See the appendix to the specification. Figure 2 The receiver system includes the following modules connected in sequence:

[0057] RF Front-End and Filters: The radio signal received from the antenna is processed by the RF front-end and digital filters. The signal is filtered and amplified to generate a time-domain data stream. This process involves time delays, including digital processing delays, filter delays, and RF front-end delays. This time delay is defined as T_delay and is typically less than 2µs.

[0058] Time-domain memory: Used to cache time-domain data to meet the FFT operation requirements of OFDM symbol length. It also supports time synchronization and frequency synchronization algorithms.

[0059] Fast Fourier Transform (FFT) module: After removing the OFDM time-domain cyclic prefix, a Fast Fourier Transform is performed on each symbol to obtain the frequency domain data of each symbol.

[0060] Frequency domain memory: Stores the frequency domain data of the FFT output. For system performance considerations, channel estimation and phase tracking across symbols are generally required, for example, using channel information from the later symbol to correct the earlier symbol. Therefore, frequency domain data needs to be cached.

[0061] Phase-locked loop (PLL) phase compensation and equalization module: For STBC-encoded data packets, joint equalization of two consecutive frequency domain symbols is required; for non-STBC packets, single-symbol equalization is performed. The equalized data is stored in the equalization memory. This memory is actually unnecessary; the same effect can be achieved by increasing the size of the subsequent LLR Init memory. This is because this memory is normally smaller than the LLR Init Memory, since in 4096QAM modulation, a single frequency domain data packet contains a maximum of 12 bits, and each bit contains LLR information; therefore, the LLR module's Init memory needs to store more bits.

[0062] Log-Likelihood Ratio (LLR) Calculation: Calculates the soft information value of each bit based on the equalization result.

[0063] LLR preprocessing: The LLR initial value is generated by performing the inverse operation based on the LDPC encoding parameters (repetition, puncturing, shortening). Specifically, according to the LDPC encoding process specified in the 802.11 protocol, the LDPC receiver operation is exactly the reverse; the receiver outputs the LLR. Anti-repetition operation: The LLR values ​​of the repeated transmitted bits are summed and combined. Anti-puncturing operation: Zero-valued LLRs are padded at punctured positions. Anti-shortening operation: The maximum confidence LLR value is padded at shortened positions. Through the above processing, the initial LLR value LLRInit, conforming to the decoder input format, is obtained.

[0064] LLR Initial Memory: Stores the initial LLR values ​​to be fed into the LDPC decoder. The existence of this memory allows the decoder to operate in a pipelined manner: while the decoder is processing the current code block, the input data for the next code block is already ready in this memory.

[0065] LDPC decoding control and execution module: includes:

[0066] Iteration count calculation unit: dynamically calculates the available iteration time budget T_decode(k) for each code block.

[0067] Decoding: Supports multi-core parallel architecture and is subject to unified scheduling and management.

[0068] Cross-layer scheduler: Implements bidirectional scheduling at the MAC packet level and code block level.

[0069] The following section focuses on explaining the data processing flow.

[0070] Step S1 mainly involves obtaining the OFDM data packet to be decoded and the core parameters of the preset LDPC decoding, providing data support and rule basis for subsequent time margin calculation and dynamic allocation of iteration number.

[0071] Specifically, the signaling fields (such as preamble and frame control fields) of OFDM data packets contain basic structural information about the data packets. The demodulation process restores this field data through synchronization and demodulation algorithms, directly parsing to obtain the total time length T and the total number of LDPC code blocks N. This clarifies the time boundaries and data unit size of the decoding operation, providing a global dimension reference for subsequent timing calculations and resource allocation.

[0072] The preset core decoding parameters include the maximum number of iterations for a single LDPC code block. Minimum number of iterations The system's expected average number of iterations Resource fine-tuning parameters and the time consumption of a single LDPC iteration This sets boundaries for calculating subsequent iterations, avoiding the waste of system resources due to unlimited allocation of iterations or decoding failures due to insufficient iterations.

[0073] in, This is the maximum allowed number of iterations for a single LDPC code block (e.g., 20 times). Because LDPC decoding has a bottleneck, too many iterations do not improve performance. Therefore, if the iteration exceeds the current threshold, we need to stop the current LDPC block iteration to save valuable iteration time for subsequent LDPC blocks. The minimum number of iterations (e.g., 2) required for a single LDPC code block. The system design aims to determine the expected average number of iterations (e.g., 4.5). This number determines the complexity and power consumption of the LDPC decoding module of the entire system. The LDPC decoding module is designed based on this parameter. This is to reserve the number of undecoded LDPC iterations (e.g., 0.5 times) for fine-tuning the resources reserved for subsequent code blocks, thereby increasing the system's robustness. The time required for one LDPC iteration is determined by the system design. For example, in a fully equipped Wi-Fi 7 system, nearly 400 LDPC blocks need to be processed within a single symbol period, resulting in an average decoding time of only about 35 ns (nanoseconds) for each block. If the average number of iterations... If it's 4.5 times, then the iteration time is... =35ns / 4.5=7.8ns.

[0074] It is worth noting that the above five parameters can be decimals. This is because LDPC decoding is typically iterated line by line, and a code block consists of multiple lines (e.g., 4 to 20 lines), for example... = 4.5 means that each LDPC block iterates an average of 4.5 times. For a 4-line LDPC code block, the total number of iterations is 4.5. 4 = 21 lines.

[0075] In addition, the global parameters (T, N) and preset parameters obtained above are stored in a hierarchical association according to the “OFDM data packet - code block”. When processing the k-th LDPC code block, the corresponding T, N and preset parameters can be quickly retrieved to avoid duplicate calculations and data conflicts.

[0076] Step S2 mainly involves calculating the time margin, quantifying the remaining time resources available for LDPC decoding, providing a scientific basis for the dynamic allocation of subsequent iterations, avoiding decoding timeouts or memory overflows due to insufficient time resources, and maximizing the utilization of idle time.

[0077] For details, please refer to the instruction manual appendix. Figure 3 The calculation of the real-time available time margin of the current LDPC code block based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory, and protocol timing constraints, includes the following steps:

[0078] S201. Locate the arrival time of the maximum energy path component within the OFDM data packet using a synchronization algorithm, and use it as a time reference;

[0079] S202. Calculate the elapsed processing time from the time base to the current time, and combine it with the total time length of the OFDM data packet to obtain the remaining packet time when processing the current LDPC code block.

[0080] S203. Based on the data backlog status of all buffer memories in the receiver system under real-time monitoring, determine the available buffer time of the memory;

[0081] S204. Based on the remaining packet time, available memory buffer time, fixed delay, and protocol response time margin, calculate the real-time available time margin of the current LDPC code block and determine the latest completion time for decoding the code block.

[0082] In step S201, due to multipath effects in OFDM data packet transmission in the wireless channel (the same signal arrives at the receiver via different paths), there is a deviation in signal arrival time. Directly using the data packet reception start time as the reference would cause timing calculation errors. Therefore, this application uses a synchronization algorithm to locate the arrival time of the component with the maximum energy path within the OFDM data packet, and uses this time point as the reference for all subsequent time calculations. Synchronization is achieved using the STF, LTF, or DATA fields in the OFDM data packet preamble. This eliminates the impact of multipath interference on timing calculations, laying the foundation for accurate calculation of the remaining packet time and elapsed time.

[0083] In step S202, based on the reference time point determined in step S201, the elapsed time from the reference time to the current processing time of the k-th LDPC code block is calculated. Combined with the total time length T of the acquired OFDM data packets, the formula is used to... Calculate the remaining packet time when processing the k-th LDPC code block. Where k is the LDPC code block index, with a value ranging from 1 to N. This clarifies the upper limit of the time constraint for the decoding task, ensuring that subsequent iterations of resource allocation do not exceed the overall timing requirements of the data packets, and avoiding data transmission failure due to timeouts.

[0084] In step S203, due to the limited capacity of the receiver's buffer memory, if the decoding speed is too slow, newly received data will continuously accumulate in the memory, potentially leading to memory overflow and data loss. Therefore, it is necessary to quantify the remaining capacity of the memory and convert it into a time resource indicator that can be used for decoding, avoiding memory overflow due to excessive decoding time and ensuring the smooth operation of the data processing pipeline. In this application, the data accumulation status of all buffer memories (including time-domain memory, frequency-domain memory, LLR Init memory, etc.) in the receiver's data processing pipeline is monitored in real time, and the data accumulation status is determined by formula... The available cache time of the memory is calculated; where, This indicates the time corresponding to the maximum amount of cached data across all buffers. This represents the time corresponding to the total amount of data currently cached in all buffer memories when processing the k-th LDPC code block.

[0085] In step S204, considering the RF filtering delay (typically 2µs) and the response time margin required by the protocol (typically 15µs), it is finally determined that the system must be able to [operate at the latest]. The decoding of all remaining (Nk) LDPC code blocks is completed before the iteration time. Where:

[0086]

[0087] This represents the total real-time available time margin that the system can allocate to the remaining (Nk) code blocks when processing the kth LDPC code block; This represents the total delay of the RF filtering delay and the protocol response; This indicates the amount of time adjustment.

[0088] Maximum number of iterations: .

[0089] Step S3 mainly involves calculating the number of iterations. Combining the cross-layer characteristics of the MAC layer with the system timing margin, iterative resources are precisely allocated to each LDPC code block. This ensures the decoding success rate while avoiding resource waste, ultimately achieving a balance between performance, power consumption, and complexity.

[0090] For details, please refer to the instruction manual appendix. Figure 4 The number of iterations for adaptation is dynamically calculated as follows, including the following steps:

[0091] S301. Extract the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs, and determine whether the MAC layer data packet has been marked as decoding failure;

[0092] S302. If the MAC layer data packet has been marked as decoding failure, terminate the iterative decoding process of the current LDPC code block, and calculate the iteration time resources saved by this termination and transfer them to the system iteration resource pool for subsequent LDPC decoding of MAC layer data packets that have not been marked as decoding failure.

[0093] S303. If the MAC layer data packet is not marked as decoding failure, the final iteration number of the current LDPC code block is dynamically calculated according to the code block position characteristics, real-time available time margin and preset core parameters, depending on the scenario.

[0094] S304. Perform LDPC iterative decoding on the current LDPC code block according to the final iteration number, monitor the checksum status and checksum improvement rate after each iteration in real time, and determine the decoding result; and update the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs according to the decoding result; wherein, if the decoding fails, the MAC layer data packet is marked as decoding failed; if the decoding is successful in advance, the remaining iteration time resources are carried over to the subsequent LDPC code block of the MAC layer data packet.

[0095] In step S301, the decoding status flag of the upper-layer data packet (such as a MAC layer data packet) to which the current k-th LDPC code block belongs is retrieved to determine whether the upper-layer data packet has been marked as "decoding failed". This quickly eliminates failed code blocks, avoids invalid iterations on LDPC code blocks whose data packets have failed, prevents resource waste from the source, and provides a prerequisite for subsequent resource transfer.

[0096] In step S302, if it is determined that the MAC layer data packet to which the current LDPC code block belongs has been marked as decoding failure, the iterative decoding process of the current code block is immediately terminated, and no iteration resources are allocated. Simultaneously, the total iteration time resources saved by prematurely terminating the iteration of this code block and the remaining unprocessed code blocks in the same packet are calculated and dynamically reallocated to the LDPC code blocks corresponding to subsequent unmarked MAC layer data packets. Wherein, the total saved iteration resources = (number of remaining unprocessed code blocks in the same packet × average number of iterations) (+Number of iterations not yet executed for the current code block) × Single iteration time This improves the overall resource utilization of the system and solves the problem of package-level resource waste in traditional fixed iteration strategies.

[0097] In step S303, if it is determined that the MAC layer data packet to which the current LDPC code block belongs is not marked as a decoding failure, then the final iteration number of the code block is dynamically calculated by combining the code block location characteristics, the system's real-time available time margin, and preset parameters, according to the following specific rules:

[0098] Scenario 1: If the current LDPC block is the first block of its MAC layer data packet or the MAC frame length is not correctly parsed, and it is the last LDPC block of an OFDM data packet, the final number of iterations is:

[0099]

[0100] Scenario 2: If the current LDPC block is the first block of its MAC layer data packet or the MAC frame length is not correctly parsed, and it is not the last LDPC block of the OFDM data packet, the final number of iterations is:

[0101]

[0102] in, For LDPC code block index; This represents the total number of LDPC code blocks contained in the current OFDM data packet; The maximum number of iterations; , , , The maximum number of iterations, minimum number of iterations, expected average number of iterations, and resource fine-tuning parameters are preset respectively.

[0103] Scenario 3: If the current LDPC block is not the first block of the MAC layer data packet, but the last LDPC block of the OFDM data packet, and the MAC layer data has been marked as successfully decoded, the calculation is performed according to Scenario 1.

[0104] Scenario 4: If the current LDPC block is not the first block of the MAC layer data packet, nor the last LDPC block of the OFDM data packet, and the MAC layer data has been marked as successfully decoded, then the calculation is performed according to Scenario 2.

[0105] This enables iterative resource allocation with a one-code-one-policy approach, allowing code blocks with good channel conditions to undergo fewer iterations (saving resources) and code blocks with poor channel conditions to undergo more iterations (ensuring performance). At the same time, it strictly adheres to system timing margin constraints, avoiding decoding timeouts or memory overflows, thus solving the shortcomings of traditional fixed iteration with a one-size-fits-all approach.

[0106] In step S304, the final number of iterations calculated in step S303 is used. Perform iterative decoding on the current LDPC code block; during the iteration process, monitor the checksum status of the code block in real time. If any of the following convergence conditions are met, terminate the iteration immediately, record the saved iteration time resources and transfer them to subsequent code blocks: (1) The checksum is zero after a certain iteration, indicating that the code block has been correctly decoded; (2) The checksum improvement rate of multiple consecutive iterations is lower than the preset convergence threshold, indicating that the code block cannot converge and is judged as decoding failure. Wherein, the saved iteration time = (final iteration number) - Actual number of iterations) × time per iteration .

[0107] Thus, through steps S301-S304, a deep fusion of cross-layer perception (MAC packet-level state) and system timing perception (time margin, memory state) is achieved, which not only solves the resource waste problem of traditional fixed iteration, but also balances decoding performance and hardware overhead through dynamic number allocation.

[0108] Furthermore, to verify the technical effectiveness of this application, simulation tests were conducted on the MCS13 modulation and coding scheme in the Wi-Fi 7 standard under an AWGN channel. The test conditions were set near the receiver sensitivity critical point to evaluate the algorithm's performance under the worst channel conditions. Simulation results are attached to the specification. Figure 5 As shown, it statistically illustrates the distribution of the number of iterations required for successful decoding.

[0109] Simulation data analysis shows that under the critical conditions, the average number of iterations required for successful decoding is only 5. More than 90% of code blocks can be decoded in 7 iterations or fewer, while the observed maximum number of iterations is 13.

[0110] The traditional approach suffers from resource waste: If the fixed iteration count strategy of existing technologies is adopted, the maximum number of iterations must be set to 13 to ensure decoding reliability. In this case, the average computational complexity of the system is 13 / 5 = 2.6 times that of the average 5 iterations achieved in this application. Even with a relatively conservative fixed 7 iteration count scheme, its average complexity is still 7 / 5 = 1.4 times that of this invention.

[0111] Based on the above data, this application provides an LDPC iterative decoding method based on cross-layer awareness and system timing. Through the proposed system timing awareness and MAC packet-level scheduling coordination mechanism, the following quantifiable performance improvements are achieved:

[0112] Significant power consumption optimization: This application dynamically stabilizes the average iteration requirement of the LDPC decoding module at approximately 4.5 iterations (an additional 0.5 iterations can be saved through MAC packet-level scheduling). Compared to the traditional fixed 13 iteration scheme, the computational complexity is reduced to approximately 34.6%, equivalent to saving approximately 65.4% of the iteration computational resources. Compared to the traditional fixed 7 iteration scheme, it also achieves a complexity reduction of approximately 1 - 4.5 / 7 = 36%.

[0113] Significant reduction in system-level power consumption: In a typical Wi-Fi receiver, the LDPC decoding module is the core of power consumption, accounting for up to half of the total power consumption of the entire receiver link. Therefore, the power consumption optimization of the LDPC decoding module in this application will directly bring system-level benefits. Calculations show that the solution in this application can reduce the total power consumption of the entire Wi-Fi receiver by approximately 18%.

[0114] Optimal balance between performance and complexity: This application does not simply reduce the number of iterations, but rather uses intelligent scheduling to reallocate the saved resources to code blocks with poor channel conditions. This ensures that while significantly reducing average complexity, the overall frame error rate performance remains comparable to or even better than that of high-complexity fixed-iteration schemes.

[0115] Based on the same inventive concept, this application also provides an LDPC iterative decoding device based on cross-layer sensing and system timing. Since the principle of the device in this application is similar to the LDPC iterative decoding method based on cross-layer sensing and system timing described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0116] As per the instruction manual Figure 6 As shown in the figure, this application embodiment also provides an LDPC iterative decoding device based on cross-layer sensing and system timing, the device comprising:

[0117] The parameter initialization module 601 is used to obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding.

[0118] The time margin calculation module 602 is used to calculate the real-time available time margin of the current LDPC code block based on the system timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory and the protocol timing constraints.

[0119] The iteration count calculation module 603 is used to determine the decoding status of the MAC layer data packet to which the current LDPC code block belongs based on the cross-layer perception mechanism, and combined with the obtained real-time available time margin, dynamically calculate the appropriate iteration count for the current LDPC code block according to the scenario and perform LDPC iterative decoding.

[0120] In some embodiments, the core parameters of LDPC decoding include the maximum number of iterations, the minimum number of iterations, the system's expected average number of iterations, resource fine-tuning parameters, and the time consumed in a single LDPC iteration.

[0121] In some embodiments, the time margin calculation module 602, based on the system timing awareness mechanism and combined with the synchronization information of OFDM data packets, the real-time status of the memory, and protocol timing constraints, calculates the real-time available time margin of the current LDPC code block. This includes: locating the arrival time of the maximum energy path component within the OFDM data packet using a synchronization algorithm and using it as a time reference; calculating the elapsed processing time from the time reference to the current time, and combining this with the total time length of the OFDM data packet to obtain the remaining packet time for processing the current LDPC code block; determining the available buffer time of the memory based on the data backlog status of all buffer memories in the receiver system under real-time monitoring; and calculating the real-time available time margin of the current LDPC code block based on the remaining packet time, the available buffer time of the memory, the fixed delay, and the protocol response time margin, and determining the latest completion time for decoding the code block.

[0122] In some embodiments, the iteration count calculation module 603 dynamically calculates the adapted iteration count, including: extracting the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs, and determining whether the MAC layer data packet has been marked as decoding failure; if the MAC layer data packet has been marked as decoding failure, terminating the iterative decoding process of the current LDPC code block, and calculating the iteration time resources saved by this termination and transferring them to the system iteration resource pool for subsequent LDPC decoding of MAC layer data packets that have not been marked as decoding failure; if the MAC layer data packet has not been marked as decoding failure, combining the code block Based on location characteristics, real-time available time margin, and preset core parameters, the final iteration number of the current LDPC code block is dynamically calculated according to the scenario. LDPC iterative decoding is performed on the current LDPC code block according to the final iteration number, and the checksum status and checksum improvement rate are monitored in real time after each iteration to determine the decoding result. Furthermore, the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs is updated according to the decoding result. Specifically, if decoding fails, the MAC layer data packet is marked as decoded failed; if decoding is successful ahead of schedule, the remaining iteration time resources are carried over to subsequent LDPC code blocks of the MAC layer data packet. The dynamic calculation of the final iteration number of the current LDPC code block according to the scenario includes:

[0123] If the current LDPC block is the first block of its MAC layer data packet and the last LDPC block of its OFDM data packet, the final number of iterations is:

[0124]

[0125]

[0126] If the current LDPC block is the first block of its MAC layer data packet and not the last LDPC block of the OFDM data packet, the final number of iterations is:

[0127]

[0128] in, For LDPC code block index; This represents the total number of LDPC code blocks contained in the current OFDM data packet; The maximum number of iterations; , , , The maximum number of iterations, minimum number of iterations, expected average number of iterations, and resource fine-tuning parameters are preset respectively; This provides a margin of time for real-time availability. This is the preset time for a single LDPC iteration.

[0129] In some embodiments, the iteration count calculation module 603 determines the decoding result by: if the checksum is zero after a certain iteration, the decoding is determined to be successful and the iteration is terminated; if the checksum improvement rate is lower than a preset convergence threshold during the iteration process, or the checksum is not zero when the iteration count reaches the maximum iteration count, the decoding is determined to be unsuccessful.

[0130] The LDPC iterative decoding device based on cross-layer perception and system timing described in this application obtains the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of LDPC decoding, through a parameter initialization module; calculates the real-time available time margin of the current LDPC code block based on the system timing perception mechanism, combined with the synchronization information of the OFDM data packet, the real-time status of the memory, and the protocol timing constraints through a time margin calculation module; and determines the decoding status of the MAC layer data packet to which the current LDPC code block belongs based on the cross-layer perception mechanism through an iteration count calculation module, and dynamically calculates the appropriate number of iterations for the current LDPC code block according to different scenarios and performs LDPC iterative decoding based on the obtained real-time available time margin. By integrating the MAC layer-physical layer cross-layer sensing mechanism with the receiver system timing sensing mechanism, dynamic allocation of LDPC iterations, rapid termination of invalid iterations, and cross-code block and cross-MAC packet scheduling of iteration resources are achieved. This solves the problems of resource waste, layer fragmentation, and timing mismatch in traditional fixed iteration methods. While ensuring decoding accuracy, it reduces the consumption of invalid system resources, improves resource utilization, and adapts to the low latency and high throughput transmission requirements of high-speed wireless LANs.

[0131] Based on the same concept of the present invention, as shown in the appendix to the specification. Figure 7 As shown in the figure, an embodiment of this application provides the structure of an electronic device 700, which includes: at least one processor 701, at least one network interface 704 or other user interface 703, a memory 705, and at least one communication bus 702. The communication bus 702 is used to realize the connection and communication between these components. The electronic device 700 may optionally include a user interface 703, including a display (e.g., touch screen, LCD, CRT, holographic imaging, or projector, etc.), a keyboard, or a clicking device (e.g., mouse, trackball, touchpad, or touch screen, etc.).

[0132] Memory 705 may include read-only memory and random access memory, and provides instructions and data to processor 701. A portion of memory 705 may also include non-volatile random access memory (NVRAM).

[0133] In some implementations, memory 705 stores executable modules or data structures, or subsets thereof, or extended sets thereof:

[0134] The 7051 operating system contains various system programs used to implement various basic business functions and handle hardware-based tasks.

[0135] Application module 7052 contains various applications, such as desktop (launcher), media player (MediaPlayer), browser (Browser), etc., to implement various application services.

[0136] In this embodiment of the application, by calling the program or instructions stored in the memory 705, the processor 701 is used to execute steps such as those of an LDPC iterative decoding method based on cross-layer sensing and system timing.

[0137] This application also provides a computer-readable storage medium storing a computer program that is executed by a processor, such as steps in an LDPC iterative decoding method based on cross-layer sensing and system timing.

[0138] Specifically, the storage medium can be a general-purpose storage medium, such as a portable disk or hard disk. When the computer program on the storage medium is run, it can achieve fine-grained and dynamic scheduling of iterative resources, adapting to the high-speed transmission requirements of the 802.11 protocol.

[0139] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, and the indirect coupling or communication connection of the apparatus or units may be electrical, mechanical, or other forms.

[0140] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0142] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0143] Finally, it should be noted that the above embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for LDPC iterative decoding based on cross-layer sensing and system timing, characterized in that, The method includes the following steps: Obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding; Based on the system timing awareness mechanism, and combining the synchronization information of OFDM data packets, the real-time status of the memory, and protocol timing constraints, the real-time available time margin of the current LDPC code block is calculated. Specifically, the arrival time of the maximum energy path component within the OFDM data packet is located using a synchronization algorithm and used as a time reference. The elapsed processing time from the time reference to the current time is calculated, and combined with the total time length of the OFDM data packet, the remaining packet time for processing the current LDPC code block is obtained. Based on the real-time monitoring of the data backlog status of all buffer memories in the receiver system, the available buffer time is determined. Based on the remaining packet time, available buffer time, fixed delay, and protocol response time margin, the real-time available time margin of the current LDPC code block is calculated, and the latest completion time for decoding this code block is determined. Based on the cross-layer perception mechanism, the decoding status of the MAC layer data packet to which the current LDPC code block belongs is determined. Combined with the obtained real-time available time margin, the number of iterations for the current LDPC code block is dynamically calculated according to the scenario, and LDPC iterative decoding is performed.

2. The LDPC iterative decoding method based on cross-layer sensing and system timing as described in claim 1, characterized in that, in, The core parameters of LDPC decoding include the maximum number of iterations, the minimum number of iterations, the expected average number of iterations, resource fine-tuning parameters, and the time consumed in a single LDPC iteration.

3. The LDPC iterative decoding method based on cross-layer sensing and system timing as described in claim 2, characterized in that, The number of iterations for adaptation is dynamically calculated as follows, including the following steps: Extract the decoding status flag of the MAC layer data packet to which the current LDPC code block belongs, and determine whether the MAC layer data packet has been marked as decoding failure; If the MAC layer data packet has been marked as decoding failure, the iterative decoding process of the current LDPC code block is terminated, and the iteration time resources saved by this termination are calculated and carried over to the system iteration resource pool for subsequent LDPC decoding of MAC layer data packets that have not been marked as decoding failure. If the MAC layer data packet is not marked as decoding failure, the final iteration number of the current LDPC code block is dynamically calculated according to the code block position characteristics, real-time available time margin and preset core parameters, depending on the scenario. LDPC iterative decoding is performed on the current LDPC code block according to the final iteration number. The checksum status and checksum improvement rate after each iteration are monitored in real time to determine the decoding result. The decoding status flag of the MAC layer data packet to which the current LDPC code block belongs is updated according to the decoding result. If the decoding fails, the MAC layer data packet is marked as decoding failed. If the decoding is successful in advance, the remaining iteration time resources are carried over to the subsequent LDPC code block of the MAC layer data packet.

4. The LDPC iterative decoding method based on cross-layer sensing and system timing as described in claim 3, characterized in that, The dynamic calculation of the final iteration number of the current LDPC code block for each scenario includes the following steps: If the current LDPC block is the first block of its MAC layer data packet and the last LDPC block of its OFDM data packet, the final number of iterations is: If the current LDPC block is the first block of its MAC layer data packet and not the last LDPC block of the OFDM data packet, the final number of iterations is: in, For LDPC code block index; This represents the total number of LDPC code blocks contained in the current OFDM data packet; The maximum number of iterations; , , , The maximum number of iterations, minimum number of iterations, expected average number of iterations, and resource fine-tuning parameters are preset respectively.

5. The LDPC iterative decoding method based on cross-layer sensing and system timing as described in claim 4, characterized in that, in, The maximum number of iterations can be calculated using the following formula: in, This provides a margin of time for real-time availability. This is the preset time for a single LDPC iteration.

6. The LDPC iterative decoding method based on cross-layer sensing and system timing as described in claim 5, characterized in that, The decoding result is determined as follows: If the checksum is zero after a certain iteration, the decoding is considered successful, and the iteration is terminated. If the checksum improvement rate is lower than the preset convergence threshold during the iteration process, or if the checksum is not zero when the number of iterations reaches the maximum number of iterations, the decoding is deemed to have failed.

7. An LDPC iterative decoding device based on cross-layer sensing and system timing, characterized in that, The device includes: The parameter initialization module is used to obtain the total time length and the total number of LDPC code blocks contained in the current OFDM data packet, as well as the core parameters of the preset LDPC decoding. The time margin calculation module is used to calculate the real-time available time margin of the current LDPC code block based on the system's timing awareness mechanism, combined with the synchronization information of OFDM data packets, the real-time status of the memory, and protocol timing constraints. Specifically, it locates the arrival time of the largest energy path component within the OFDM data packet using a synchronization algorithm, and uses this as a time reference; it calculates the elapsed processing time from the time reference to the current time, and combines this with the total duration of the OFDM data packet to obtain the remaining packet time for processing the current LDPC code block; it determines the available buffer time of the memory based on the real-time monitoring of the data backlog status of all buffer memories in the receiver system; and it calculates the real-time available time margin of the current LDPC code block based on the remaining packet time, the available buffer time, the fixed delay, and the protocol response time margin, thus determining the latest completion time for decoding this code block. The iteration count calculation module is used to determine the decoding status of the MAC layer data packet to which the current LDPC code block belongs based on the cross-layer perception mechanism. Combined with the obtained real-time available time margin, it dynamically calculates the appropriate iteration count for the current LDPC code block according to the scenario and performs LDPC iterative decoding.

8. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of an LDPC iterative decoding method based on cross-layer sensing and system timing as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of an LDPC iterative decoding method based on cross-layer sensing and system timing as described in any one of claims 1 to 6.

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