A SiC MOSFET device with integrated Schottky diode and its fabrication method

Abstract

The application discloses a kind of integrated Schottky SiC MOSFET devices and its manufacturing method, after preparing the SiC epitaxial structure including second conductive type well region, first conductive type source region and heavily doped region and located between adjacent well region light doped JFET region, after the formation and patterning of gate dielectric and gate electrode, and the isolation medium side wall is made, then deposit source metal and annealing treatment are carried out at one time;Utilize the high concentration doping of first conductive type source region, especially the first conductive type high doped source region therein, to make metal and here form low resistance ohmic contact dominated by tunneling mechanism;At the same time, by the light doping characteristics of JFET region and drift region, the metal and here form Schottky contact with rectifier characteristics;Using relatively low annealing temperature, it can be ensured that the Schottky junction characteristics on light doped JFET region are not damaged while high-quality ohmic contact is formed.

Description

Technical Field

[0001] This invention relates to the field of MOSFET chip technology, and in particular to a SiC MOSFET device with integrated Schottky diode and its fabrication method. Background Technology

[0002] In the development of silicon carbide power MOSFETs, effectively addressing the inherent bipolar conduction problem of their body diode has always been a key challenge. The current mainstream solution is to connect a separate Schottky barrier diode (SBD) in parallel outside the MOSFET chip. The SBD's unipolar conduction characteristic bypasses the body diode, thus suppressing the accumulation of reverse recovery charge. However, this combination of discrete devices increases the system's packaging complexity and overall cost. Furthermore, due to the parasitic inductance in the circuit, its clamping effect is significantly reduced in high-frequency switching scenarios, limiting further performance improvements. Another technical approach is to attempt to integrate the Schottky structure into the MOSFET cell. However, traditional integration schemes mostly rely on complex process sequences, such as requiring two separate metal deposition and photolithography steps to define the ohmic and Schottky contact regions, or using different metal material systems. These methods not only significantly increase the number of process steps and manufacturing costs but also potentially affect the consistency of device parameters and long-term reliability due to the introduction of more interfaces and thermal budgets. In addition, in order to obtain excellent ohmic contact, traditional designs usually require a high overall doping concentration in the source region. However, this can lead to excessively high drain current peaks when the device experiences a short-circuit fault, thereby weakening the device's short-circuit withstand capability and posing a hidden danger in applications with stringent reliability requirements. Summary of the Invention

[0003] Technical Objective: To address the shortcomings of existing technologies, such as cumbersome processes and high costs, this invention provides an integrated Schottky SiC MOSFET device and its fabrication method. Through a single source metal deposition and annealing process, contacts with distinct properties are simultaneously formed in different doped regions of the device. This ensures the formation of high-quality ohmic contacts without compromising the Schottky junction characteristics on the lightly doped JFET region.

[0004] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0005] A method for fabricating a SiC MOSFET device with integrated Schottky diodes includes the following steps:

[0006] S1. Selective doping is performed on the drift region of the SiC epitaxial layer of the first conductivity type to form a well region of the second conductivity type, a source region of the first conductivity type, and a heavily doped region of the second conductivity type. The area between adjacent well regions of the second conductivity type is a JFET region. The source region of the first conductivity type and the heavily doped region of the second conductivity type are located in the well region of the second conductivity type. A highly doped source region of the first conductivity type is formed in the source region of the first conductivity type. The doping concentration of the highly doped source region of the first conductivity type is greater than the doping concentration of the source region of the first conductivity type.

[0007] S2. A gate dielectric, a gate electrode material layer, and a first isolation dielectric material layer are sequentially formed on the device of S1.

[0008] S3. Photolithography and etching of the first isolation dielectric material layer and the gate electrode material layer to form the first isolation dielectric and the gate electrode located above the partial JFET region, above the second conductivity type well region, above the first conductivity type source region and above the first conductivity type highly doped source region.

[0009] S4. A second isolation medium sidewall is formed on the sidewall of the first isolation medium and the gate electrode;

[0010] S5. A source metal is formed on the second conductivity type heavily doped region, the first conductivity type highly doped source region, the second isolation dielectric sidewall and above, the first isolation dielectric, and the JFET region. The source metal contacts the first conductivity type highly doped source region to form a source ohmic contact; the source metal contacts the second conductivity type heavily doped region to form a second conductivity type ohmic contact; and the source metal contacts the JFET region to form a Schottky contact.

[0011] S6. Form source thickening metal on the top of the device, and fabricate drain ohmic contact and drain thickening metal on the bottom of the device.

[0012] Preferably, the total implantation dose of the highly doped source region of the first conductivity type is 200% to 1000% of the total implantation dose of the source region of the first conductivity type; the implantation energy range of the highly doped source region of the first conductivity type is 10 keV to 150 keV, and the implantation dose is 5E13cm. -2 ~2E14cm -2 After implantation, the surface doping concentration is greater than 1E20cm. -3 .

[0013] Preferably, the annealing time of the source metal in S5 is 1 minute to 5 minutes, and the annealing temperature range is 500℃ to 750℃.

[0014] Preferably, an additional step S4' is added after S4 and before S5, including:

[0015] S4', A third isolation medium sidewall is formed on the sidewall of the second isolation medium sidewall.

[0016] Preferably, the spacing between the JFET region and the adjacent third isolation medium sidewall ranges from 0.2µm to 1.8µm.

[0017] Preferably, the spacing between the JFET region and the adjacent second isolation medium sidewall is in the range of 0.2um to 2.0um.

[0018] Preferably, the gate-source spacing at the source ohmic contact is equal to the gate-source spacing at the Schottky metal contact, ranging from 0.2µm to 0.8µm.

[0019] An integrated Schottky SiC MOSFET device, fabricated according to any of the above-described methods for fabricating an integrated Schottky SiC MOSFET device, includes:

[0020] First conductivity type: SiC epitaxial layer drift region;

[0021] The second conductivity type well region is located in the drift region of the first conductivity type SiC epitaxial layer; the first conductivity type source region and the second conductivity type heavily doped region are located in the second conductivity type well region, and the JFET region is between adjacent second conductivity type well regions; the boundary between the second conductivity type well region and the first conductivity type source region on the side closer to the JFET region defines the channel region of the device.

[0022] A highly doped source region of the first conductivity type located within a source region of the first conductivity type;

[0023] Gate dielectric covering the channel region, part of the first conductivity type source region, and part of the JFET region;

[0024] The gate electrode is located on the gate dielectric; the distances from the highly doped source regions of the first conductivity type to the channel regions on both sides of the gate electrode are equal;

[0025] The first isolation medium located on the gate electrode;

[0026] The second isolation dielectric sidewall is located on the gate electrode, the first isolation dielectric sidewall, and encloses the gate electrode;

[0027] The source metal covers the heavily doped region of the second conductivity type, the highly doped source region of the first conductivity type, and part of the JFET region; the source metal contacts the highly doped source region of the first conductivity type to form a source ohmic contact; the source metal contacts the heavily doped region of the second conductivity type to form a second conductivity type ohmic contact; the source metal contacts the JFET region to form a Schottky contact.

[0028] Source metal thickening covering the source metal.

[0029] Preferably, the second isolation medium sidewall is provided with a third isolation medium sidewall, and the widths of the third isolation medium sidewalls on both sides of the JFET are the same.

[0030] Beneficial effects:

[0031] 1. This invention utilizes a single source metal deposition and annealing process to simultaneously form contacts with distinct properties in different doped regions of a device. Specifically, after fabricating a SiC epitaxial structure comprising a second conductivity type well region, a first conductivity type source region, a heavily doped region, and a lightly doped JFET region located between adjacent well regions, the gate dielectric and gate electrode are formed and patterned, and isolation dielectric sidewalls are fabricated. Subsequently, the source metal is deposited in a single step and annealed. Utilizing the high doping concentration of the first conductivity type source region, particularly the highly doped first conductivity type source region, a low-resistance ohmic contact dominated by a tunneling mechanism is formed between the metal and this region. Simultaneously, leveraging the light doping characteristics of the JFET region, which is comparable to the drift region, a Schottky contact with rectifying properties is formed between the metal and this region. By precisely controlling the annealing conditions, especially employing a relatively low annealing temperature, it is ensured that high-quality ohmic contacts are formed without damaging the Schottky junction characteristics on the lightly doped JFET region. Furthermore, the highly doped first conductivity type source region helps to balance and reduce the source region doping concentration, improving the device's short-circuit withstand capability.

[0032] 2. This invention successfully constructs a natural Schottky diode within a single cell. This integrated diode provides a low-threshold unipolar conduction path for reverse current during switching, effectively avoiding the problems of increased on-state voltage drop and carrier lifetime degradation caused by body diode conduction. This significantly reduces reverse recovery charge and improves switching efficiency and speed. More importantly, this invention cleverly introduces a locally heavily doped source region design, allowing for a suitable reduction in the overall doping level of the source region while ensuring excellent ohmic contact with the metal. This design effectively balances the contradiction between on-resistance and short-circuit robustness, maintaining low contact resistance while suppressing excessive peak current during short-circuit events, thus significantly enhancing the device's short-circuit withstand capability and improving the system's survivability and reliability under fault conditions.

[0033] 3. In terms of manufacturing process, the advantages of this invention are extremely prominent. It eliminates the cumbersome multi-step metallization process and completes high-quality ohmic contacts and Schottky contacts simultaneously through only one deposition of source metal and one precisely controlled rapid annealing. This greatly simplifies the process flow, saves photomask and material costs, and improves production efficiency and wafer yield. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating a method for fabricating a SiC MOSFET device with integrated Schottky diode according to Embodiment 1 of the present invention.

[0035] Figure 2This is a flowchart illustrating a method for fabricating a SiC MOSFET device with integrated Schottky diode according to Embodiment 2 of the present invention.

[0036] Figure 3 This is a schematic diagram of the structure of a SiC MOSFET device with integrated Schottky diode according to Embodiment 1 of the present invention;

[0037] Among them, 100 is the SiC epitaxial layer drift region of the first conductivity type; 110 is the well region of the second conductivity type; 120 is the source region of the first conductivity type; 121 is the highly doped source region of the first conductivity type; 130 is the heavily doped region of the second conductivity type; 200 is the gate dielectric; 300 is the gate electrode material layer; 400 is the first isolation dielectric material layer; 510 is the second isolation dielectric sidewall; 600 is the source metal; 601 is the source ohmic contact; 602 is the Schottky contact; 700 is the source thickened metal; and 810 is the third isolation dielectric sidewall. Detailed Implementation

[0038] The following description, in conjunction with the accompanying drawings and embodiments, further explains and illustrates an integrated Schottky SiC MOSFET device and its fabrication method according to the present invention.

[0039] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0040] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] Example 1:

[0042] As attached Figure 1 As shown, a method for fabricating an integrated Schottky SiC MOSFET device according to the present invention includes the following steps:

[0043] S1. Selective doping is performed on the drift region 100 of the SiC epitaxial layer of the first conductivity type to form a well region 110 of the second conductivity type, a source region 120 of the first conductivity type, and a heavily doped region 130 of the second conductivity type. The area between adjacent well regions of the second conductivity type is a JFET region. The source region 120 of the first conductivity type and the heavily doped region 130 of the second conductivity type are located in the well region 110 of the second conductivity type. The source region 120 of the first conductivity type and the heavily doped region 130 of the second conductivity type may or may not be in contact. In this embodiment, the source region 120 of the first conductivity type and the heavily doped region 130 of the second conductivity type are adjacent. A highly doped source region 121 of the first conductivity type is formed in the source region 120. The highly doped source region 121 of the first conductivity type does not directly contact the well region 110 of the second conductivity type. The doping concentration of the highly doped source region of the first conductivity type is greater than the doping concentration of the first conductivity type source region.

[0044] As attached Figure 1 As shown in Figure (A), a second conductivity type well region 110, a first conductivity type source region 120, and a second conductivity type heavily doped region 130 are sequentially formed on the SiC epitaxial layer drift region 100 through multiple photolithography, etching, and ion implantation processes. The upper surfaces of the second conductivity type well region 110, the first conductivity type source region 120, and the second conductivity type heavily doped region 130 are flush, and the depth of the first conductivity type source region 120 is less than the depth of the second conductivity type well region 110. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0045] In the first conductivity type source region 120, after fabricating a sidewall mask using dielectric growth and etching, a first conductivity type highly doped source region 121 is formed by implantation. The width of the sidewall ranges from 0.1 μm to 0.5 μm. When forming the first conductivity type highly doped source region, the highest implantation energy used does not exceed 70% of the highest implantation energy of the first conductivity type source region. The total implantation dose of the first conductivity type highly doped source region is 200% to 1000% of the total implantation dose of the first conductivity type source region. The implantation energy range of the first conductivity type highly doped source region is 10 keV to 150 keV, and the implantation dose is 5E13cm. -2 ~2E14cm -2 After implantation, the surface doping concentration is greater than 1E20cm. -3 The depth of the highly doped source region 121 of the first conductivity type is less than the depth of the source region 120 of the first conductivity type.

[0046] The area between adjacent second conductivity types is the JFET region of the device, which is approximately 2.8 μm wide in this example. Typically, the peak doping concentration of the well region for the second conductivity type is 1E18 cm⁻¹. -3 The peak doping concentration of the source region for the first conductivity type is above 1E19cm. -3The doping concentration in the JFET region is comparable to that in the epitaxial drift region, typically 1E15cm depending on the voltage rating. -3 ~5E16cm -3 .

[0047] S2. A gate dielectric 200, a gate electrode material layer 300, and a first isolation dielectric material layer 400 are sequentially formed on the device of S1; the thickness L1 of the first isolation dielectric material layer 400 ranges from 0.8um to 2um.

[0048] As attached Figure 1 As shown in (B), a gate dielectric 200 is first formed on the device S1 using thermal oxidation. In this example, the thickness of the gate dielectric is approximately 50 nm. Next, a gate electrode material layer 300 is deposited using LPCVD. This gate electrode material layer is made of doped polysilicon and has a thickness of approximately 500 nm. Finally, a first isolation dielectric material layer 400 is deposited using either LPCVD or PECVD. This first isolation dielectric material layer 400 is made of SiO2, and in this example, its thickness is approximately 1 μm.

[0049] S3. Photolithography and etching of the first isolation dielectric material layer and the gate electrode material layer to form the first isolation dielectric and the gate electrode located above the partial JFET region, above the second conductivity type well region 110, and above the first conductivity type source region 120; the spacing between adjacent gate electrodes above the JFET region ranges from 0.6um to 3.2um;

[0050] As attached Figure 1 As shown in (C), to ensure good conduction characteristics, the remaining gate electrode should completely cover the channel region in the device depth projection direction. In this example, the width of a single gate electrode is approximately 1.7 μm, and the spacing between the gate electrodes above the JFET region is approximately 2 μm.

[0051] S4. A second isolation dielectric sidewall 510 is formed on the sidewall of the first isolation dielectric and the gate electrode, and a highly doped source region of the first conductivity type is exposed; the spacing between adjacent second isolation dielectric sidewalls 510 above the JFET region ranges from 0.2um to 2.0um.

[0052] First, a second isolation dielectric material is grown on the sidewalls of the first isolation dielectric and the gate electrode using LPCVD (Liquid Chemical Vapor Deposition). The thickness L2 of the second isolation dielectric material ranges from 0.2 μm to 1.2 μm. Then, the second isolation dielectric material is etched to form second isolation dielectric sidewalls 510 on both sides of the gate electrode. During etching, the over-etching amount is 20% to 100%, i.e., the total etching thickness ranges from 1.2L2 to 2L2. If there is residual gate dielectric above the highly doped source region of the first conductivity type after step S3, this step will also etch it to ensure that the highly doped source region of the first conductivity type is exposed.

[0053] As attached Figure 1 As shown in (D), a second isolation dielectric material is grown and etched to form second isolation dielectric sidewalls 510 on both sides of the gate electrode. The second isolation dielectric material is SiO2, with a growth thickness of approximately 500 nm and an etching thickness of approximately 700 nm. By setting the over-etching amount, the SiC in the source region and the center of the JFET, i.e., the drift region 100 of the first conductivity type SiC epitaxial layer, is exposed to facilitate subsequent alloying processes.

[0054] S5. A source metal 600 is formed on the second conductivity type heavily doped region 130, the first conductivity type highly doped source region 121, the sidewall of the second isolation dielectric 510 and above, the first isolation dielectric, and the JFET region. The source metal 600 contacts all or part of the first conductivity type highly doped source region, and the source metal 600 may not contact the first conductivity type source region 120, but the projected area of ​​the source metal 600 must cover the first conductivity type source region 120 and the gate electrode. The source metal 600 contacts the first conductivity type highly doped source region 121 to form a source ohmic contact 601; the source metal 600 contacts the second conductivity type heavily doped region 130 to form a second conductivity type ohmic contact (in this embodiment, a P-type ohmic contact); the source metal 600 contacts the JFET region to form a Schottky contact 602.

[0055] As attached Figure 1 As shown in (E) and (F), source metal 600 is deposited on the S4 device and annealed to form a source ohmic contact 601 and a Schottky contact 602 above the JFET region. The annealing process uses a rapid annealing (RTA) device with an annealing time of 1 to 5 minutes and an annealing temperature range of 500°C to 750°C, which is lower than the annealing temperature range of 800°C to 1050°C in the prior art. In this example, the source metal material is nickel, with a deposition thickness of 0.2 μm, formed by sputtering. In some other embodiments of the present invention, the annealing temperature range is 600°C to 700°C, and the annealing time is 2 to 3 minutes to form the Schottky contact 602 in the JFET region. Due to the high doping concentration of the first conductivity type in the source region, a tunneling-assisted ohmic contact, i.e., the source ohmic contact 601, is formed.

[0056] S6. A source thickening metal 700 is formed on the top of the device, and a drain ohmic contact and a drain thickening metal are formed on the bottom of the device, that is, below the drift region 100 of the first conductivity type SiC epitaxial layer.

[0057] As attached Figure 1 As shown in Figure (G), a source thickening metal 700 is formed on the top of the device, and a drain ohmic contact and drain thickening metal are fabricated on the bottom of the device, below the drift region 100 of the SiC epitaxial layer of the first conductivity type, and then alloyed and annealed. In this example, the source thickening metal is aluminum with a thickness ranging from 4µm to 5µm, and is deposited by sputtering.

[0058] As attached Figure 3 As shown, this embodiment also discloses a SiC MOSFET device with integrated Schottky diodes, comprising:

[0059] First conductivity type SiC epitaxial layer drift region 100;

[0060] The second conductivity type well region 110 is located in the drift region of the first conductivity type SiC epitaxial layer; the upper surface of the drift region of the first conductivity type SiC epitaxial layer is flush with the upper surface of the second conductivity type well region.

[0061] The first conductivity type source region 120 and the second conductivity type heavily doped region 130 are located in the second conductivity type well region, and the area between adjacent second conductivity type well regions is the JFET region; the boundary between the second conductivity type well region and the first conductivity type source region on the side closer to the JFET region defines the channel region of the device; the upper surfaces of the second conductivity type well region, the first conductivity type source region, and the second conductivity type heavily doped region are flush; the depth of the first conductivity type source region is less than the depth of the second conductivity type well region;

[0062] The first conductivity type highly doped source region 121 is located in the first conductivity type source region, and the depth of the first conductivity type highly doped source region is less than the depth of the first conductivity type source region;

[0063] Gate dielectric 200 covering the channel region, part of the first conductivity type source region, and part of the JFET region;

[0064] The gate electrode is located on the gate dielectric; the distances from the highly doped source regions of the first conductivity type to the channel regions on both sides of the gate electrode are equal;

[0065] The first isolation medium located on the gate electrode;

[0066] The second isolation dielectric sidewall 510 is located on the gate electrode, the sidewall of the first isolation dielectric, and encloses the gate electrode;

[0067] A source metal 600 covers a heavily doped region of the second conductivity type, all or part of a highly doped source region of the first conductivity type, and part of a JFET region; the source metal 600 contacts the highly doped source region 121 of the first conductivity type to form a source ohmic contact 601; the source metal 600 contacts the JFET region to form a Schottky contact 602.

[0068] Source metal thickening 700 covering source metal.

[0069] The gate-source spacing (minimum distance between ohmic contact and gate electrode) at the source ohmic contact is equal to the gate-source spacing (minimum distance between Schottky contact and gate electrode) at the Schottky metal contact, ranging from 0.2µm to 0.8µm, which corresponds to the width of a single second isolation medium sidewall 510.

[0070] Example 2:

[0071] As attached Figure 2 As shown, the method for fabricating an integrated Schottky SiC MOSFET device according to the present invention differs from that in Example 1 in that an additional step S4' is added after S4 and before S5, including:

[0072] S4' A third isolation medium sidewall 810 is formed on the sidewall of the second isolation medium sidewall 510. The spacing between adjacent third isolation medium sidewalls 810 above the JFET region ranges from 0.2um to 1.8um. ​​The widths of the third isolation medium sidewalls on both sides of the JFET are the same.

[0073] A third isolation dielectric material is formed on the first isolation dielectric, the sidewall of the second isolation dielectric 510, and above it. After etching, a third isolation dielectric sidewall 810 is formed on the sidewall of the second isolation dielectric 510. The third isolation dielectric sidewall 810 can reduce the aspect ratio of the opening between adjacent second isolation dielectric sidewalls, reduce the difficulty of subsequent source electrode thickening metal filling, and avoid the formation of voids in the high aspect ratio dielectric trench. In this embodiment, the third isolation dielectric material is SiO2, with a growth thickness of about 200 nm and an etching thickness of about 300 nm.

[0074] In this embodiment, the gate-source spacing (minimum distance between ohmic contact and gate electrode) at the source ohmic contact is equal to the gate-source spacing (minimum distance between Schottky contact and gate electrode) at the Schottky metal contact, ranging from 0.2um to 0.8um, which corresponds to the sum of the width of a single second isolation medium sidewall 510 and the width of a single third isolation medium sidewall 810.

[0075] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a SiC MOSFET device with integrated Schottky diodes, characterized in that, Includes the following steps: S1. Selective doping is performed on the drift region (100) of the SiC epitaxial layer of the first conductivity type to form a well region (110) of the second conductivity type, a source region (120) of the first conductivity type, and a heavily doped region (130) of the second conductivity type. The area between adjacent well regions of the second conductivity type is a JFET region. The source region (120) of the first conductivity type and the heavily doped region (130) of the second conductivity type are located in the well region (110). A highly doped source region (121) of the first conductivity type is formed in the source region (120). The doping concentration of the highly doped source region of the first conductivity type is greater than that of the source region of the first conductivity type. S2. A gate dielectric (200), a gate electrode material layer (300), and a first isolation dielectric material layer (400) are sequentially formed on the device of S1. S3. Photolithography and etching of the first isolation dielectric material layer and the gate electrode material layer to form the first isolation dielectric and the gate electrode located above the partial JFET region, above the second conductivity type well region (110), and above the first conductivity type source region (120); S4. A second isolation medium sidewall (510) is formed on the sidewall of the first isolation medium and the gate electrode. S5. A source metal (600) is formed on the second conductivity type heavily doped region (130), the first conductivity type highly doped source region (121), the sidewall of the second isolation dielectric (510) and above, the first isolation dielectric and the JFET region. The source metal (600) is in contact with the first conductivity type highly doped source region (121) to form a source ohmic contact (601); the source metal (600) is in contact with the second conductivity type heavily doped region (130) to form a second conductivity type ohmic contact; the source metal (600) is in contact with the JFET region to form a Schottky contact (602); the annealing time of the source metal in S5 is 1 minute to 5 minutes, and the annealing temperature range is 500℃ to 750℃. S6. Form source thickening metal (700) on the top of the device, and fabricate drain ohmic contact and drain thickening metal on the bottom of the device.

2. The method for fabricating a SiC MOSFET device with integrated Schottky diode according to claim 1, characterized in that: The total implantation dose of the highly doped source region of the first conductivity type is 200% to 1000% of the total implantation dose of the source region of the first conductivity type; the implantation energy range of the highly doped source region of the first conductivity type is 10 keV to 150 keV, and the implantation dose is 5E13cm. -2 ~2E14cm -2 After implantation, the surface doping concentration is greater than 1E20cm. -3 .

3. The method for fabricating a SiC MOSFET device with integrated Schottky diodes according to claim 1, characterized in that: An additional step S4' is added after S4 and before S5, including: S4', A third isolation medium sidewall (810) is formed on the sidewall of the second isolation medium sidewall (510).

4. The method for fabricating a SiC MOSFET device with integrated Schottky diode according to claim 3, characterized in that: The spacing between the JFET region and the adjacent third isolation medium sidewall (810) ranges from 0.2um to 1.8um.

5. The method for fabricating a SiC MOSFET device with integrated Schottky diode according to claim 1, characterized in that: The spacing between the JFET region and the adjacent second isolation medium sidewall (510) ranges from 0.2um to 2.0um.

6. The method for fabricating a SiC MOSFET device with integrated Schottky diode according to claim 1, characterized in that: The gate-source spacing at the source ohmic contact is equal to that at the Schottky metal contact, ranging from 0.2µm to 0.8µm.

7. A SiC MOSFET device with integrated Schottky diode, manufactured according to the method for fabricating an SiC MOSFET device with integrated Schottky diode as described in any one of claims 1-6, characterized in that: include: First conductivity type SiC epitaxial layer drift region (100); A second conductivity type well region (110) is located in the drift region of the first conductivity type SiC epitaxial layer; a first conductivity type source region (120) and a second conductivity type heavily doped region (130) are located in the second conductivity type well region, and a JFET region is located between adjacent second conductivity type well regions; the boundary between the second conductivity type well region and the first conductivity type source region on the side near the JFET region defines the channel region of the device. The first conductivity type highly doped source region (121) is located in the first conductivity type source region. Gate dielectric (200) covering the channel region, part of the first conductivity type source region and part of the JFET region. The gate electrode is located on the gate dielectric; the distances from the highly doped source regions of the first conductivity type to the channel regions on both sides of the gate electrode are equal. The first isolation medium located on the gate electrode; A second isolation dielectric sidewall (510) is located on the gate electrode, the first isolation dielectric sidewall and encapsulates the gate electrode. A source metal (600) covers a heavily doped region of the second conductivity type, a highly doped source region of the first conductivity type, and part of the JFET region; the source metal (600) contacts the highly doped source region of the first conductivity type (121) to form a source ohmic contact (601); the source metal (600) contacts the heavily doped region of the second conductivity type (130) to form a second conductivity type ohmic contact; the source metal (600) contacts the JFET region to form a Schottky contact (602). Source metal thickening (700) covering the source metal.

8. A SiC MOSFET device with integrated Schottky diode according to claim 7, characterized in that: The second isolation medium sidewall (510) has a third isolation medium sidewall (810) on its sidewall, and the width of the third isolation medium sidewall on both sides of the JFET is the same.

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