Operational transconductance amplifier

Abstract

The invention relates to an operational transconductance amplifier. The improved OTA may include an input circuit arranged to receive a differential voltage input; a load circuit arranged to measure a positive branch current and a negative branch current from the input circuit; a bias circuit arranged to determine a bias voltage based on the negative branch current; a folded current branch circuit arranged to generate an adaptive bias current; and a pass transistor configured to adjust an amount of the adaptive bias current based on the bias voltage; and a push-pull output circuit configured to draw a current based on the adjusted adaptive bias current. The folded current branch circuit may generate an adaptive bias current based on the measured negative branch current. An output circuit may supply a current based on the measured positive branch current. Advantageously, most transistors may have a minimum size.

Description

TECHNICAL FIELD

[0001] The present application relates generally to operational transconductance amplifiers, and more specifically to current mirror based operational transconductance amplifiers. BACKGROUND

[0002] Operational transconductance amplifiers (OTAs) are used in many electronic circuits for various applications, such as voltage controlled amplifiers, filters, image sensors, other analog circuits, etc. For example, OTAs can be used with readout circuits of CMOS image sensors. OTAs generally convert an input voltage signal to an output current. An OTA can amplify a voltage difference between two input terminals to produce a proportional output current. The ratio of the output current to the input voltage difference is referred to as the transconductance, or g m .

[0003] Current mirror OTAs use a current mirror configuration to generate an output current proportional to an input voltage. A current mirror OTA has a differential input transistor pair that receives a differential input voltage (e.g., on respective control terminals). The voltage difference controls the current flowing through each transistor in the differential pair, which is mirrored to control one or more output transistors to produce an output current. For example, the output transistors can be arranged as a push-pull pair, and each can be driven according to a respective current mirror corresponding to a respective transistor in the differential pair. A variety of transistor types (e.g., MOSFET, BJT, etc.) can be used to implement the OTA.

[0004] The bandwidth of an OTA refers to the range of frequencies in which the OTA can effectively amplify a signal without significant attenuation or distortion, e.g., where the DC gain remains relatively constant within certain tolerances. The slew rate of the output current of an OTA refers to the rate at which the output current can change in response to a sudden change in the input voltage, e.g., while still maintaining linearity and stability. When increased performance is desired, e.g., faster settling time, increased slew rate, etc., the OTA can be designed with increased current and increased transconductance. This requires increased device size, increased area for implementing the OTA, and increased power consumption.

[0005] Accordingly, it is desirable to provide improved current mirror OTA devices and methods with lower power and area requirements. SUMMARY

[0006] Various embodiments relate to systems, devices, and methods for current mirror operational transconductance amplifiers.

[0007] In various embodiments, an operational transconductance amplifier (OTA) can include: an input circuit including a first input transistor coupled in parallel with a second input transistor, wherein the first input transistor and the second input transistor are controllable according to a differential voltage input signal; a load circuit coupled with the input circuit, the load circuit including a first reference transistor coupled in series with the first input transistor and a second reference transistor coupled in series with the second input transistor, wherein the first reference transistor is configured to measure a first current through the first input transistor and the second reference transistor is configured to measure a second current through the second input transistor; an output circuit including a sourcing transistor coupled in series with a sinking transistor, wherein the sourcing transistor is coupled with the sinking transistor at an output terminal; a folded current branch circuit coupled with the output circuit and including a pass transistor, wherein the pass transistor is configured to control a third current flowing through the folded current branch circuit based on a bias voltage, and the folded current branch circuit is configured to control the sinking transistor based on the third current; and a bias circuit coupled with the load circuit and the folded current branch circuit and configured to determine the bias voltage based on the measured first current.

[0008] In various embodiments, an OTA can include: an input circuit configured to generate a positive branch current based on a positive differential input voltage and a negative branch current based on a negative differential input voltage; a load circuit coupled with the input circuit and configured to measure the positive branch current and the negative branch current; a bias circuit coupled with the load circuit and configured to determine a dynamic bias voltage based on the measured negative branch current; an output circuit coupled with the load circuit, wherein the output circuit includes a push-pull transistor pair and is configured to supply current to an output terminal based on the measured positive branch current; and a folded current branch circuit coupled with the bias circuit and the output circuit and configured to control the output circuit to sink current from the output terminal based on the dynamic bias voltage.

[0009] In various embodiments, an OTA can include: an input circuit including a first input transistor coupled in parallel with a second input transistor, wherein a gate of the first input transistor is configured to receive a negative differential input voltage and a gate of the second input transistor is configured to receive a positive differential input voltage; a load circuit coupled with the input circuit, the load circuit including a negative branch current mirror configured to measure a negative branch current through the first input transistor and a positive branch current mirror configured to measure a positive branch current through the second input transistor, wherein the negative branch current mirror and the positive branch current mirror are cross-coupled; a folded current branch circuit coupled with an output circuit, wherein the folded current branch circuit includes a pass transistor configured to adjust an adaptive current based on a bias voltage, and the folded current branch circuit is configured to control the output circuit to sink an output current at an output terminal based on the adjusted adaptive current; and a bias circuit coupled with the load circuit and the folded current branch circuit and configured to determine the bias voltage based on the measured negative branch current.

[0010] These and other examples are described in more detail below. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic diagram illustrating a first exemplary current mirror operational transconductance amplifier (OTA) in accordance with various embodiments.

[0012] Figure 2 FIG. 2 is a schematic diagram illustrating a second exemplary current mirror OTA in accordance with various embodiments.

[0013] Figure 3 FIG. 3 is a schematic diagram illustrating a third exemplary current mirror OTA in accordance with various embodiments.

[0014] Figure 4A FIG. 4 illustrates simulated output voltages compared to differential input voltages for each of the first exemplary OTA, the second exemplary OTA, and the third exemplary OTA in accordance with various embodiments.

[0015] Figure 4B FIG. 5 is a table illustrating additional simulated results for each of the first exemplary OTA, the second exemplary OTA, and the third exemplary OTA in accordance with various embodiments. DETAILED DESCRIPTION

[0016] The following detailed description is intended to provide a number of examples that will illustrate the broader concepts set forth herein, but are not intended to limit the present application or the application and uses of the present application. Furthermore, no theory or the foregoing background is intended to limit the present application or the application and uses of the present application.

[0017] According to various embodiments, current mirror OTA circuits and methods are used to measure a difference between differential voltage input signals and drive an output current accordingly, such as sourcing the output current in the case of a respective increase in positive voltage input signals and sinking the output current in the case of a respective increase in negative voltage input signals. Various embodiments can include improved circuits that increase or otherwise improve the transconductance, gain, bandwidth, slew rate, settling time, and stability of the current mirror OTA without substantially increasing the circuit size and while maintaining the ability to use minimum size transistors.

[0018] Figure 1 An exemplary embodiment of a first current mirror OTA 100 circuit is shown. The OTA 100 can include an input circuit 110 configured to receive differential voltage input signals. In some embodiments, the input circuit 110 can include a differential input transistor pair, such as a first input transistor Ml configured to receive a respective negative input Vin of the differential voltage input signals and a second input transistor M2 configured to receive a respective positive input Vip of the differential voltage input signals. The negative input node Vin can be referred to as the inverting input of the OTA 100 and the positive input node Vip can be referred to as the non-inverting input of the OTA 100.

[0019] The differential pair transistors Ml, M2 can be coupled in parallel, with the first input transistor Ml on a negative branch of the input circuit 110 and the second input transistor M2 on a positive branch of the input circuit 110. The differential pair transistors Ml, M2 can receive respective input signals on their control terminals (e.g., gate terminals for field effect transistors (FETs)). In some embodiments, the differential pair transistors Ml, M2 can be N-channel metal-oxide-semiconductor (NMOS) transistors.

[0020] The input circuit 110 can be coupled in series with a tail current source 115 configured to provide a constant current. The tail current source 115 can be coupled in series between the input circuit 110 and a common voltage node (e.g., ground). The tail current source 115 can include any suitable current source, such as a current mirror, a resistor, a bias transistor, etc. During operation of the OTA 100, the respective currents through the differential pair transistors Ml, M2 can change with changes in the positive and negative input signals at Vin, Vip, but will sum to the current determined by the tail current source 115.

[0021] In some implementations, the tail current source 115 can include a tail transistor M15 that is biased, e.g., as part of a current mirror (not shown), to provide a constant current to the differential pair of transistors Ml, M2. The tail transistor M15 can be a MOSFET, such as an NMOS transistor, with its source terminal coupled to a common voltage node and its drain coupled to the source terminals of the first and second input transistors Ml, M2. In various implementations, the differential pair of transistors Ml, M2 can be sized independently of one another or can be matched. In various implementations, the differential pair of transistors Ml, M2 need not be matched or sized with respect to the tail transistor M15 and / or the tail current source 135 tail transistor M14 (discussed below).

[0022] The input circuit 110 can also be coupled in series with a load circuit 120 that is configured to help determine one or more internal voltage reference nodes based on respective currents flowing through the differential pair of transistors Ml, M2. The load circuit 120 can be coupled between the input circuit 110 and a supply voltage terminal (e.g., providing a digital operating voltage Vdd, etc.). The load circuit 120 can include one or more devices coupled in series with the negative leg of the input circuit 110, and one or more devices coupled in series with the positive leg of the input circuit 110.

[0023] In some implementations, the load circuit 120 can include a negative-side current mirror having a reference transistor M3 coupled in series between the supply voltage Vdd and the first input transistor Ml of the negative leg of the input circuit 110. The negative-side current mirror can also include a mirror transistor M4 (also referred to herein as a load mirror transistor M4) that is configured to mirror a current measured by the reference transistor M3. The negative-side current mirror can be referred to as a M3-M4 current mirror, and the negative-side reference transistor M3 can be referred to as a first load reference transistor M3. In some implementations, the reference transistor M3 can include a diode-connected MOSFET, such as a PMOS transistor, and the mirror transistor M4 can include a MOSFET, such as a PMOS transistor, with a control terminal coupled to the control terminal of the reference transistor M3.

[0024] For example, the reference transistor M3 can have its source terminal coupled to the supply voltage Vdd and its drain and gate terminals coupled to the first input transistor Ml at a positive internal voltage reference node Vop (also referred to herein as a positive reference node). The mirror transistor M4 can have its gate terminal coupled to the positive reference node Vop, its source terminal coupled to the supply voltage Vdd, and its drain terminal coupled to a negative internal voltage reference node Von (also referred to herein as a negative reference node). As used herein, a voltage reference node can provide a reference voltage for use by various circuits and components.

[0025] The load circuit 120 may also include a diode-connected transistor M5, such as a PMOS transistor, coupled in series between the supply voltage Vdd and the second input transistor M2 on the positive branch of the input circuit 110. For example, transistor M5 may be configured as a reference transistor for a current mirror, with a corresponding mirror transistor located in the output circuit 150. The reference transistor M5 may have its source terminal coupled to the supply voltage Vdd and its drain terminal and gate terminal coupled to the second input transistor M2 at the negative reference node Von. The reference transistor M5 may be referred to as the second load reference transistor M5.

[0026] Typically, when the positive input signal Vip increases relative to the negative input signal Vin, the voltage at the positive reference node Vop increases and the voltage at the negative reference node Von decreases. Similarly, when the positive input signal Vip decreases relative to the negative input signal Vin, the voltage at the positive reference node Vop decreases and the voltage at the negative reference node Von increases. Other load circuitry 120 configurations, such as load resistors, can be implemented to determine the voltages at reference nodes Vop and Von relative to the differential voltage input signals.

[0027] The OTA 100 may also include an output circuit 150 configured to supply current to or draw current from a load (not shown) in response to a positive input signal Vin and a negative input signal Vip. In some embodiments, the output circuit 150 may include one or more transistors configured to supply current to and / or draw current from the load at the output terminal Vout of the OTA 100. For example, the output circuit 150 may include a push-pull arrangement of transistors (e.g., MOSFETs) configured to supply and / or draw current based on a differential voltage input signal. In some embodiments, the output circuit 150 may include a current-source transistor M11 configured to supply current to the load, coupled in series with a current-sinking transistor M10 configured to draw current from the load.

[0028] The load can be connected between the current-source transistor M11 and the current-sink transistor M10. For example, the current-source transistor M11 can be a PMOS transistor with its source terminal coupled to the supply voltage Vdd and its drain terminal coupled to the output terminal Vout, and the current-sink transistor M10 can be an NMOS transistor with its source terminal coupled to the common voltage node and its drain terminal coupled to the output terminal Vout.

[0029] In some implementations, the current-source transistor M11 may be a mirror transistor of the reference transistor M5 on the positive branch of the load circuit 120, and its control terminal may be coupled to the negative reference node Von. This current mirror may be referred to as the M5-M11 current mirror. For example, when the positive input signal Vip increases relative to the negative input signal Vin and the voltage at the negative reference node Von decreases, the Vgs of the current-source transistor M11 will increase and the current source will increase. The current-source transistor M11 will mirror the increased current through the second load reference transistor M5.

[0030] The OTA 100 may also include a bias circuit 130 and a folded current branch circuit 140. The bias circuit 130 may include any suitable configuration of components configured to generate one or more bias voltages for the folded current branch circuit 140. In some embodiments, the bias circuit 130 may include a first reference transistor M12, a second reference transistor M13, and a tail current source 135. The first reference transistor M12, the second reference transistor M13, and the tail current source 135 may be coupled in series and, in some embodiments, may include PMOS and / or NMOS transistors. The first reference transistor M12 and the second reference transistor M13 may provide a fixed bias voltage to the folded current branch circuit 140 and may be referred to herein as the first bias reference transistor M12 and the second bias reference transistor M13, respectively.

[0031] For example, the first bias reference transistor M12 may be a diode-connected PMOS transistor, with its source terminal coupled to the supply voltage Vdd and its gate and drain terminals coupled to the source terminals of the second reference transistor M13. The second bias reference transistor may also be a diode-connected PMOS transistor, with its gate and drain terminals coupled to the tail current source 135. The tail current source 135 may be configured to provide a constant current through the first bias reference transistor M12 and the second bias reference transistor M13, and may include any suitable current source, such as a current mirror, resistor, bias transistor, etc.

[0032] In some embodiments, tail current source 135 may include tail transistor M14, which is biased, for example, as part of a current mirror (not shown) to provide a constant current. Tail transistor M14 may be a MOSFET, such as an NMOS transistor, with its source terminal coupled to a common voltage node and its drain coupled to the drain of a second bias reference transistor M13. In various embodiments, tail transistor M15 does not need to be matched with tail transistor M14 of tail current source 135 (e.g., no size relationship is required).

[0033] The folded current branch circuit 140 can be configured to help control the current flowing through the current-source transistor M11 and / or current-sink transistor M10 of the output circuit 150 based on differential voltage input signals Vin, Vip. The folded current branch circuit 140 can provide a current source that varies depending on the differential voltage input signals Vin, Vip, and is mirrored by the current-source transistor M11 and / or current-sink transistor M10. In some embodiments, the folded current branch circuit 140 may include a mirror transistor M7, a transfer transistor M8, and a reference transistor M9. The mirror transistor M7, transfer transistor M8, and reference transistor M9 may be coupled in series.

[0034] The mirror transistor M7 (also referred to herein as the current-branch mirror transistor M7) can be configured to mirror the current measured through the first bias reference transistor M12, for example, to provide a current source for the folded current-branch circuit 140. The mirror transistor M7 can couple its control terminal to the control terminal of the first reference transistor M12 of the bias circuit to create an M12-M7 current mirror. In some embodiments, the mirror transistor M7 can be a PMOS transistor, with its source terminal coupled to the supply voltage Vdd and its drain terminal coupled to the negative reference node Von.

[0035] The transfer transistor M8 can be configured to carry a varying amount of current provided by the mirror transistor M7, depending on the fixed bias provided by the second bias reference transistor M13 and the voltage of the negative reference node Von. The transfer transistor M8 can thus adjust the amount of current provided by the mirror transistor M7. The transfer transistor M8 can be a PMOS transistor with its source terminal coupled to the negative reference node Von, its drain coupled to the reference transistor M9, and its control terminal coupled to the control terminal of the second bias reference transistor M13 of the bias circuit 130. The second bias reference transistor M13 and the transfer transistor M8 can form a current mirror referred to as the M13-M8 current mirror. The transfer transistor M8 and the second load reference transistor M5 can act as a load on the negative reference node Von.

[0036] A reference transistor M9 (also referred to herein as a current-branch reference transistor M9) may be configured as a reference transistor in a current mirror. In some embodiments, the current-branch reference transistor M9 may measure the current passing through the transfer transistor M8 for mirroring by the current-sinking transistor M10 of the output circuit 150, thereby generating an M9-M10 current mirror. For example, the current-branch reference transistor M9 may be a diode-connected NMOS transistor whose gate and drain terminals are coupled to the drain terminal of the transfer transistor M8, and whose source terminal is coupled to a common voltage node. The gate of the current-branch reference transistor M9 may be coupled to the gate of the current-sinking transistor M10.

[0037] Therefore, the current from the change in the mirror transistor M7 will pass through the transfer transistor M8 and the reference transistor M9 to be mirrored by the sink transistor M10, thus acting as a pull-down current. Typically, when the positive input signal Vip increases relative to the negative input signal Vin and the voltage at the negative reference node Von decreases, the voltage difference (Vgs) between the gate and source of the transfer transistor M8 will decrease, resulting in a decrease in the current from the mirror transistor M7 through the transfer transistor M8. This decreased current through the transfer transistor M8 is measured by the current branch reference transistor M9 and mirrored to the sink transistor M10, resulting in a decrease in the sink current in the output circuit 150. The decrease in the sink current occurs when the decreased negative reference node Von causes an increase in the pull-up current, thus increasing the current output at the output terminal Vout.

[0038] Similarly, when the positive input signal Vip decreases relative to the negative input signal Vin and the voltage at the negative reference node Von increases, the voltage difference (Vgs) between the gate and source of the transfer transistor M8 increases, resulting in an increase in the current flowing through the transfer transistor M8 from the mirror transistor M7. This increased current through the transfer transistor M8 is measured by the current branch reference transistor M9 and mirrored to the current sink transistor M10, resulting in an increase in the sink current in the output circuit 150. The increase in the sink current occurs when the increased negative reference node Von causes a decrease in the pull-in current. Therefore, small changes in the differential voltage input signals Vin and Vip can lead to a large swing in the output current at the output terminal Vout.

[0039] The various transistors of the OTA 100 can be sized or otherwise selected to have one or more gain values, transconductance values, and / or other parameters tuned to provide the desired performance of the OTA 100. For example, the transistors of the OTA 100 include MOSFET transistors having one or more width-to-length (W / L) ratios, wherein the relative strength of the transistor increases with increasing ratio. The various W / L ratios described herein are merely exemplary and may vary depending on process parameters, design rules, and requirements, etc.

[0040] In some embodiments, the transfer transistor M8 and the current branch mirror transistor M7 may be selected (e.g., configured) to have the minimum size allowed by the relevant process technology, such as a W / L ratio of 1, and the current branch reference transistor M9 may also be selected to have the minimum size, such as a W / L ratio of 1. In other embodiments, the transistors of the folded current branch circuit 140 may be selected to not have the same W / L ratio.

[0041] In some embodiments, the first input transistor M1 and the second input transistor M2 may be configured to have the same W / L ratio, for example, 1. Tail transistors M15 and M14 may be configured to have the same or different W / L ratios, for example, both having a W / L ratio of 1. Similarly, the first bias reference transistor M12 and the second bias reference transistor M13 may be configured to have a W / L ratio of 1. In some embodiments, the first bias reference transistor M12 and the second bias reference transistor M13 may be selected to not have the same W / L ratio.

[0042] The first load reference transistor M3 can be selected to have a W / L ratio equal to the sum of the W / L ratios of the second load reference transistor M5 and the load mirror transistor M4. In some embodiments, the load mirror transistor M4 can be selected to have a W / L ratio equal to a variable M, where M is greater than 1 (e.g., greater than the minimum transistor size). Furthermore, the first load reference transistor M3 can be selected to have a W / L ratio M+1, and the second load reference transistor M5 can be selected to have a W / L ratio of 1.

[0043] In some embodiments, the current-source transistor M11 and the current-sink transistor M10 may be selected to have the same W / L ratio. The current-source transistor M11 and the current-sink transistor M10 may be selected to have a W / L ratio equal to the variable N, where N is greater than 1. The W / L ratios of M and N can be set independently. For example, in some embodiments, M may be set between approximately 2 and approximately 4, and N may be set between approximately 2 and approximately 4. Any suitable value can be selected based on design requirements, desired performance characteristics, etc.

[0044] The W / L ratio of various transistors can be selected based on desired performance, process parameters, design requirements, etc. For example, the ratio of the reference transistor to the mirror transistor in a current mirror can be selected to determine the ratio of the current to be provided by the mirror transistor to the current measured by the reference transistor. Using the W / L ratio selected as described in the examples above, the following relationship holds:

[0045]

[0046] and (Equation 2)

[0047]

[0048] Where V d Equals positive input Vip or negative input Vin (making 2V) d (equal to differential input signal), g mn It is the transconductance of the NMOS transistor, unless otherwise stated, g mp It is the transconductance of the PMOS transistor, unless otherwise stated, g mpcIt is the transconductance of the transfer transistor M8, and G mota It is the transconductance of OTA 100.

[0049] V op The value of V is determined by solving Kirchhoff's current law (KCL) at node Vop. on It is determined by solving the KCL at node Von (ignoring the influence of the current branch mirror transistor M7), and G mota It is determined by solving the KCL at the output terminal Vout.

[0050] In some implementations, the transconductances of various NMOS transistors can be matched, and the transconductances of various PMOS transistors can be matched. In some implementations, the transconductance of the transfer transistor M8 can be selected such that g mpc =g mp In some implementations, the transconductance of the transfer transistor M8 can be selected to be different from that of g. mp In some implementations, the sizes of various NMOS and PMOS transistors can differ while maintaining matching current densities.

[0051] In the preceding discussion, some terminals of the transistors were described using general terms such as “control node” or “control terminal” instead of base or gate. These general terms are used to emphasize that the circuits described herein can be implemented using a variety of transistor types. Similarly, the terms “source terminal,” “drain terminal,” and “gate terminal” used herein can be replaced by appropriate terms based on the transistor type, such as emitter, collector or base, cathode or anode (e.g., in the case of a diode), etc. Likewise, one or more current mirrors can be configured to supply or draw current. Additionally, other suitable arrangements of PMOS and NMOS transistors (or equivalents of other transistor types) can be used to configure the circuits described above.

[0052] Figure 2 An exemplary embodiment of the second current mirror OTA 200 circuit is shown. In some embodiments, the input circuit 110, tail current source 115, load circuit 120, and output circuit 150 may be the same as described above. The second current mirror OTA 200 may include a dynamically folded current branch circuit 240 and a dynamically biased circuit 230. In some embodiments, the dynamically folded current branch circuit 240 may include the same series arrangement of transistors M7, M8, and M9 as described above, but with one or more transistors having dynamic bias.

[0053] The dynamic bias circuit 230 can be configured to adaptively determine the gate bias voltage Vbpc of the transfer transistor M8 for the dynamic folding current branch circuit 240. The dynamic bias circuit 230 can measure the current through the first input transistor M1, which can then be used to determine the gate voltage Vbpc of the transfer transistor M8. The electrical node coupled to the gate of M8 can be referred to as the Vbpc node.

[0054] In some embodiments, the dynamic bias circuit 230 may include the same series arrangement of transistors M12, M13, and M14 as described above, and a second series arrangement of transistors coupled in parallel to the series arrangement of reference transistors M12, M13 and tail current source 135. For example, the dynamic bias circuit 230 may include a first mirror transistor M16 (also referred to herein as a first bias mirror transistor M16) configured to measure the current through the first input transistor M1, and a current mirror configured to measure the current through the first mirror transistor M16 to bias the Vbpc node.

[0055] In some implementations, the first bias mirror transistor M16 may include a MOSFET, such as a PMOS transistor, whose gate terminal is coupled to the positive reference node Vop and whose source terminal is coupled to the supply voltage Vdd. The first bias mirror transistor M16 may form a current mirror with the first load reference transistor M3, which may be referred to herein as the M3-M16 current mirror. The first bias mirror transistor M16 may mirror the current measured by the first load reference transistor M3.

[0056] The dynamic bias circuit 230 may include a third reference transistor M18 (also referred to herein as the third bias reference transistor M18) series coupled between the common voltage node and the first bias mirror transistor M16. The third bias reference transistor M18 may be configured to measure the current mirrored by the first bias mirror transistor M16. In some embodiments, the third bias reference transistor M18 may include a diode-connected MOSFET, such as an NMOS transistor. The third bias reference transistor M18 may couple its source terminal to the common voltage node and its drain terminal and gate terminal (directly or indirectly) to the drain terminal of the first bias mirror transistor M16.

[0057] In some implementations, the second bias mirror transistor M17 may be configured as a diode-connected MOSFET, such as a PMOS transistor, coupled in series between the first bias mirror transistor M16 and the third bias reference transistor M18 to facilitate the measurement of the current through the first input transistor M1. For example, the second bias mirror transistor may couple its gate and drain terminals to the drain terminal of the third bias reference transistor M18, and its source terminal to the drain terminal of the first bias mirror transistor M16.

[0058] The gate terminal of the third bias reference transistor M18 can control the tail current source 135 to provide a variable current based on the current measured by the third bias reference transistor M18. In some embodiments, the gate terminal of the third bias reference transistor M18 can be coupled to the gate terminal of the tail transistor M14 to form an M18-M14 current mirror, which can provide a variable current through the first bias reference transistor M12 and the second bias reference transistor M13. The variable current through the second bias reference transistor M13 will provide a dynamic bias to the transfer transistor M8. The first bias reference transistor M12 will provide a voltage at the source terminal of the second bias reference transistor M13 that is similar to or the same as the voltage at node Vop. Therefore, the dynamic bias circuit 230 can determine the dynamic gate voltage Vbpc for the transfer transistor M8 based on the change in the positive reference node Vop, and the change in the gate voltage Vbpc is a scaled version of the change in the positive reference node Vop.

[0059] For example, if the positive input signal Vip increases relative to the negative input signal Vin, the voltage at the positive reference node Vop will increase and the voltage at the negative reference node Von will decrease. The current through the first input transistor M1 will decrease, causing the current mirrors M3-M16 and M18-M14 to decrease the measured current. The tail transistor M14 will provide the reduced current, thereby increasing the gate voltage Vbpc of the transfer transistor M8. The simultaneous decrease in the source terminal voltage of the transfer transistor M8 (negative reference node Von) and the increase in the gate voltage Vbpc will cause the transfer transistor M8 to rapidly reduce the amount of current it carries and turn it off. This cuts off most or all of the reverse bias current sent to the current branch reference transistor M9 and therefore to the current sink transistor M10. The supply switching current is given by: N×I M15 .

[0060] Similarly, when the positive input signal Vip decreases relative to the negative input signal Vin, the voltage at the positive reference node Vop decreases and the voltage at the negative reference node Von increases. The gate voltage Vbpc of the transfer transistor decreases, and the source terminal voltage of the transfer transistor M8 increases, causing the transfer transistor M8 to rapidly increase the amount of current it carries. The transfer transistor M8 can carry the entire tail current, and the current sink transistor M10 can carry a larger current. The sinking conversion current is given by the following formula: N×I M15 .

[0061] Therefore, the time required to increase or decrease the current at the output terminal Vout in response to changes in the differential input voltage is reduced, and the slew rate is improved. The additional dynamic bias of the gate terminal of the transfer transistor M8 allows for a faster response to changes in the differential input voltage of smaller or minimally sized devices (e.g., transistors M7 and M8). Furthermore, in some embodiments, all transistors in the dynamic bias circuit 230 may have a small or minimal W / L ratio, for example, a W / L ratio of 1.

[0062] As described above, the dynamic folding current branch circuit 240 may include a reference Figure 1 The same transistor arrangement is described, but with one or more transistors having dynamic bias. As just mentioned above, the transfer transistor may have a dynamic gate voltage Vbpc determined by the dynamic bias circuit 230. In some embodiments, the current-branch mirror transistor M7 may also have its gate terminal dynamically biased.

[0063] Still referencing Figure 2 The current-branch mirror transistor M7 couples its gate terminal to the positive voltage reference node Vop. If the positive input signal Vip increases relative to the negative input signal Vin, the voltage at the positive reference node Vop increases. This reduces the current from the current-branch mirror transistor M7, which in turn reduces the current measured and mirrored by the current mirrors M9-M10 and increases the pull-in current at the output terminal Vout. Similarly, if the positive input signal Vip decreases relative to the negative input signal Vin, the voltage at the positive reference node Vop decreases. This increases the current from the current-branch mirror transistor M7, which in turn increases the current measured and mirrored by the current mirrors M9-M10 and increases the sink current at the output terminal Vout. The current-branch mirror transistor M7 thus provides an adaptive current source controlled by the positive voltage reference node Vop.

[0064] Therefore, the current through the current-branch mirror transistor M7 becomes dynamic based on the differential voltage input signal. When the differential voltage input signal changes in either direction, the current-branch mirror transistor M7 increases the small-signal current response of both. For the same input differential voltage, the increased sourcing and sinking currents at the output contribute to the increase in transconductance of the second current mirror OTA200.

[0065] Using the W / L ratios selected as described above, for example, the corresponding W / L relationship for current mirrors M3-M16 and M3-M7 is (M+1):1, the corresponding W / L relationship for current mirror M3-M4 is (M+1):M, the corresponding W / L relationship for current mirrors M5-M11 and M9-M10 is 1:N, and the corresponding W / L relationship for current mirrors M18-M14 and M13-M8 is 1:1, the following equation holds:

[0066]

[0067] and (Equation 6)

[0068] G mota =g mn ×N; (Equation 7)

[0069] Where V d Equals positive input Vip or negative input Vin (making 2V) d (equal to differential input signal), g mn It is the transconductance of the NMOS transistor, unless otherwise stated, g mp It is the transconductance of the PMOS transistor, unless otherwise stated, g mpc It is the transconductance of the transistor in the M13-M8 current mirror, and G mota It is the transconductance of the second current mirror OTA 200. V op It is determined by solving the KCL at node Vop, (V op -V on The value is determined by solving the KCL at node Von (including the dynamic effects of the current-branch mirror transistor M7 and the transfer transistor M8), and G mota It is determined by solving the KCL at the output terminal Vout.

[0070] Therefore, the second current mirror OTA 200 has increased transconductance, improved conversion rate, and improved stability.

[0071] Figure 3 An exemplary embodiment of the third current mirror OTA 300 circuit is shown. In some embodiments, the input circuit 110, tail current source 115, dynamic bias circuit 230, dynamic folding current branch circuit 240, and output circuit 150 may be related to the above description regarding...Figure 2 The arrangement is identical as described. The third current mirror OTA 300 may include a second load circuit 320 configured to eliminate the transconductance of the corresponding load transistor.

[0072] In some embodiments, the second load circuit may include a negative-side current mirror M3-M4. The second load circuit 320 may also include a positive-side current mirror. For example, the second load circuit 320 may include a second load mirror transistor M6 configured to mirror the current measured by the second load reference transistor M5. This positive-side current mirror may be referred to as the M5-M6 current mirror, and the transistors in the load circuit 320 may be referred to as load transistors.

[0073] The current mirrors M5-M6 can be cross-coupled with the current mirrors M3-M4. In some embodiments, the second load mirror transistor M6 may include a MOSFET, such as a PMOS transistor, whose gate terminal is coupled to the gate terminal of the second load reference transistor M5. The second load mirror transistor M6 may couple its source terminal to the supply voltage Vdd and its drain terminal to the positive reference node Vop. As described above, the second load reference transistor M5 may include a diode-connected transistor, such as a PMOS transistor, coupled between the supply voltage Vdd and the negative reference node Von.

[0074] In some implementations, the W / L ratio of the first load reference transistor M3 and the first load mirror transistor M4 can be selected as M, and the W / L ratio of the second load reference transistor M5 and the second load mirror transistor M6 can be selected as 1. When the W / L relationship of the M3-M4 current mirror is M:M and the W / L relationship of the M5-M6 current mirror is 1:1, the currents through the positive reference node Vop and the negative reference node Von due to the M3-M4 and M5-M6 current mirrors can be determined by the following formula:

[0075] I Vop =Mg dsp V op +Mg mp V o[ +g mp V on +g dsp V op (Equation 8)

[0076] I Von =-[Mg dsp V on +Mg mp V op +g mp V on +g dsp Von (Equation 9)

[0077]

[0078] Where g dsp It is the drain-source conductance of a PMOS transistor.

[0079] Therefore, in the embodiment according to the second load circuit 320, the transconductance g of the load transistors M3, M4, M5, and M6 mp The voltage is eliminated. Due to the high impedance from the load transistors M3, M4, M5, and M6, even if the differential input signal changes only slightly, there will be a large voltage change at the positive reference node Vop and the negative reference node Von.

[0080] Using the W / L ratios selected as described above, for example, the corresponding W / L relationship for current mirrors M3-M16 and M3-M7 is M:1, the corresponding W / L relationship for current mirror M3-M4 is M:M, the corresponding W / L relationship for current mirrors M5-M11 and M9-M10 is 1:N, and the corresponding W / L relationship for current mirrors M5-M6, M18-M14, and M13-M8 is 1:1, the following equation holds:

[0081]

[0082] and (Equation 12)

[0083]

[0084] Where V d Equals positive input Vip or negative input Vin (making 2V) d (equal to differential input signal), g mn It is the transconductance of the NMOS transistor, unless otherwise stated, g mp It is the transconductance of the PMOS transistor, unless otherwise stated, g mpc It is the transconductance of the transistor in the M13-M8 current mirror, and G mota It is the transconductance of OTA 200. V op It is determined by solving the KCL at node Vop (including the current from transistor M6), (V op -V on The value is determined by solving the KCL at node Von (including the dynamic effects of the current-branch mirror transistor M7 and the transfer transistor M8), and G mota It is determined by solving the KCL at the output terminal Vout.

[0085] Therefore, the third current mirror OTA 300 has increased transconductance compared to the second current mirror OTA 200 and the first current mirror OTA 100. In some embodiments, such as when configured as described above, the transconductance of the third current mirror OTA 300 can be approximately twice that of the first current mirror OTA 100. This result is achieved using only a few additional minimal-size transistors.

[0086] For example, by comparing Equations 3 and 13, we can see that the transconductance is approximately doubled. Therefore, the DC gain and bandwidth of the third current mirror OTA300 can also be approximately twice that of the first current mirror OTA100. The gain and bandwidth are increased due to the elimination of the transconductance of the load transistors M3, M4, M5, and M6. In some alternative embodiments, the second load circuit 320 can be used in conjunction with the first current mirror OTA100 circuit or other current mirror OTA circuits without having any connection to the first current mirror OTA100 circuit. Figure 2 The improvements described.

[0087] Figure 4A and Figure 4B Simulation results are shown for exemplary current mirror OTA circuits based on the first exemplary current mirror OTA 100, the second exemplary current mirror OTA 200, and the third exemplary current mirror OTA 300. (Reference) Figure 4A The various exemplary current mirror OTA circuits are simulated using a differential input voltage signal that swings from -200mV to +200mV under typical conditions (e.g., typical temperature, etc.). As shown in the first curve 410, the first current mirror OTA 100 has the minimum amount of negative and positive transition currents, at -226.6μA and +221μA, respectively. As shown in the second curve 420, for the same input voltage swing, the second current mirror OTA 200 improves the negative and positive transition currents, at -266.8μA and +253.4μA, respectively. As shown in the third curve 430, for the same input voltage swing, the third current mirror OTA 300 further improves the negative and positive transition currents, at -340μA and +255.8μA, respectively.

[0088] refer to Figure 4BThe various exemplary current mirror OTA circuits were also simulated to determine other characteristics, such as gain, bandwidth, phase margin, negative and positive switching currents, and rise and fall settling times, under typical and worst-case conditions. The second exemplary current mirror OTA 200 exhibited similar improvements over the first exemplary current mirror OTA 100 under both typical and worst-case conditions. The third exemplary current mirror OTA 300 also exhibited similar improvements over the first exemplary current mirror OTA 100 under both typical and worst-case conditions. The third exemplary current mirror OTA 300 also showed improvements over the second exemplary current mirror OTA 200.

[0089] For example, under worst-case conditions and compared to the first exemplary current mirror OTA 100, the third exemplary current mirror OTA 300 exhibits a 100% improvement in bandwidth, an 18% improvement in positive switching current, a 52% improvement in negative switching current, a 37% improvement in rise settling time, a 47% improvement in fall settling time, and a 5 dB improvement in DC gain. The first exemplary current mirror OTA 100, the second exemplary current mirror OTA 200, and the third exemplary current mirror OTA 300 maintain approximately the same phase margin.

[0090] Therefore, various implementations provide improved current mirror OTA circuits and methods. The improved current mirror OTA circuits provide high bandwidth, low power, and low area Class AB current mirror OTA. Compared to existing current mirror OTA circuits, the improved current mirror OTA circuits offer increased slew rate, gain, transconductance, stability, settling time, and other characteristics with minimal increase in area within the semiconductor substrate. Device size and area can be reduced compared to other methods of increasing the transconductance of current mirror OTA. The improved current mirror OTA circuits described herein can be easily tuned for a variety of applications and design requirements. Other implementations may provide additional benefits and features as needed.

[0091] The various functions shown and described in the various circuits of several exemplary embodiments of the current mirror OTA described herein can be distributed in various suitable configurations among the various components of the current mirror OTA and / or the circuits and components to which the current mirror OTA is connected, and different embodiments can organize various functions and circuits in any number of suitable configurations.

[0092] Unless otherwise stated, the reference to "node" refers to an electrical node. An electrical node may physically exist at one or more locations, for example, as part of a conductive trace extending from or between one or more electrical devices. Terms such as coupling and connection refer to electrical coupling unless otherwise stated, and also to direct and / or indirect coupling, connection, etc., unless otherwise stated.

[0093] The general concepts set forth herein are applicable to any number of alternative but equivalent embodiments. The term “exemplary” is used herein to denote an example, illustration, or description that may have any number of alternatives. Any specific embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other specific embodiments, nor is it intended as a model that must be replicated in other specific embodiments. While several exemplary embodiments have been presented in the foregoing detailed description, it should be understood that numerous alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, various changes may be made to the function and arrangement of the described elements without departing from the scope of the claims and their legal equivalents.

Claims

1. An operational transconductance amplifier, the operational transconductance amplifier comprising: An input circuit, comprising a first input transistor and a second input transistor coupled in parallel, wherein the first input transistor and the second input transistor are controllable according to a differential voltage input signal; A load circuit coupled to the input circuit, the load circuit including a first reference transistor coupled in series with the first input transistor and a second reference transistor coupled in series with the second input transistor, wherein the first reference transistor is configured to measure a first current through the first input transistor and the second reference transistor is configured to measure a second current through the second input transistor; An output circuit, comprising a series-coupled current-source transistor and a current-sinking transistor, wherein the current-source transistor is coupled to the current-sinking transistor at an output terminal; A folded current branch circuit coupled to the output circuit and including a transmission transistor, wherein the transmission transistor is configured to control a third current flowing through the folded current branch circuit based on a bias voltage, and the folded current branch circuit is configured to control a current sinking transistor based on the third current. and A bias circuit coupled to the load circuit and the folded current branch circuit, and configured to determine the bias voltage based on a measured first current.

2. The operational transconductance amplifier of claim 1, wherein the load circuit is coupled to the output circuit, and wherein the current-pull transistor is controllable according to the measured second current.

3. The operational transconductance amplifier according to claim 1, wherein: The folded current branch circuit is coupled to the load circuit; The measured first current determines the first reference voltage at the positive reference node; The folded current branch circuit further includes a first mirror transistor, which is coupled in series with the transmission transistor and is controllable according to a first reference voltage; and The bias voltage is a scaled version of the positive reference node.

4. The operational transconductance amplifier according to claim 3, wherein the bias circuit further comprises: A second mirror transistor coupled to the first reference transistor, wherein the first reference transistor and the second mirror transistor are configured as a first current mirror; A second current mirror is coupled to the second mirror transistor and configured to mirror a fourth current provided by the second mirror transistor. and A third reference transistor, which is coupled in series with the second current mirror and configured to determine the bias voltage based on a fourth current mirrored in the mirror.

5. The operational transconductance amplifier according to claim 4, wherein: Each of the current-pull transistor, the current-sink transistor, and the first reference transistor has a width-to-length (W / L) ratio greater than one; and Each of the transmission transistor, the first mirror transistor, and the second mirror transistor has a W / L ratio approximately equal to one; and The second current mirror includes a plurality of transistors, wherein each of the plurality of transistors in the second current mirror has a W / L ratio approximately equal to one.

6. The operational transconductance amplifier according to claim 4, wherein: The transmission transistor, the first mirror transistor, and the second mirror transistor are minimum size transistors; The second current mirror includes a plurality of transistors, wherein each of the plurality of transistors in the second current mirror is a minimum-size transistor; and The first reference transistor, the current-pull transistor, and the current-sink transistor are larger than the smallest size transistor.

7. The operational transconductance amplifier according to claim 3, wherein the load circuit further comprises a third current mirror and a fourth current mirror, wherein: The third current mirror includes the first reference transistor and the third mirror transistor; The fourth current mirror includes the second reference transistor and the fourth mirror transistor; and The third current mirror and the fourth current mirror are cross-coupled between the power supply voltage terminal, the positive reference node, and the negative reference node.

8. The operational transconductance amplifier according to claim 7, wherein: The first reference transistor and the third mirror transistor have a width-to-length (W / L) ratio greater than one; and The second reference transistor and the fourth mirror transistor have a W / L ratio that is approximately equal to 1.

9. The operational transconductance amplifier of claim 7, wherein the measured second current determines the second reference voltage at the negative reference node.

10. The operational transconductance amplifier according to claim 9, wherein: The first reference transistor is coupled in series between the power supply voltage terminal and the positive reference node; The second reference transistor is coupled in series between the power supply voltage terminal and the negative reference node; The third mirror transistor is coupled in series between the power supply voltage terminal and the negative reference node, wherein the control terminal of the third mirror transistor is coupled to the positive reference node; and The fourth mirror transistor is coupled in series between the power supply voltage terminal and the positive reference node, wherein the control terminal of the fourth mirror transistor is coupled to the negative reference node.

11. The operational transconductance amplifier according to claim 10, wherein: The transmission transistor is coupled in series between the negative reference node and the common voltage node; The first mirror transistor is coupled in series between the supply voltage terminal and the negative reference node; and The current-generating transistor is coupled in series between the power supply voltage terminal and the output terminal, wherein the control terminal of the current-generating transistor is coupled to the negative reference node.

12. An operational transconductance amplifier, the operational transconductance amplifier comprising: An input circuit configured to generate a positive branch current based on a positive differential input voltage and a negative branch current based on a negative differential input voltage; A load circuit coupled to the input circuit and configured to measure the positive branch current and the negative branch current; A bias circuit coupled to the load circuit and configured to determine a dynamic bias voltage based on the measured negative branch current; An output circuit coupled to the load circuit, wherein the output circuit includes a push-pull transistor pair and is configured to supply current to the output terminal based on a measured positive branch current; and A folded current branch circuit is coupled to the bias circuit and the output circuit, and is configured to control the output circuit to draw current from the output terminal based on the dynamic bias voltage.

13. The operational transconductance amplifier of claim 12, wherein the folded current branch circuit comprises: A first mirror transistor is configured to provide an adaptive current to the folded current branch circuit, wherein the first mirror transistor is controlled based on a measured negative branch current. and A transmission transistor, which is coupled in series with the first mirror transistor and configured to adjust the amount of the adaptive current based on the dynamic bias voltage, wherein the current draw performed by the output circuit is controlled according to the adjusted adaptive current.

14. The operational transconductance amplifier of claim 13, wherein the load circuit includes a positive branch current mirror and a negative branch current mirror, wherein the positive branch current mirror and the negative branch current mirror are cross-coupled.

15. The operational transconductance amplifier of claim 14, wherein the load circuit includes a positive reference node and a negative reference node, wherein: The load circuit is configured to determine a first reference voltage at the positive reference node based on the measured negative branch current; The load circuit is configured to determine a second reference voltage at the negative reference node based on the measured positive branch current; The positive branch current mirror includes: A first reference transistor, wherein the first reference transistor is coupled in series between the supply voltage terminal and the positive reference node; and A second mirror transistor, the second mirror transistor being series-coupled between the supply voltage terminal and the negative reference node, wherein the control terminal of the second mirror transistor is coupled to the positive reference node; and The negative branch current mirror includes: A second reference transistor, wherein the second reference transistor is coupled in series between the supply voltage terminal and the negative reference node; and A third mirror transistor is coupled in series between the power supply voltage terminal and the positive reference node, wherein the control terminal of the third mirror transistor is coupled to the positive reference node.

16. The operational transconductance amplifier according to claim 15, wherein: The first mirror transistor, the transmission transistor, the first reference transistor, and the second mirror transistor are minimum size transistors; and The push-pull transistor pair, the second reference transistor, and the third mirror transistor are larger than the smallest size transistor.

17. An operational transconductance amplifier, the operational transconductance amplifier comprising: An input circuit includes a first input transistor and a second input transistor coupled in parallel, wherein the gate of the first input transistor is configured to receive a negative differential input voltage and the gate of the second input transistor is configured to receive a positive differential input voltage; A load circuit coupled to the input circuit, the load circuit including a negative branch current mirror and a positive branch current mirror, the negative branch current mirror being configured to measure the negative branch current through the first input transistor, and the positive branch current mirror being configured to measure the positive branch current through the second input transistor, wherein the negative branch current mirror and the positive branch current mirror are cross-coupled. A folded current branch circuit, coupled to an output circuit, wherein: the folded current branch circuit includes a transfer transistor configured to adjust an adaptive current amount based on a bias voltage; and the folded current branch circuit is configured to control the output circuit to draw output current at an output terminal based on the adjusted adaptive current; and A bias circuit coupled to the load circuit and the folded current branch circuit, and configured to determine the bias voltage based on the measured negative branch current.

18. The operational transconductance amplifier of claim 17, wherein the folded current branch circuit further comprises a first mirror transistor configured to provide the adaptive current to the folded current branch circuit, and wherein the first mirror transistor is controlled according to a measured negative branch current.

19. The operational transconductance amplifier of claim 18, wherein the output circuitry includes a push-pull transistor pair configured to supply current to the output terminal based on a measured positive branch current.

20. The operational transconductance amplifier according to claim 19, wherein: The first mirror transistor and the transmission transistor are minimum size transistors; The push-pull transistor is larger than the smallest size transistor; The negative branch current mirror includes components larger than the smallest size transistor; and The positive branch current mirror includes a minimum-size transistor.

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