An ultra-low power consumption high-performance LDO circuit and a control method thereof

Abstract

The application discloses an ultra-low-power high-performance LDO circuit and a control method thereof, which comprises an LDO core circuit, a band-gap reference circuit, an RC series circuit and a static current detection circuit, wherein the band-gap reference circuit and the static current detection circuit are connected with the LDO core circuit respectively; in the static current detection circuit, when the detected voltage is less than a preset first voltage, the reference voltage is sampled and saved in a holding capacitor, the LDO core circuit is in a non-working state, a constant current source is discharged, after a preset time, the voltage on the holding capacitor is reduced to be less than a preset second reference voltage, the LDO core circuit enters a working state, the holding capacitor is charged, and after the voltage is recovered, the LDO core circuit enters the non-working state. Through the static current detection circuit, the circuit enters a hibernation working state without finding a load circuit, and thus an energy-saving working target is achieved. The application can be widely applied in the field of LDO circuits.

Description

Technical Field

[0001] This invention relates to the field of LDO circuits, and more particularly to an ultra-low power, high-performance LDO circuit and its control method. Background Technology

[0002] Low-dropout linear regulators (LDOs), as an important module in power management integrated circuits, typically convert fluctuating input power supply voltages into a clean and stable voltage, providing power to various noise-sensitive analog or radio frequency circuits. LDOs have received widespread attention in academic and industrial circles both domestically and internationally as a crucial component of power management integrated circuit chips. However, most current LDO circuits do not address the no-load quiescent current of the LDO, resulting in unnecessary power consumption and impacting the battery life of electronic products. Summary of the Invention

[0003] In view of this, in order to solve the technical problem that existing LDO circuits do not limit the quiescent current under no-load conditions, this invention proposes an ultra-low power, high-performance LDO circuit, including an LDO core circuit, a bandgap reference circuit, an RC series circuit, and a quiescent current detection circuit. The bandgap reference circuit and the quiescent current detection circuit are respectively connected to the LDO core circuit, wherein:

[0004] The static current detection circuit includes a first comparator, a second comparator, a sensing MOSFET, a logic control signal module, a holding capacitor, a sensing resistor, a first constant current source, a first switch, and a second switch. The positive input terminal of the first comparator is connected to a first voltage terminal. The negative input terminal of the first comparator, the first terminal of the sensing resistor, and the drain of the sensing MOSFET are connected. The output terminal of the first comparator is connected to the first terminal of the logic control module. The first terminal of the first switch is connected to the first voltage terminal. The second terminal of the first switch, the positive input terminal of the second comparator, the first terminal of the second switch, and the first terminal of the holding capacitor are connected. The negative input terminal of the second comparator is connected to a second voltage terminal. The output terminal of the second comparator is connected to the second terminal of the logic control signal module. The output terminal of the logic control signal module is connected to the LDO core circuit. The second terminal of the second switch is connected to the first terminal of the first constant current source. The second terminal of the first constant current source, the second terminal of the holding capacitor, and the second terminal of the sensing resistor are connected and grounded.

[0005] In some embodiments, an RC series circuit and a second current source are also included. The first end of the RC series circuit, the first end of the second current source and the LDO core circuit are connected, the second end of the RC series circuit is connected to the Vout terminal and the second end of the second current source is grounded.

[0006] In some embodiments, the LDO core circuit includes a feedforward ripple cancellation circuit, a buffer, a first amplifier, a first resistor, a second resistor, a power transistor, a first MOSFET, and a second MOSFET. The first terminal of the feedforward ripple cancellation circuit, the drain of the first MOSFET, and the gate of the power transistor are connected. The second terminal of the feedforward ripple cancellation circuit is connected to the output terminal of the first amplifier. The third terminal of the feedforward ripple cancellation circuit and the source of the power transistor are both connected to the Vin terminal. The gate of the first MOSFET is connected to the output terminal of the enable control module. The first terminal of the buffer is connected to the negative input terminal of the first amplifier. The second terminal of the buffer is connected to the bandgap reference circuit. The drain of the power transistor, the first terminal of the first resistor, and the first terminal of the RC parallel circuit are connected. The positive input terminal of the first amplifier, the second terminal of the first resistor, and the first terminal of the second resistor are connected. The second terminal of the second resistor is connected to the drain of the second MOSFET. The source of the second MOSFET is grounded. The gate of the second MOSFET is connected to the output terminal of the enable control module.

[0007] In some embodiments, the feedforward ripple cancellation circuit includes a first capacitor, a third resistor, a fourth resistor, a second amplifier, a fifth resistor, a sixth resistor, a seventh resistor, and a third amplifier. The first terminal of the first capacitor and the first terminal of the third resistor are connected together and connected to the Vin terminal. The second terminal of the first capacitor, the second terminal of the third resistor, the first terminal of the fourth resistor, and the negative input terminal of the second amplifier are connected together. The second terminal of the fourth resistor, the output terminal of the second amplifier, and the first terminal of the fifth resistor are connected together. The second terminal of the fifth resistor, the first terminal of the sixth resistor, the first terminal of the seventh resistor, and the negative input terminal of the third amplifier are connected together. The second terminal of the sixth resistor, the output terminal of the third amplifier, and the gate of the power transistor are connected together. The second terminal of the seventh resistor is grounded.

[0008] In this embodiment, feedforward ripple cancellation technology is used to further improve the power supply rejection ratio performance.

[0009] In some embodiments, the bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a compensation circuit, wherein:

[0010] A compensation circuit is added to the bandgap reference core circuit to improve the output voltage accuracy of the bandgap reference circuit.

[0011] A startup circuit is used to remove the degeneracy state under zero current conditions.

[0012] In this embodiment, since the bandgap reference circuit has no input signal, it may enter a zero-current degeneracy state and fail to function properly. Therefore, a self-starting circuit must be introduced to remove the degeneracy state. The reference voltage core circuit is used to achieve an output reference voltage signal with minimal temperature dependence. The output voltage magnitude and temperature drift coefficient, caused by factors such as process angle and temperature, will deviate. The compensation circuit will correct this deviation, thereby obtaining a high-precision output reference voltage signal.

[0013] In some embodiments, an active low-pass filter is also included, and the output of the bandgap reference circuit is connected to the LDO circuit through the active low-pass filter.

[0014] In this embodiment, the bandgap reference based on active filter RC circuit technology avoids the increase in chip area caused by adding resistors and capacitors, as well as the use of additional chip pins and external resistors and capacitors.

[0015] In some embodiments, an over-temperature protection circuit and an over-current protection circuit are also included, both of which are connected to the gate of the power transistor.

[0016] In this embodiment, the over-temperature protection and over-current protection functions of the LDO chip are implemented through these two additional circuits.

[0017] In the static current detection circuit, when the detected voltage is less than a preset first voltage, the logic control signal module sends a control signal to sample the reference voltage and store it in the holding capacitor, causing the LDO core circuit to be in a non-working state. The first constant current source begins to discharge. After a preset time, the voltage on the holding capacitor drops to less than a preset second reference voltage, and the LDO core circuit re-enters the working state, charging the holding capacitor. After the voltage of the holding capacitor recovers, the LDO core circuit enters the non-working state again.

[0018] Based on the above scheme, this invention provides an ultra-low power, high-performance LDO circuit and its control method. By introducing a static current detection circuit, the design goal of an LDO circuit with a typical static current value less than a preset value under no-load conditions is achieved without affecting the stability of the LDO core circuit loop. The LDO circuit solution based on feedforward ripple cancellation technology effectively improves the PSR in the LDO core circuit loop frequency band. Furthermore, a simple noise reduction RC network is used to achieve the design goal of low output voltage noise, and the noise reduction network can also effectively reduce the PSR of the LDO in the low-frequency domain. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating the structural principle of an ultra-low power, high-performance LDO circuit according to the present invention.

[0020] Figure 2 This is a partial circuit diagram of an ultra-low power, high-performance LDO circuit according to the present invention.

[0021] Figure 3 This is the timing diagram of the LDO circuit of this invention;

[0022] Figure 4 This is a schematic diagram of an LDO circuit incorporated into an RC series circuit according to a specific embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the loop gain of the LDO varying with frequency in a specific embodiment of the present invention;

[0024] Figure 6 This is a specific embodiment of the LDO circuit of the present invention, which is a coupling circuit from the input voltage ripple to the output terminal.

[0025] Figure 7 This invention relates to the impact of the input voltage ripple of each path in the LDO circuit on the overall PSR of the LDO in a specific embodiment of the invention.

[0026] Figure 8 This is a circuit diagram of a wideband high power supply rejection LDO according to a specific embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of the mathematical model of a wideband high power supply rejection ratio LDO circuit according to a specific embodiment of the present invention;

[0028] Figure 10 This is a circuit diagram of a bandgap reference circuit according to a specific embodiment of the present invention;

[0029] Figure 11 (a) is a partial circuit diagram of the overcurrent protection circuit in a specific embodiment of the present invention; Figure 11 (b) is a partial circuit diagram of the over-temperature protection of the present invention.

[0030] Reference numerals: 1. Logic control signal module; Comp1. First comparator; Comp2. Second comparator; Msen. Sensing MOSFET; Rsen. Sensing resistor; CL. Holding capacitor; I1. First constant current source; M1. First MOSFET; Mp. Power transistor; M2. Second MOSFET; Rf1. First resistor; Rf2. Second resistor; C1. First capacitor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; R7. Seventh resistor; U1. First amplifier; U2. Second amplifier; U3. Third amplifier. Detailed Implementation

[0031] In applications, wide load range, high power supply rejection (PSR), low voltage drop, low quiescent current, low noise, small size, and low cost are important performance indicators for LDOs.

[0032] There is currently no LDO chip in the technology that meets the following specifications: high power supply rejection for radio frequency signals, maximum load current of 200mA, ultra-low quiescent current under no-load conditions, and low output noise, while also incorporating over-temperature protection, over-current protection, and enable control. The technical problems this invention aims to solve include: a high-precision bandgap reference voltage circuit, a wideband high power supply rejection LDO implementation circuit, a low-noise LDO circuit, and a circuit scheme for achieving a quiescent current of less than 5μA under no-load conditions.

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] It should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0035] It should be understood that the terms "system," "apparatus," "unit," and / or "module" used in this application are a method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0036] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "a," and / or "the" are not specifically singular and may include the plural. Generally, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. An element defined by the phrase "comprising an..." does not exclude the presence of other identical elements in the process, method, product, or apparatus that includes the element.

[0037] In the description of the embodiments of this application, "a plurality of" refers to two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0038] Furthermore, flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, the steps can be processed in reverse order or simultaneously. Additionally, other operations can be added to these processes, or one or more steps can be removed from them.

[0039] Reference Figure 1 This is a schematic diagram of an embodiment of an ultra-low power, high-performance LDO circuit according to the present invention. It mainly consists of an LDO core circuit, a bandgap reference voltage circuit, an enable control logic circuit, an over-temperature protection circuit, an over-current protection circuit, and a static current detection circuit and its control circuit under no-load conditions. The bandgap reference voltage circuit generates a 1.2V reference voltage, which, after passing through an internal buffer, generates a reference voltage of 1.2–5.2V, similar in magnitude to the output voltage. This ensures that the loop gain of the LDO core circuit, composed of the power transistor Mp, error amplifier, and feedback resistor, is 0dB. This reduces the design difficulty of the LDO circuit loop stability, improves circuit stability, and thus provides necessary assurance for the development of high-performance LDO chips.

[0040] Reference Figure 2 This is a circuit diagram of an ultra-low power, high-performance LDO circuit according to the present invention, including an LDO core circuit, a bandgap reference circuit, an RC series circuit, and a quiescent current detection circuit. The bandgap reference circuit and the quiescent current detection circuit are respectively connected to the LDO core circuit, wherein:

[0041] The static current detection circuit includes a first comparator, a second comparator, a sensing MOSFET, a logic control signal module, a holding capacitor, a sensing resistor, a first constant current source, a first switch, and a second switch. The positive input terminal of the first comparator is connected to a first voltage terminal. The negative input terminal of the first comparator, the first terminal of the sensing resistor, and the drain of the sensing MOSFET are connected. The output terminal of the first comparator is connected to the first terminal of the logic control module. The first terminal of the first switch is connected to the first voltage terminal. The second terminal of the first switch, the positive input terminal of the second comparator, the first terminal of the second switch, and the first terminal of the holding capacitor are connected. The negative input terminal of the second comparator is connected to a second voltage terminal. The output terminal of the second comparator is connected to the second terminal of the logic control signal module. The output terminal of the logic control signal module is connected to the LDO core circuit. The second terminal of the second switch is connected to the first terminal of the first constant current source. The second terminal of the first constant current source, the second terminal of the holding capacitor, and the second terminal of the sensing resistor are connected and grounded.

[0042] In this embodiment, the detection current magnitude can be selected by setting the ratio of Msen to Mp, and the detection voltage V1 can be determined by selecting an appropriate Rsen value. V1 is compared with the reference voltage Vref1 to determine whether the LDO has entered a no-load state. The reference voltage Vref used in this invention is 600mV. Comparator Comp1 is always in the working state, and its total current is approximately 300nA. When the voltage V1 is less than Vref1, the logic control circuit generates a control signal to first sample and store the reference voltage in CL, and then put the LDO core circuit into a non-working off state. After that, a constant current of approximately 20nA begins to discharge. The magnitude of the discharge current and the capacitance value are used together to determine the duration of the LDO core circuit entering the sleep state and the circuit being in the off state. This project plans to set the duration to 1.5s. After 1.5s, the voltage V2 on CL drops to less than Vref2, the LDO core circuit re-enters the working state, charges CL, and after the CL voltage recovers, the LDO core circuit enters the non-working state again. The timing relationship is as follows: Figure 3 During this process, the LDO core circuit operates for tens of μs, therefore the average quiescent current I under no-load conditions is... Q,AVG It can be represented as:

[0043]

[0044] Assume when t on =39μs,t off =1.5s, I Q,on =35μA, I Q,off =740nA, from which the average current I can be obtained. Q,AVG =741nA. During the dormant state of this project, each t on +t off The time interval will detect whether there is a load circuit. If no load circuit is detected, the circuit enters a sleep state, thereby achieving the goal of energy saving. In summary, with proper design, LDO chips can achieve the goal of ultra-low quiescent current under no-load conditions.

[0045] Furthermore, this circuit technology achieves ultra-low power consumption under no-load conditions through logic control, without affecting the loop stability of the LDO core circuit, thus greatly improving the probability of successful LDO chip circuit design.

[0046] In some feasible embodiments, an RC series circuit is also included, wherein the first end of the RC series circuit is connected to the LDO core circuit and the second end of the RC series circuit is connected to the Vout terminal.

[0047] Specifically, the main noise sources of an LDO are its internal reference voltage source and error amplifier. This invention proposes to use an active RC filter to achieve a low-noise reference voltage. However, the noise of the error amplifier and the residual noise of the reference source will still be amplified by the AC closed-loop gain, and the LDO output voltage noise changes proportionally to the output voltage.

[0048] Reducing the noise gain of the error amplifier to prevent the output noise from changing significantly with increasing output voltage is the basic idea behind achieving a low-noise LDO. Fortunately, for LDOs with controllable outputs, the feedback point is easy to design. (Refer to...) Figure 4 A simple passive RC circuit (consisting of capacitor Cc and resistor Rc) is used on the basic LDO structure. This passive RC circuit network, through proper design, can achieve low-noise LDO design, such as... Figure 5 The figure shows the open-loop AC gain, closed-loop DC gain, and noise loop gain of the LDO as a function of frequency after using a passive RC network. It can be seen that the noise AC gain is significantly reduced compared to the DC gain over a large frequency band, thus the reference voltage noise and error amplifier noise are hardly amplified. Specifically, a suitable resistor Rc can make the gain at high frequencies approximately 1.1, and a suitable C1 sets the low-frequency zero close to the origin, thereby reducing 1 / f noise. By using this RC network, the design goal of a low-noise LDO is achieved without affecting the stability of the LDO loop.

[0049] The following is an analysis of the basic principles of LDOs and the design challenges of PSR:

[0050] like Figure 6 The diagram shows the basic principle of LDO circuit power supply ripple coupling to the output voltage, and the relationship between each coupling path (①, ②, ③ and ④) and the overall PSR is as follows. Figure 7 As shown, the high-frequency domain PSR performance is mainly limited by the dominant pole of the error amplifier, the size of the equivalent inductance, the size of the equivalent resistance, and the size of the external capacitance. Figure 6 and 7 As shown, the low-frequency domain PSR is mainly determined by the PSR performance of the reference voltage. Path ① is determined by the main loop control of the LDO core circuit; path ② is determined by the finite transconductance of the power transistor Mp, and with the use of advanced processes, the low-frequency characteristics of this path become more prominent. Path ③ is a result of the error amplifier PSR; and path ④ is the influence of the finite PSR of the bandgap reference voltage on the output voltage PSR. Figure 7It can be seen that paths ③ and ④ will be suppressed by paths ① and ② together. However, the low PSR of the reference power supply voltage in the low-frequency domain will reduce the low-frequency PSR of the total LDO circuit output voltage. Usually, the output voltage Vout is equal to the reference voltage Vref, so the low-frequency PSR of path ③ is similar to the PSR characteristics of the main loop of the LDO.

[0051] In summary, the design challenge of a broadband high PSR LDO in this project is how to improve the low-frequency PSR of the reference voltage, thereby avoiding the influence of path ④ on the low-frequency PSR of the LDO. The most important design challenge is how to optimize paths ① and ② to achieve the design goal of a broadband high PSR LDO.

[0052] In some feasible embodiments, the LDO core circuit includes a feedforward ripple cancellation circuit, a buffer, a first amplifier, a first resistor, a second resistor, a power transistor, a first MOSFET, and a second MOSFET. The first terminal of the feedforward ripple cancellation circuit, the drain of the first MOSFET, and the gate of the power transistor are connected. The second terminal of the feedforward ripple cancellation circuit is connected to the output terminal of the first amplifier. The third terminal of the feedforward ripple cancellation circuit and the source of the power transistor are both connected to the Vin terminal. The gate of the first MOSFET is connected to the output terminal of the enable control module. The first terminal of the buffer is connected to the negative input terminal of the first amplifier. The second terminal of the buffer is connected to the bandgap reference circuit. The drain of the power transistor, the first terminal of the first resistor, and the first terminal of the RC series network are connected. The positive input terminal of the first amplifier, the second terminal of the first resistor, and the first terminal of the second resistor are connected. The second terminal of the second resistor is connected to the drain of the second MOSFET. The source of the second MOSFET is grounded. The gate of the second MOSFET is connected to the output terminal of the enable control module.

[0053] A schematic diagram of the LDO core circuit is shown below. Figure 8 .

[0054] As mentioned earlier, the PSR of an LDO circuit is mainly determined by paths ①, ②, ③, and ④, especially paths ① and ②, which are the main factors determining the PSR performance of the LDO across the entire frequency domain. Furthermore, based on... Figure 6 The transfer function of the LDOs shown, generated by paths ① and ②, can be expressed as:

[0055]

[0056] Among them, g m,Mp and r ds,Mp These are the transconductance and channel resistance of the power transistor Mp, respectively, and Z. L To determine the overall output equivalent impedance without considering the feedback resistor, A e0 and ω eThese represent the DC gain and dominant pole of the error amplifier, respectively. The low-frequency PSR performance of an LDO mainly depends on the feedback loop gain A. e0 (R f2 / (R f1 +R f2 As the frequency increases, the dominant pole of the error amplifier reduces the feedback loop gain, thus the PSR of the LDO begins to decrease due to paths ① and ②. If the equivalent inductance (ESL) and equivalent resistance (ESR) of the external capacitors themselves are disregarded, the LDO's transfer function in the high-frequency domain causes the input ripple to couple to ground through the output voltage due to the external capacitors. However, due to the equivalent resistance and inductance of the external capacitors themselves, the ripple coupling from the input ripple to the output voltage may increase. The transfer function from the input signal to the output voltage generated by paths ③ and ④ can be expressed as:

[0057]

[0058] Z tot (s)=Z L (s) / / r ds,M,p / / (R f1 +R f2 )

[0059] Among them, PSRR e The power supply rejection ratio (PSR) of the error amplifier. BG This is for the power supply suppression of the bandgap reference voltage circuit. As shown in the equation above, paths ③ and ④ amplify the power supply suppression ratio of the error amplifier and the bandgap reference voltage circuit with a certain gain, which is the feedback coefficient of the resistor network [R2 / (R1+R2)]. In the high-frequency domain, the dominant pole of the error amplifier makes the transfer function approximately zero; therefore, the ripple generated in the output voltage by the error amplifier and the bandgap reference circuit in the high-frequency domain is effectively suppressed.

[0060] In summary, this project plans to use Huahong's 0.35μm CMOS process to design and implement the LDO chip circuit. The error amplifier exhibits good power supply rejection ratio in the low-frequency domain, and the bandgap reference voltage circuit will employ... Figure 10 The circuit structure and active low-pass filter shown achieve good low-frequency power supply rejection ratio (PSR) performance. Paths ③ and ④ have relatively little impact on the PSR design of the LDO in this project. Therefore, the wideband, high PSR design of the LDO circuit in this project will primarily consider paths ① and ②. The proposed LDO circuit structure is as follows: Figure 8 As shown, based on the traditional LDO structure, feedforward ripple cancellation technology is used to further improve the power supply rejection ratio performance.

[0061] Feedforward ripple cancellation technology mainly consists of a feedforward amplifier and an adder, such as Figure 8As shown. When the finite channel resistance of the power transistor Mp is not considered, the input signal ripple is transmitted to one end of the adder through the feedforward amplifier, and then coupled to the gate of the power transistor Mp by the adder. When the input and the gate of the power transistor change synchronously, the current of the power transistor will remain constant, thus ensuring that the current to the load and the resistor feedback network remains constant, thereby obtaining a stable output Vout. Actual LDO circuit design considers the finite channel resistance of the power transistor Mp, simply increasing the ripple amplitude of the power transistor gate. The increased ripple will offset the change in the finite channel resistance. Based on the above basic principle, this project will obtain an LDO circuit with a high PSR over a wider bandwidth, while in the high-frequency domain, a passive RC network circuit based on an off-chip 4.7μF capacitor will be used to effectively suppress the input ripple. Furthermore, Figure 9 This is a schematic diagram of the mathematical model of the wideband high power supply rejection ratio LDO circuit of the present invention.

[0062] As some feasible preferred embodiments, the bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a compensation circuit.

[0063] As some feasible preferred embodiments, an active low-pass filter is used instead of a traditional passive RC low-pass filter.

[0064] As some feasible preferred embodiments, it also includes an over-temperature protection circuit and an over-current protection circuit.

[0065] The overcurrent protection circuit is implemented using a new voltage comparator;

[0066] The over-temperature protection circuit, over-current protection circuit, and enable control logic all control the opening and closing of the LDO circuit. The enable control logic controls the quiescent current when the LDO is operating under light load. The over-temperature and over-current protection circuits ensure the chip operates normally and prevent it from burning out under extreme conditions. The over-temperature protection circuit and over-current protection circuit are described below. Figure 11 As shown in (a) and (b).

[0067] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A low-power, high-performance LDO circuit, characterized in that, It includes an LDO core circuit, a bandgap reference circuit, an RC series circuit, and a quiescent current sensing circuit. The bandgap reference circuit and the quiescent current sensing circuit are respectively connected to the LDO core circuit, wherein: The static current detection circuit includes a first comparator, a second comparator, a sensing MOSFET, a logic control signal module, a holding capacitor, a sensing resistor, a first constant current source, a first switch, and a second switch. The positive input terminal of the first comparator is connected to a first voltage terminal. The negative input terminal of the first comparator, the first terminal of the sensing resistor, and the drain of the sensing MOSFET are connected. The output terminal of the first comparator is connected to the first terminal of the logic control module. The first terminal of the first switch is connected to the first voltage terminal. The second terminal of the first switch, the positive input terminal of the second comparator, the first terminal of the second switch, and the first terminal of the holding capacitor are connected. The negative input terminal of the second comparator is connected to a second voltage terminal. The output terminal of the second comparator is connected to the second terminal of the logic control signal module. The output terminal of the logic control signal module is connected to the LDO core circuit. The second terminal of the second switch is connected to the first terminal of the first constant current source. The second terminal of the first constant current source, the second terminal of the holding capacitor, and the second terminal of the sensing resistor are connected and grounded.

2. The ultra-low power, high-performance LDO circuit according to claim 1, characterized in that, It also includes an RC series circuit and a second current source. The first end of the RC series circuit and the first end of the second current source are connected to the LDO core circuit. The second end of the RC series circuit is connected to the Vout terminal, and the second end of the second current source is grounded.

3. The ultra-low power, high-performance LDO circuit according to claim 2, characterized in that, The core circuit of the LDO includes a feedforward ripple cancellation circuit, a buffer, a first amplifier, a first resistor, a second resistor, a power transistor, a first MOSFET, and a second MOSFET. The first terminal of the feedforward ripple cancellation circuit, the drain of the first MOSFET, and the gate of the power transistor are connected. The second terminal of the feedforward ripple cancellation circuit is connected to the output terminal of the first amplifier. The third terminal of the feedforward ripple cancellation circuit and the source of the power transistor are both connected to the Vin terminal. The gate of the first MOSFET is connected to the output terminal of the enable control module. The first terminal of the buffer is connected to the negative input terminal of the first amplifier. The second terminal of the buffer is connected to the bandgap reference circuit. The drain of the power transistor, the first terminal of the first resistor, and the first terminal of the RC parallel circuit are connected. The positive input terminal of the first amplifier, the second terminal of the first resistor, and the first terminal of the second resistor are connected. The second terminal of the second resistor is connected to the drain of the second MOSFET. The source of the second MOSFET is grounded. The gate of the second MOSFET is connected to the output terminal of the enable control module.

4. The ultra-low power, high-performance LDO circuit according to claim 3, characterized in that, The feedforward ripple cancellation circuit includes a first capacitor, a third resistor, a fourth resistor, a second amplifier, a fifth resistor, a sixth resistor, a seventh resistor, and a third amplifier. The first terminal of the first capacitor and the first terminal of the third resistor are connected together and connected to the Vin terminal. The second terminal of the first capacitor, the second terminal of the third resistor, the first terminal of the fourth resistor, and the negative input terminal of the second amplifier are connected together. The second terminal of the fourth resistor, the output terminal of the second amplifier, and the first terminal of the fifth resistor are connected together. The second terminal of the fifth resistor, the first terminal of the sixth resistor, the first terminal of the seventh resistor, and the negative input terminal of the third amplifier are connected together. The second terminal of the sixth resistor, the output terminal of the third amplifier, and the gate of the power transistor are connected together. The second terminal of the seventh resistor is grounded.

5. The ultra-low power, high-performance LDO circuit according to claim 2, characterized in that, The bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and a compensation circuit, wherein: A compensation circuit is added to the bandgap reference core circuit to improve the output voltage accuracy of the bandgap reference circuit. A startup circuit is used to remove the degeneracy state under zero current conditions.

6. The ultra-low power, high-performance LDO circuit according to claim 2, characterized in that, It also includes an active low-pass filter, the output of which is connected to the LDO circuit via the active low-pass filter.

7. The ultra-low power, high-performance LDO circuit according to claim 1, characterized in that, It also includes an over-temperature protection circuit and an over-current protection circuit, both of which are connected to the gate of the power transistor.

8. The ultra-low power, high-performance LDO circuit according to claim 1, characterized in that, The control method is as follows: In the static current detection circuit, when the detected voltage is less than a preset first voltage, the logic control signal module sends a control signal to sample the reference voltage and store it in the holding capacitor, causing the LDO core circuit to be in a non-working state. The first constant current source begins to discharge. After a preset time, the voltage on the holding capacitor drops to less than a preset second reference voltage, and the LDO core circuit re-enters the working state, charging the holding capacitor. After the voltage of the holding capacitor recovers, the LDO core circuit enters the non-working state again.

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