High-frequency pulse interference detection and suppression method

Abstract

The embodiment of the invention provides a high-frequency pulse interference detection and suppression method. The method comprises the following steps: extracting a rising edge of an input signal through a rising edge extraction unit; modulating each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude through a first modulation unit; filtering the pulse wave through a filtering unit, and converting the frequency information of the input signal into a voltage signal; comparing the voltage signal with a fixed level through an over-frequency judgment unit, and outputting a judgment result; the over-frequency judgment unit has a hysteretic characteristic; carrying out duration prolonging processing on the judgment result through a second modulation unit, and outputting an over-frequency signal; and controlling the conduction state of the suppression circuit gating switch according to the level of the over-frequency signal. According to the invention, the problems of manufacturing precision and consistency caused by the need of extremely small current and capacitance are avoided, the accurate detection of MHz-level high-frequency interference is realized, the top-speed transmission of signals without interference is ensured, and the unification of high reliability and low delay is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for detecting and suppressing high-frequency pulse interference. Background Technology

[0002] With the rapid development of semiconductor technology, the feature size of integrated circuits is constantly shrinking and the operating frequency is increasing. While this trend improves chip performance, it also brings increasingly severe signal integrity and power integrity issues. Considering scenarios such as aerospace and electronic warfare, severe high-frequency pulse interference has become one of the key bottlenecks affecting the performance, stability, and reliability of advanced integrated circuits. Although on-chip decoupling capacitors are a common and effective suppression method, they also have limitations such as non-adjustable parasitic parameters, area, and impedance. Therefore, detecting and suppressing high-frequency pulse interference within the integrated circuit is more suitable for complex application scenarios.

[0003] In existing technologies for high-frequency interference detection within integrated circuits, a typical approach involves using a constant current source to charge a constant capacitor to generate a fixed reference frequency signal, which is then compared to the input signal frequency. However, this approach has significant drawbacks when dealing with megahertz (MHz) level high-frequency interference: First, the extremely small charging current and capacitance value required for detecting high-frequency signals are difficult to guarantee in terms of accuracy and consistency during manufacturing, leading to unstable detection circuit performance. Second, if the circuit is required to activate protection only after the input signal frequency continuously exceeds a set value, complex counting or timing circuits are needed, significantly increasing system complexity and chip area. For these reasons, existing integrated circuit solutions struggle to accurately detect MHz-level high-frequency interference signals and cannot achieve adaptive switching between operating and non-operating modes for the suppression circuit. Often, to suppress interference, a continuous signal delay must be introduced, sacrificing the circuit's transmission speed under normal operating conditions. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method for detecting and suppressing high-frequency pulse interference. One or more embodiments of this application also relate to a high-frequency pulse interference suppression device for integrated circuits, a computing device, a computer-readable storage medium, and a computer program, to address the technical deficiencies existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a method for detecting and suppressing high-frequency pulse interference, applied to a high-frequency pulse interference detection and suppression circuit. The high-frequency pulse interference detection and suppression circuit includes a high-frequency interference detection unit and a high-frequency interference suppression unit. The high-frequency interference detection unit includes a rising edge extraction unit, a first modulation unit, a filtering unit, an over-frequency judgment unit, and a second modulation unit connected in sequence. The high-frequency interference suppression unit includes a suppression circuit selection switch and a high-frequency disturbance suppression unit, wherein the suppression circuit selection switch includes a first selection switch and a second selection switch.

[0006] The method includes:

[0007] The rising edge of the input signal is extracted by the rising edge extraction unit.

[0008] The first modulation unit modulates each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude.

[0009] The pulse wave is filtered by the filtering unit, and the frequency information of the input signal is converted into a voltage signal.

[0010] The over-frequency judgment unit compares the voltage signal with a fixed level and outputs the judgment result; the over-frequency judgment unit has hysteresis characteristics.

[0011] The second modulation unit extends the duration of the judgment result and outputs an over-frequency signal.

[0012] The conduction state of the suppression circuit gating switch is controlled according to the level of the overfrequency signal. When the overfrequency signal is high, the first gating switch is closed, so that the input signal is processed by the high-frequency disturbance suppression unit and then output. When the overfrequency signal is low, the second gating switch is closed, so that the input signal is directly output.

[0013] In one possible implementation, the rising edge extraction unit comprises a first inverter, a first delay capacitor, and a first AND gate; the input signal is connected to the input terminal of the first inverter and the first input terminal of the first AND gate, and the output of the first inverter is connected to the second input terminal of the first AND gate through the first delay capacitor.

[0014] In one possible implementation, the first modulation unit is a monostable multivibrator used to convert each rising edge into a pulse with a first fixed pulse width, which is controlled by a capacitor in the first modulation unit.

[0015] In one possible implementation, the filtering unit is a resistor-capacitor filter circuit.

[0016] In one possible implementation, the over-frequency judgment unit is a hysteresis comparator; the comparison of the voltage signal with a fixed level by the over-frequency judgment unit and the output of the judgment result includes: when the voltage signal is greater than the uplink judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a high level; when the voltage signal is less than the downlink judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a low level; the uplink judgment threshold of the hysteresis comparator is the sum of the fixed level and half of the hysteresis threshold; the downlink judgment threshold of the hysteresis comparator is the difference between the fixed level and half of the hysteresis threshold.

[0017] In one possible implementation, the second modulation unit is configured to: when the output of the over-frequency judgment unit flips from low level to high level, make the high level of the over-frequency signal last for at least a second fixed time, the second fixed time being controlled by a capacitor in the second modulation unit.

[0018] In one possible implementation, the high-frequency disturbance suppression unit includes a second inverter, a second AND gate, and a second delay capacitor; after the input signal passes through the second inverter, a delay time is generated by the second delay capacitor, and when the pulse width of the input signal is less than the delay time, the output of the high-frequency disturbance suppression unit remains at a low level.

[0019] In one possible implementation, during system initialization, the suppression circuit gating switch is in the on state, allowing the input signal to be directly output to the target output terminal.

[0020] In one possible implementation, the high-frequency disturbance suppression unit directly transmits the turn-off edge of the input signal to the target output terminal.

[0021] Secondly, embodiments of this application provide a high-frequency pulse interference suppression device for integrated circuits, comprising: a high-frequency pulse interference detection and suppression circuit, the high-frequency pulse interference detection and suppression circuit including a high-frequency interference detection unit and a high-frequency interference suppression unit; the high-frequency interference detection unit including a rising edge extraction unit, a first modulation unit, a filtering unit, an over-frequency judgment unit, and a second modulation unit connected in sequence; the high-frequency interference suppression unit including a suppression circuit selection switch and a high-frequency disturbance suppression unit, wherein the suppression circuit selection switch includes a first selection switch and a second selection switch;

[0022] The rising edge extraction unit is used to extract the rising edge of the input signal;

[0023] The first modulation unit is used to modulate each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude;

[0024] The filtering unit is used to filter the pulse wave and convert the frequency information of the input signal into a voltage signal;

[0025] The over-frequency judgment unit is used to compare the voltage signal with a fixed level and output the judgment result; the over-frequency judgment unit has hysteresis characteristics.

[0026] The second modulation unit is used to extend the duration of the judgment result and output an over-frequency signal;

[0027] The suppression circuit selector switch is used to control its own conduction state according to the level of the overfrequency signal. When the overfrequency signal is high, the first selector switch is closed, so that the input signal is processed by the high-frequency disturbance suppression unit and then output. When the overfrequency signal is low, the second selector switch is closed, so that the input signal is directly output.

[0028] Thirdly, embodiments of this application provide a computing device, including:

[0029] Memory and processor;

[0030] The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the steps of the above-described high-frequency pulse interference detection and suppression method.

[0031] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the above-described high-frequency pulse interference detection and suppression method.

[0032] Fifthly, embodiments of this application provide a computer program, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described high-frequency pulse interference detection and suppression method.

[0033] The technical solution provided in this application embodiment captures the transition moments of the input signal through the rising edge extraction unit in the high-frequency interference detection unit, and the first modulation unit converts each transition into a pulse wave with a fixed pulse width and amplitude; the pulse wave is processed by the filtering unit and converted into a voltage signal characterizing the frequency of the input signal; this voltage signal is compared with a fixed level in the over-frequency judgment unit with hysteresis characteristics, and the judgment result is then processed by the second modulation unit to extend the duration, finally generating an over-frequency signal; the high-frequency interference suppression unit automatically switches its working state according to the level of this over-frequency signal, that is, when the level is high, the suppression function is activated so that the signal is processed and output, and when the level is low, the input and output are directly connected. Based on this scheme, firstly, by converting the frequency information of the input signal into a voltage signal and comparing it with a fixed level, the manufacturing precision and consistency problems caused by the need for extremely small currents and capacitors in traditional schemes are avoided, thus achieving accurate detection of high-frequency interference at the MHz level. Secondly, by adaptively controlling the start and stop of the suppression circuit based on the over-frequency signal level, the traditional mode of continuous operation of the suppression circuit and the unnecessary increase in delay are completely changed. This allows the circuit to intervene in suppression only when the high-frequency interference is confirmed to be persistent, thereby eliminating interference while ensuring extremely fast signal transmission when there is no interference, successfully achieving a balance between high reliability and low latency. Attached Figure Description

[0034] Figure 1 A schematic diagram of the connection structure of a high-frequency pulse interference detection and suppression circuit provided in one embodiment of this application;

[0035] Figure 2 A flowchart illustrating a high-frequency pulse interference detection and suppression method provided in one embodiment of this application;

[0036] Figure 3 A schematic diagram of the specific structure of a high-frequency pulse interference detection and suppression circuit is provided for one embodiment of this application;

[0037] Figure 4 This is a performance simulation diagram of a high-frequency pulse interference detection and suppression circuit provided in one embodiment of this application;

[0038] Figure 5 A performance simulation diagram of a high-frequency pulse interference detection and suppression circuit provided in another embodiment of this application. Detailed Implementation

[0039] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0040] The terminology used in one or more embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of one or more embodiments of this application. The singular forms “a” and “the” as used in one or more embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0041] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this application, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0042] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0043] 1. High-frequency pulse interference: refers to sudden noise signals with extremely high frequency (such as megahertz) and short duration, which can seriously affect the signal integrity of integrated circuits.

[0044] 2. Rising edge: refers to the instantaneous process of a digital signal transitioning from a low level to a high level.

[0045] 3. Hysteresis characteristic: This refers to the comparator having two different trigger thresholds, which can prevent the output from frequently flipping near the critical point due to small fluctuations in the input signal.

[0046] 4. Over-frequency signal: This circuit has a custom flag signal. Its high level indicates that the input signal frequency has been continuously detected to exceed the preset value.

[0047] This application provides a method for detecting and suppressing high-frequency pulse interference. This application also relates to a high-frequency pulse interference suppression device for integrated circuits, a computing device, and a computer-readable storage medium, which will be described in detail in the following embodiments.

[0048] The high-frequency pulse interference detection and suppression method provided in this application involves a high-frequency interference detection unit that extracts the rising edge of the input signal and modulates each rising edge into a pulse wave with a fixed pulse width. This pulse wave is then filtered and converted into a DC voltage signal proportional to the input signal frequency. This voltage signal is compared with a preset threshold in a comparator with hysteresis characteristics. If the threshold is continuously exceeded, an over-frequency signal is generated through a pulse broadening circuit. Finally, the high-frequency interference suppression unit automatically switches its operating state based on this over-frequency signal. When the signal frequency is normal, it outputs directly to ensure low delay. When the frequency continuously exceeds the limit, it activates the suppression function to filter high-frequency interference before outputting.

[0049] In some embodiments, the high-frequency pulse interference detection and suppression method is applied to a high-frequency pulse interference detection and suppression circuit. To implement the above-mentioned high-frequency pulse interference detection and suppression method, this application embodiment also provides a high-frequency pulse interference detection and suppression circuit.

[0050] Figure 1 This is a schematic diagram of the connection structure of a high-frequency pulse interference detection and suppression circuit provided in one embodiment of this application.

[0051] In some embodiments, the high-frequency pulse interference detection and suppression circuit is a high-frequency pulse interference detection and suppression circuit.

[0052] Reference Figure 1 As shown, the high-frequency pulse interference detection and suppression circuit may include a high-frequency interference detection unit 10 and a high-frequency interference suppression unit 20.

[0053] The high-frequency interference detection unit 10 includes a rising edge extraction unit 101, a first modulation unit 102, a filtering unit 103, an over-frequency judgment unit 104, and a second modulation unit 105 connected in sequence; the high-frequency interference suppression unit 20 includes a suppression circuit selection switch 201 and a high-frequency disturbance suppression unit 202.

[0054] In one implementation,

[0055] Figure 2 This is a flowchart illustrating a high-frequency pulse interference detection and suppression method provided in one embodiment of this application.

[0056] Reference Figure 2 As shown, the method may include the following steps:

[0057] Step 201: Extract the rising edge of the input signal using the rising edge extraction unit;

[0058] Step 202: Modulate each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude using the first modulation unit;

[0059] Step 203: Filter the pulse wave using a filtering unit to convert the frequency information of the input signal into a voltage signal;

[0060] Step 204: The voltage signal is compared with a fixed level by the over-frequency judgment unit, and the judgment result is output; the over-frequency judgment unit has hysteresis characteristics;

[0061] Step 205: The judgment result is extended in duration by the second modulation unit, and an over-frequency signal is output;

[0062] Step 206: Control the conduction state of the suppression circuit gating switch according to the level of the overfrequency signal. When the overfrequency signal is high, the gating switch is closed, so that the input signal is processed by the high-frequency disturbance suppression unit and then output. When the overfrequency signal is low, the gating switch is opened, so that the input signal is directly output.

[0063] Combination Figure 1 and Figure 2 As shown, in some embodiments, the input signal enters the rising edge extraction unit 201, which extracts the rising edge from low to high level of the input signal. By specifically extracting the rising edge of the signal, the complex frequency detection problem is simplified to counting and filtering a fixed pulse width sequence, thereby bypassing the high-precision current and capacitance required for direct detection of high-frequency signals in traditional solutions, and fundamentally solving the problem that manufacturing processes cannot accurately detect megahertz-level frequencies.

[0064] In some embodiments, the first modulation unit 102 modulates each rising edge in the rising edge extraction unit 202 into a pulse wave with a fixed amplitude and fixed pulse width. The filtering unit filters the modulated pulse wave into Vx. Discrete time-domain events (rising edges) are converted into stable analog voltage signals, thereby achieving accurate measurement of signal frequency. The first modulation unit converts each rising edge into a standard pulse with a fixed amplitude and pulse width, ensuring that the pulse energy reference generated at different frequencies is consistent; subsequently, the filtering unit performs integral averaging on these standard pulses, outputting a DC voltage Vx that is proportional to the number of pulses per unit time (i.e., signal frequency). By configuring a "frequency-voltage" conversion mechanism, not only is the dependence on small components for direct detection of high-frequency signals avoided, but the accuracy and consistency problems of traditional schemes in megahertz-level frequency detection are also solved.

[0065] In some embodiments, the filtering unit filters the pulse wave and converts the frequency information of the input signal into a voltage signal. That is, the frequency information of the input signal is converted into the voltage signal Vx through the rising edge extraction unit 101, the first modulation unit 102 and the filtering unit 103. The filtering unit receives the pulse wave from the previous stage with a fixed area (amplitude × pulse width) and smooths these pulses through its integration effect. When the frequency of the input signal increases, the number of pulses input per unit time increases, and the average voltage (Vx) output by the filtering unit increases accordingly, and vice versa. Based on the above "frequency-voltage" conversion mechanism, the high-frequency time information that is difficult to directly measure is converted into a stable analog voltage that is easy to process, which not only overcomes the manufacturing accuracy problem caused by the traditional solution's dependence on tiny current and capacitance, but also provides a stable and reliable judgment basis for the subsequent circuit, thus achieving the precise detection of high-frequency interference.

[0066] In some embodiments, the input signal of the over-frequency judgment unit 104 is compared between Vx and a fixed level V1, and V1 is a fixed level obtained through reasonable design. When Vx ≥ V1, it is considered that the frequency of the input signal is higher than the set value; when Vx < V1, it is considered that the frequency of the input signal is lower than the set value. The over-frequency judgment unit 104 needs to have a certain hysteresis to prevent the output of the over-frequency judgment from frequently flipping between high and low levels. Through the over-frequency judgment unit with hysteresis characteristics, the voltage signal representing the frequency is compared with the preset fixed level threshold: when the voltage signal exceeds the upper threshold, it is determined that the frequency exceeds the standard and a high level is output; when the voltage signal is lower than the lower threshold, it is determined that the frequency is normal and a low level is output. This dual-threshold judgment mechanism effectively prevents the frequent output jumps caused by the small fluctuations of the signal at the critical frequency point, solves the reliability problem of the traditional detection circuit being prone to malfunction in a noisy environment, and provides a stable and definite trigger signal for the subsequent protection circuit.

[0067] If the over-frequency judgment unit 104 outputs a high level, the second modulation unit 105 extends the high-level time of the over-frequency judgment unit 104, ultimately outputting an over-frequency signal. If the second modulation unit 105 outputs a high level, it is considered that the frequency of the input signal exceeds the preset value; if the second modulation unit 105 outputs a low level, it is considered that the frequency of the input signal does not exceed the preset value. If the over-frequency signal is high, the suppression circuit selector switch 201 closes, and the high-frequency disturbance suppression unit 202 starts working, suppressing high-frequency interference higher than the set frequency and transmitting it to the output signal, which is the final output of the chip; if the over-frequency signal is low, the suppression circuit selector switch 201 opens, and the high-frequency suppression circuit stops working. By performing pulse broadening processing on the frequency judgment result through the second modulation unit 105, it is ensured that the output over-frequency signal can be sustained for a fixed time, thereby effectively preventing false triggering caused by instantaneous fluctuations in the input signal. The system intelligently switches its operating state based on the frequency signal level: when the level is high, the suppression circuit selector switch 201 is closed, allowing the input signal to be output after being filtered by the high-frequency disturbance suppression unit; when the level is low, the suppression circuit selector switch 201 is opened, maintaining direct signal transmission. This design ensures that high-frequency interference can be effectively filtered out when it occurs continuously, while also ensuring zero signal transmission delay under normal operating conditions, thus resolving the technical contradiction between suppressing interference and maintaining transmission efficiency that is difficult to achieve simultaneously in traditional solutions.

[0068] Figure 3 A schematic diagram of the specific structure of a high-frequency pulse interference detection and suppression circuit is provided for one embodiment of this application.

[0069] Reference Figure 3 As shown, in some embodiments, the rising edge extraction unit 101 consists of an inverter U1 (first inverter), a delay capacitor C1 (first delay capacitor), and an AND gate U2 (first logic AND gate); the input signal is connected to the input terminal of the inverter U1 and the first input terminal of the AND gate U2, and the output of the inverter U1 is connected to the second input terminal of the AND gate U2 through the delay capacitor C1.

[0070] Reference Figure 3 As shown, in some embodiments, PWM is a logic input signal in a high-frequency pulse interference detection and suppression circuit. When the driving input signal enters the inverter U1 and AND gate U2, the rising edge of each driving signal is extracted by the rising edge extraction circuit composed of inverter U1, delay capacitor C1 and AND gate U2. The extracted rising edge enters the first modulation unit 102.

[0071] Reference Figure 3As shown, in some embodiments, the first modulation unit 102 consists of inverters U3, U4, U5, NOR gate U6, and capacitor C2, used to convert each rising edge into a pulse with a first fixed pulse width, which is controlled by capacitor C2 in the first modulation unit. By converting frequency information into pulse area information, a reference is laid for the subsequent filtering circuit to linearly convert the frequency into voltage; secondly, the design of controlling the pulse width with a single capacitor avoids the technological difficulties of simultaneously controlling a very small current and a capacitor in traditional schemes, significantly improving the manufacturability and parameter consistency of the circuit; furthermore, the fixed pulse width characteristic can effectively filter out narrow pulse interference in the input signal, fundamentally enhancing the anti-interference capability and reliability of the entire detection system.

[0072] Reference Figure 3 As shown, in some embodiments, the modulated pulse wave enters the filter unit 103, which includes a resistor R1 and a capacitor C3. That is, the filter unit 103 is a resistor-capacitor filter circuit. The parameter design of the filter unit 103 needs to take into account the desired frequency determination point and the desired response time, and finally convert the frequency information of the output PWM into voltage information Vx. The desired frequency determination point determines the specific voltage threshold that the standard pulse sequence should reach after filtering at the target frequency; while the desired response time requires the circuit to ensure that the filtered output voltage can be established to the determination threshold in time within the set interference duration period. Through this targeted parameter design, the system successfully linearly converts the dynamic frequency information of the PWM signal into a stable DC voltage Vx, thereby providing an accurate and timely quantitative basis for the subsequent over-frequency determination unit.

[0073] Reference Figure 3As shown, in some embodiments, the over-frequency judgment unit 104 consists of a hysteresis comparator U7. The fixed level V1 is a set level. In one implementation, the over-frequency judgment unit 104 is a hysteresis comparator; when the voltage signal is greater than the upward judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a high level; when the voltage signal is less than the downward judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a low level; the upward judgment threshold of the hysteresis comparator is the sum of the fixed level and half of the hysteresis threshold; the downward judgment threshold of the hysteresis comparator is the difference between the fixed level and half of the hysteresis threshold, where the hysteresis threshold VTH is a design value. In other words, when Vx is rising, when Vx > V1 + VTH / 2, the comparator U7 outputs a high level; when Vx is falling, when Vx < V1 - VTH / 2, the comparator U7 outputs a low level. When the voltage signal Vx rises above the upper threshold (V1 + VTH / 2), a high-level output is triggered, and when Vx falls, it needs to be lower than the lower threshold (V1 - VTH / 2) to resume the low-level output. This dual-threshold mechanism effectively eliminates the problem of frequent flipping of the comparator output caused by fluctuations in the input signal frequency near the critical value or superposition of noise, greatly improving the anti-interference ability, ensuring that subsequent protection actions are only triggered under continuous and definite over-frequency conditions, thus eliminating false protection while ensuring the stability and reliability of the system operation.

[0074] Referring to Figure 3 As shown, in some embodiments, the high level or low level output by U7 enters the second modulation unit 105 composed of U8 - U14, C4, and C5. The second modulation unit 105 is configured to make the high level of the over-frequency signal last at least a second fixed time when the output of the over-frequency judgment unit 104 flips from low level to high level, and the second fixed time is controlled by the capacitor in the second modulation unit. When the output of the over-frequency judgment unit triggers a high level, through the monostable working mechanism controlled by the internal capacitor of this circuit, the high level of the output over-frequency signal is forced to maintain a fixed shortest duration precisely controlled by the capacitance value. This duration extension mechanism ensures that all high-frequency interference can be suppressed within the second fixed time; it avoids the problem of frequent flipping of the over-frequency signal in a short time due to the uncertainty of high-frequency pulse interference after triggering the over-frequency protection.

[0075] In some embodiments, the second modulation unit 105 outputs the final result of the frequency detection, OVER_FMAX. When OVER_FMAX is high, it indicates that the frequency of the input signal PWM is continuously greater than the set frequency for a certain period of time; when OVER_FMAX is low, it indicates that the frequency of the input signal PWM does not exceed the set frequency or the duration does not meet the detection requirements. By requiring the input signal frequency to not only exceed the set threshold but also continuously meet the minimum time threshold, the true continuous high-frequency interference and instantaneous pulse noise are effectively identified. This fundamentally eliminates the malfunction of the protection circuit caused by signal jitter or instantaneous glitches, thereby significantly improving the overall system's operational stability and anti-interference reliability while ensuring that the suppression circuit only responds to effective interference.

[0076] Reference Figure 3 As shown, in some embodiments, the suppression circuit gating switch 201 includes a first switch S1 and a second switch S2. During system initialization, the suppression circuit gating switch 201 is in the ON state, allowing the input signal to be directly output to the target output terminal. This setting allows for the immediate establishment of a delay-free signal path during system power-on or reset, ensuring instantaneous response to control commands and completely eliminating the control lag problem caused by the inherent delay introduced by traditional suppression circuits during initialization. Furthermore, by delaying the activation of the high-frequency suppression function, it effectively avoids false protection actions that may be caused by power fluctuations or signal transients during system startup, significantly improving the stability and reliability of the system in its initial stage.

[0077] When the overfrequency signal OVER_FMAX is high, the first switch S1 is closed and the second switch S2 is open; when the overfrequency signal OVER_FMAX is low, the first switch S1 is open and the second switch S2 is closed. Specifically, when OVER_FMAX is high, S1 is closed and S2 is open, and the input signal PWM is transmitted to the high-frequency disturbance suppression unit via S1; when OVER_FMAX is low, the output signal is directly transmitted to the chip's output PWM_LOGIC (i.e., the target output terminal). The switching control mechanism of the above-mentioned suppression circuit selector switch 201 precisely switches between two independent signal paths by the high and low levels of the overfrequency signal, achieving an intelligent balance between suppression function and transmission efficiency. Specifically, when continuous high-frequency interference is detected, S1 is closed and S2 is open, forcing the signal to be filtered by the high-frequency disturbance suppression unit, completely eliminating the interference's impact on subsequent circuits; under normal operating conditions, S1 is open and S2 is closed, constructing a direct path from input to output, achieving delay-free signal transmission. This adaptive path switching based on frequency detection results fundamentally solves the inherent contradiction that traditional circuits must compromise between "interference resistance" and "low latency," ensuring both the reliability of the system in complex electromagnetic environments and the high-speed response characteristics during normal operation.

[0078] In some embodiments, during system initialization, S1 is open and S2 is closed, allowing the input signal to be output directly without delay, ensuring the shortest possible latency. After the chip starts working, the output of comparator U3 is continuously monitored. When the PWM input signal exceeds a certain frequency, the filter output rises. When the flip of comparator U3 is detected, it means that the high-frequency PWM pulse has lasted for a period of time, triggering the OVER_FMAX protection. To avoid the OVER_FMAX duration being too short, the OVER_FMAX high-level output lasts for at least 1ms after comparator U3 goes high. During the duration of the high level of OVER_FMAX, S1 is closed and S2 is open, allowing the input signal to be transmitted to the output after a 200ns delay.

[0079] Reference Figure 3 As shown, in some embodiments, inverter U16 (second inverter), AND gate U17 (second AND gate), and capacitor C6 (second delay capacitor) constitute the high-frequency disturbance suppression unit 202. After the input signal passes through inverter U16, a delay time is generated by delay capacitor C6, and then the signal is output through AND gate U17. When the pulse width of the input signal is less than the delay time, the output of the high-frequency disturbance suppression unit 202 remains low, and high-frequency interference from the PWM input signal will not be transmitted to the secondary side. The high-frequency disturbance suppression unit 202 achieves precise control of the input signal pulse width through the synergistic effect of the inverter, AND gate, and delay capacitor, indirectly achieving precise frequency filtering of the input signal. Specifically, when a normal pulse width signal passes through, its high-level duration is sufficient to overcome the delay introduced by capacitor C6, allowing the output to completely reproduce the input waveform. However, when high-frequency narrow pulse interference occurs, its pulse width is less than the delay introduced by capacitor C6, and the signal is forcibly truncated by AND gate U17 before reaching the logic threshold, resulting in a stable low-level output. This pulse width recognition-based filtering mechanism can completely block the propagation path of high-frequency interference while preserving the integrity of normal control signals, thereby solving the signal integrity problem at its root and ensuring that the power circuit switching transistors will not malfunction due to high-frequency interference, thus preventing system reliability risks.

[0080] In some embodiments, the high-frequency disturbance suppression unit 202 directly transmits the turn-off edge of the input signal to the target output terminal. The high-frequency disturbance suppression unit 202 achieves direct transmission of the turn-off edge through its unique structural design: when the input signal experiences a turn-off edge (a high-level transition to a low-level), the AND gate U17 quickly detects the change in the input signal, causing its output terminal to respond to a low level with almost no delay. This mechanism allows the turn-off command to bypass the conventional RC delay stage, achieving instantaneous transmission of the turn-off edge. Its key technical effect is to ensure that the power switching device can be turned off quickly, effectively avoiding the risk of common conduction caused by turn-off delay, and significantly improving the system's safety and reliability while maintaining high-frequency interference suppression functionality.

[0081] In some embodiments, the filter and comparator threshold parameter design process is as follows: It is assumed that the effective frequency of the input signal to be detectable is 1MHz, with a maximum of 2MHz; input frequencies above 5MHz are defined as high-frequency interference signals, and the higher the frequency of the input signal, the faster the high-frequency suppression circuit is expected to take effect; therefore, it is defined that if the frequency of the input signal is 10MHz, the over-frequency protection is triggered after 10 cycles; the pulse width of ONE SHOT1 is 50ns, the amplitude is 2.5V, and the RC time constant is set to 1.6us;

[0082] At this point, the ripple is calculated as follows: Vripple = 2.5V * 50ns / 0.8us = 75mV;

[0083] After 1µs, the RC response increases to: 1 - e^(-1 / 0.8) = 46.47%;

[0084] If the input frequency is a stable 10MHz, the stable threshold after filtering should be: VDD*ONE_SHOT*10MHz=1.25V;

[0085] After 1µs, the voltage response after RC filtering rises to 1.25V * 46.47% = 0.58V. Therefore, the uplink judgment threshold of the comparator is designed to be 0.6V. Considering the ripple of 75mV, a hysteresis of 0.2V is left, and the downlink judgment threshold is designed to be 0.4V.

[0086] Figure 4 This is a performance simulation diagram of a high-frequency pulse interference detection and suppression circuit provided in one embodiment of this application.

[0087] Reference Figure 4As shown in the simulation built in Simplis simulation software, the horizontal axis represents time. The purple line represents the curve of the input PWM signal, the green line represents the curve of the PWM_LOGIC signal output by the high-frequency pulse suppression circuit, and the red line represents the curve of the OVER_FMAX signal output by the over-frequency detection circuit. The input PWM signal is a 1MHz pulse, which abruptly changes to 10MHz at time t2. After a very short time (approximately 1µs) following the abrupt change, the OVER_FMAX protection is triggered at time t3, the 10MHz frequency is blocked, and the output signal PWM_LOGIC remains at a low level. This invention continuously monitors the frequency of the input PWM signal. Only when the PWM signal frequency continuously exceeds the set frequency will the over-frequency judgment signal OVER_FMAX become high. This continuous detection circuit prevents false triggering of the over-frequency judgment signal.

[0088] Figure 5 This is a performance simulation diagram of a high-frequency pulse interference detection and suppression circuit provided in another embodiment of this application.

[0089] Reference Figure 5 As shown, the horizontal axis represents time; purple represents the curve of the input PWM signal; green represents the curve of the PWM_LOGIC signal output by the high-frequency pulse suppression circuit; and red represents the curve of the OVER_FMAX signal output by the over-frequency detection circuit. When the OVER_FMAX over-frequency signal is triggered, the high-frequency interference suppression unit starts working. When the input signal PWM flips to a high level, the output signal PWM_LOGIC responds to the input signal PWM after 200ns and flips to a high level. When OVER_FMAX is low, the high-frequency suppression circuit stops working, and the output signal PWM_LOGIC can respond to the input signal PWM immediately without delay, ensuring that the input signal PWM controls the output signal PWM_LOGIC quickly.

[0090] The high-frequency pulse interference detection and suppression method provided in this application accurately extracts the rising edge of the input signal and then converts each rising edge into a standard pulse with a fixed pulse width through a first modulation unit. These pulses are then integrated and averaged by a filtering unit to generate a DC voltage proportional to the signal frequency. This voltage is compared with a preset threshold in an over-frequency judgment unit with hysteresis characteristics. If the threshold is continuously exceeded, a second modulation unit is triggered to perform pulse broadening on the judgment result, outputting an over-frequency signal with a minimum duration. Finally, the system automatically controls the state of the selection switch based on this signal level. When there is no interference, the signal is passed through to ensure transmission speed; when interference is confirmed, the system switches to a high-frequency disturbance suppression unit to delay and filter the signal before outputting it. Through the synergistic mechanism of "frequency-voltage conversion" and "hysteresis judgment-pulse broadening," accurate detection and reliable judgment of MHz-level high-frequency interference are achieved. Furthermore, by using adaptive path switching technology, the core contradiction between "interference suppression" and "maintaining transmission efficiency" in traditional circuits is completely resolved, ultimately achieving high reliability anti-interference capability and extremely low signal transmission delay simultaneously on a single chip. This solution effectively detects and suppresses extremely high frequency signals (>10MHz), with a simple circuit design and controllable accuracy. The high-frequency interference suppression unit only activates protection after a sustained high-frequency signal, and the higher the frequency, the faster the protection is triggered, aligning with current application scenarios. When the input is low-frequency, the high-frequency suppression circuit remains inactive, ensuring extremely short transmission delays and avoiding trade-offs between transmission speed and bandwidth during chip design. During the high-frequency suppression circuit's operation, only the input signal's on / off state is delayed by 200ns, while the off state is directly transmitted to the output, allowing the driver chip to quickly shut down, meeting current application requirements.

[0091] Corresponding to the above method embodiments, this application also provides an embodiment of a high-frequency pulse interference suppression device for integrated circuits. The device includes a high-frequency pulse interference detection and suppression circuit, including a high-frequency interference detection unit and a high-frequency interference suppression unit. The high-frequency interference detection unit includes a rising edge extraction unit, a first modulation unit, a filtering unit, an over-frequency judgment unit, and a second modulation unit connected in sequence. The high-frequency interference suppression unit includes a suppression circuit selection switch and a high-frequency disturbance suppression unit.

[0092] Rising edge extraction unit, used to extract the rising edge of the input signal;

[0093] The first modulation unit is used to modulate each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude.

[0094] The filtering unit is used to filter pulse waves and convert the frequency information of the input signal into a voltage signal;

[0095] The over-frequency judgment unit is used to compare the voltage signal with a fixed level and output the judgment result; the over-frequency judgment unit has hysteresis characteristics.

[0096] The second modulation unit is used to extend the duration of the judgment result and output an over-frequency signal;

[0097] The suppression circuit selector switch is used to control its own conduction state according to the level of the overfrequency signal. When the overfrequency signal is high, the selector switch is closed, so that the input signal is processed by the high-frequency disturbance suppression unit and then output. When the overfrequency signal is low, the selector switch is opened, so that the input signal is directly output to the target output terminal.

[0098] In one possible implementation, the rising edge extraction unit comprises a first inverter, a first delay capacitor, and a first AND gate; the input signal is connected to the input terminal of the first inverter and the first input terminal of the first AND gate, and the output of the first inverter is connected to the second input terminal of the first AND gate through the first delay capacitor.

[0099] In one possible implementation, the first modulation unit is a monostable multivibrator used to convert each rising edge into a pulse with a first fixed pulse width, which is controlled by a capacitor in the first modulation unit.

[0100] In one possible implementation, the filtering unit is a resistor-capacitor filter circuit.

[0101] In one possible implementation, the over-frequency judgment unit is a hysteresis comparator. The over-frequency judgment unit compares the voltage signal with a fixed level and outputs a judgment result including: when the voltage signal is greater than the uplink judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a high level; when the voltage signal is less than the downlink judgment threshold of the hysteresis comparator, the hysteresis comparator outputs a low level; the uplink judgment threshold of the hysteresis comparator is the sum of the fixed level and half of the hysteresis threshold; the downlink judgment threshold of the hysteresis comparator is the difference between the fixed level and half of the hysteresis threshold.

[0102] In one possible implementation, the second modulation unit is configured to: when the output of the over-frequency judgment unit flips from low level to high level, make the high level of the over-frequency signal last for at least a second fixed time, the second fixed time being controlled by a capacitor in the second modulation unit.

[0103] In one possible implementation, the high-frequency disturbance suppression unit includes a second inverter, a second AND gate, and a second delay capacitor; after the input signal passes through the second inverter, a delay time is generated by the second delay capacitor, and when the pulse width of the input signal is less than the delay time, the output of the high-frequency disturbance suppression unit remains at a low level.

[0104] In one possible implementation, the suppression circuit gating switch includes a first switch and a second switch; when the overfrequency signal is high, the first switch is closed and the second switch is open; when the overfrequency signal is low, the first switch is open and the second switch is closed.

[0105] In one possible implementation, during system initialization, the suppression circuit gating switch is in the on state, allowing the input signal to be directly output to the target output terminal.

[0106] In one possible implementation, the high-frequency disturbance suppression unit directly transmits the turn-off edge of the input signal to the target output terminal.

[0107] The above is a schematic scheme of a high-frequency pulse interference suppression device for integrated circuits according to this embodiment. It should be noted that the technical solution of this high-frequency pulse interference suppression device for integrated circuits belongs to the same concept as the technical solution of the high-frequency pulse interference detection and suppression method described above. Details not described in detail in the technical solution of the high-frequency pulse interference suppression device for integrated circuits can be found in the description of the technical solution of the high-frequency pulse interference detection and suppression method described above.

[0108] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this application.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] The preferred embodiments disclosed above are merely illustrative of this application. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments of this application. These embodiments are selected and specifically described in this application to better explain the principles and practical applications of the embodiments of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method of high frequency impulse interference detection and suppression, the method comprising: The method is applied to a high-frequency pulse interference suppression circuit, the high-frequency pulse interference suppression circuit comprising a high-frequency interference detection unit and a high-frequency interference suppression unit; the high-frequency interference detection unit comprising a rising edge extraction unit, a first modulation unit, a filter unit, an over-frequency judgment unit and a second modulation unit connected in sequence; the high-frequency interference suppression unit comprising a suppression circuit gating switch and a high-frequency disturbance suppression unit, wherein the suppression circuit gating switch comprises a first gating switch and a second gating switch; The method comprises: extracting rising edges of an input signal through the rising edge extraction unit; modulating each extracted rising edge into a pulse wave with a fixed pulse width and a fixed amplitude through the first modulation unit; filtering the pulse wave to convert frequency information of the input signal into a voltage signal through the filter unit; comparing the voltage signal with a fixed level through the over-frequency judgment unit and outputting a judgment result; wherein the over-frequency judgment unit has a hysteresis characteristic; performing duration extension processing on the judgment result through the second modulation unit and outputting an over-frequency signal; controlling the conduction state of the suppression circuit gating switch according to the level of the over-frequency signal, wherein when the over-frequency signal is at a high level, the first gating switch is closed to make the input signal output after being processed by the high-frequency disturbance suppression unit, and when the over-frequency signal is at a low level, the second gating switch is closed to make the input signal directly output.

2. The method of claim 1, wherein, The rising edge extraction unit is composed of a first inverter, a first delay capacitor and a first logic AND gate; the input signal is connected to the input end of the first inverter and the first input end of the first logic AND gate, and the output of the first inverter is connected to the second input end of the first logic AND gate through the first delay capacitor.

3. The method of claim 1, wherein, The first modulation unit is used to convert each rising edge into a pulse with a first fixed pulse width, and the first fixed pulse width is controlled by a capacitor in the first modulation unit.

4. The method of claim 1, wherein, The filter unit is a resistance-capacitance filter circuit.

5. The method of claim 1, wherein, The over-frequency judgment unit is a hysteresis comparator; The comparison of the voltage signal with a fixed level through the over-frequency judgment unit and the output of a judgment result comprises: when the voltage signal is greater than the up-judgment threshold value of the hysteresis comparator, the hysteresis comparator outputs a high level; when the voltage signal is less than the down-judgment threshold value of the hysteresis comparator, the hysteresis comparator outputs a low level; the up-judgment threshold value of the hysteresis comparator is the sum of the fixed level and one-half of the hysteresis threshold value; and the down-judgment threshold value of the hysteresis comparator is the difference between the fixed level and one-half of the hysteresis threshold value.

6. The method according to claim 1 or 5, characterized in that, The second modulation unit is configured to make the high level of the over-frequency signal last for at least a second fixed time when the output of the over-frequency judgment unit is flipped from a low level to a high level, and the second fixed time is controlled by a capacitor in the second modulation unit.

7. The method of claim 1, wherein, The high-frequency disturbance suppression unit comprises a second inverter, a second logical AND gate and a second delay capacitor; after the input signal passes through the second inverter, a delay time is generated through the second delay capacitor; when the pulse width of the input signal is less than the delay time, the output of the high-frequency disturbance suppression unit maintains a low level.

8. The method of claim 1, wherein, In the system initialization state, the suppression circuit gating switch is in the on state, so that the input signal is directly output to the target output end.

9. The method of claim 7, wherein, The high-frequency disturbance suppression unit directly transmits the off edge of the input signal to the target output end.

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