A method, device, equipment and medium for generating a test file of a memory
By automatically parsing memory operation sequence files and matching them with register access and timing parameter sequences in the database, memory test files are generated, solving the problem of low efficiency in existing technologies and achieving automation of the verification process and reducing configuration errors.
CN121862180BActive Publication Date: 2026-06-16合肥康芯威存储技术有限公司
Patent Information
- Application Number
- CN202610321693.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-17
- Publication Date
- 2026-06-16
- Estimated Expiration
- 2046-03-17
AI Technical Summary
Technical Problem
Existing memory verification methods are inefficient, cumbersome, and error-prone, requiring verification engineers to manually translate NAND flash memory operation instructions into the controller's internal register configuration sequence.
Method used
By parsing the memory operation sequence file, the system automatically matches the register access sequence and timing parameter sequence in the preset database to generate a test file for the memory.
Benefits of technology
It achieves a high degree of automation in the verification process, reduces configuration errors caused by human mistakes, and improves the reusability and maintainability of the verification platform.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN121862180B_ABST
Abstract
The application provides a memory test file generation method, device, equipment and medium. The memory test file generation method comprises the following steps: obtaining and analyzing an operation sequence file of a memory to obtain a device model of the memory and at least one functional test operation; determining, according to the device model and each functional test operation, a corresponding register access sequence and a timing parameter sequence of each functional test operation in a preset database; and configuring the timing parameter sequence into the corresponding register access sequence to generate a test file of the memory. The memory test file generation method, device, equipment and medium provided by the application can solve the technical problem of low efficiency of the existing verification method.
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Citation Information
Patent Citations
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