Manufacturing method of semiconductor structure and semiconductor structure

By forming a gate stack structure on a high dielectric constant dielectric layer and using it as a mask to etch sigma trenches, the problem of pseudo-gate damage in the PMOS device region was solved, improving device yield and reliability while reducing process complexity and cost.

CN121968691AActive Publication Date: 2026-05-01NEXCHIP SEMICON CO LTD
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Patent Information

Application Number
CN202610380978.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-26
Publication Date
2026-05-01
Estimated Expiration
2046-03-26

AI Technical Summary

Technical Problem

In the process of forming sigma trenches, the pseudo-gate structure of the PMOS device region is damaged by the etching process, resulting in a difference in pseudo-gate height between the PMOS device region and the NMOS device region. This affects the uniformity of subsequent processes and device yield, and increases process complexity and cost.

Method used

After forming a gate stack structure on a high dielectric constant layer, a patterned high dielectric constant layer is used as a mask to form sigma trenches in the PMOS device region using an etching process. By selectively retaining the high dielectric constant layer in the NMOS device region as an etching barrier layer, additional photomask processes are avoided, thus achieving region-selective control.

Benefits of technology

It eliminates the height difference between the dummy gates in PMOS and NMOS device regions, improves device yield and reliability, simplifies the process flow, reduces cost and complexity, and ensures etching uniformity.

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Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.
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