Semiconductor layout processing method and related product
By employing an algorithm-driven interruption strategy in semiconductor layout processing, combined with secondary interruption and correction based on process-limited lengths, the problem of reliance on experience and low efficiency in existing OPC optimization processes is solved. This achieves fast and accurate optical proximity effect correction, meeting production timeliness requirements.
Patent Information
- Application Number
- CN202610437152.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-02
- Publication Date
- 2026-05-12
AI Technical Summary
The existing OPC optimization process is highly unpredictable, difficult to systematically cover all potential scenarios, has low solution adaptation coverage, slow execution efficiency, cannot meet production timeliness requirements, and has a long solution implementation cycle.
The semiconductor layout processing method first breaks the line segment by a small preset length, then performs an optical proximity correction to obtain the target line segment. The breaking position is determined by combining the length limit of the process, and a second breaking and correction is performed. The algorithm drives the breaking strategy to avoid reliance on human experience.
It significantly improves the systematicness and efficiency of OPC correction, shortens the optimization cycle from one to two weeks to within one week to meet the timeliness requirements of the production site, ensures the accuracy of edge placement error, and improves the solution adaptation coverage and execution efficiency.
Smart Images
Figure CN122018252A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor layout processing technology, and in particular to a semiconductor layout processing method and related products. Background Technology
[0002] In the semiconductor manufacturing field, starting with the 180nm technology node, the minimum linewidth on semiconductor devices begins to be smaller than the exposure wavelength, making optical proximity correction (OPC) essential. The pattern on the photomask is projected onto the photoresist through an exposure system. Due to imperfections in the optical system and diffraction effects, the pattern on the photoresist and the pattern on the photomask are not perfectly identical. Optical proximity correction uses computational methods to correct the pattern on the photomask, ensuring that the pattern projected onto the photoresist conforms as closely as possible to the design requirements.
[0003] The goal of OPC correction is to ensure consistency between the exposed graphic and the design graphic, specifically that the edge placement error (EPE) is within an acceptable range. OPC correction requires mask rule checking (MRC) to determine whether relevant manufacturing rules are met, such as minimum line width, line spacing, and spacing between graphic corners.
[0004] In OPC correction, long lines are typically broken into relatively short lines to obtain more variables for optimization, leading to better results. Different breaking methods result in different correction outcomes. The process involves initial breaking of the input layout; after OPC optimization, a Lithography Rule Check (LRC) is performed to identify bad pixels; break variables near the bad pixels are adjusted; OPC optimization is then performed again, followed by an LRC check; if adjusting break variables near the bad pixels fails to resolve the issue, the variables are adjusted again until the bad pixels are resolved. However, current OPC optimization processes have several drawbacks: they are highly dependent on experience, lack sufficient solution coverage, and rely heavily on the experience and judgment of OPC engineers. Because the possible combinations of break variables are almost infinite, the optimization process is highly unpredictable, making it difficult to systematically cover all potential scenarios and resulting in low solution compatibility. Furthermore, execution efficiency is slow, failing to meet production timeliness requirements, and the solution implementation cycle is long; typically, it takes 1 to 2 weeks to output relatively ideal optimization results for typical defect problems. However, production sites have strict requirements for the timeliness of anomaly response, generally requiring a closed loop within one week. Existing OPC optimization processes have significant problems in terms of time adaptability. Summary of the Invention
[0005] In view of the above problems, the present invention is proposed to provide a semiconductor layout processing method and related products that overcome or at least partially solve the above problems, so as to solve the problems of large randomness in the existing optimization process, difficulty in systematically covering all potential scenarios resulting in low solution adaptation coverage, and the problems of lagging execution efficiency, inability to meet production timeliness requirements, and long solution implementation cycle.
[0006] According to one aspect of the present invention, a semiconductor layout processing method is provided, comprising: Obtain the target edge for correction on the semiconductor layout; The target edge to be corrected is interrupted once according to a preset length, and the target edge to be corrected for optical proximity effect once, so as to obtain the preliminary optimized edge corresponding to the target edge to be corrected. The target line segment is obtained from the preliminary optimized edge based on the distance between the preliminary optimized edge and the corrected target edge; The break position on the target edge to be corrected is determined based on the target line segment and the process-defined length; the process-defined length is greater than the preset length. The target edge to be corrected is interrupted a second time according to the interruption position, and the target edge to be corrected is then subjected to a second optical proximity effect correction.
[0007] Optionally, obtaining the target line segment from the preliminary optimized edge based on the distance between the preliminary optimized edge and the corrected target edge includes: The initial optimized edge is divided based on the intersection points of the initial optimized edge and the target edge of the correction, to obtain an initial segment; Within each line segment of the initial segmentation, a line segment parallel to the corresponding line segment of the target edge is determined to obtain a parallel line segment; Obtain the distance between each of the parallel line segments and the corresponding position on the correction target edge; The parallel line segment corresponding to the maximum distance is taken as the target line segment.
[0008] Optionally, determining the break position on the target edge based on the target line segment and the process-defined length includes: On the target edge of the correction, determine the mapping line segment corresponding to the target line segment, and the connecting line segment connected to the mapping line segment; Compare the length of the mapped line segment with the process-defined length, and extend or eliminate the mapped line segment whose length is less than the process-defined length. Compare the length of the connecting line segment with the process-defined length, and eliminate connecting line segments whose length is less than the process-defined length; The endpoints of the processed mapped line segments and the endpoints of the processed connecting line segments are used as the first set of break positions. A second set of break positions is determined on each processed mapped line segment according to the process-defined length. A third set of break positions is determined on each processed connecting line segment according to the process-defined length. The break positions include the first set of break positions, the second set of break positions, and the third set of break positions.
[0009] Optionally, the process of extending or eliminating mapped line segments whose length is less than the process-defined length includes: Obtain the total length of the mapped line segment whose length is less than the process-defined length and the connecting line segments connected to it; When the total length is greater than or equal to the process-defined length, the endpoints of the mapping segment are determined on at least one connecting segment connected to the mapping segment, such that the length of the mapping segment is equal to the process-defined length. When the total length is less than the process-defined length, the midpoint of the mapped line segment is used as the endpoint of the connecting line segment connected to the mapped line segment, thereby eliminating the mapped line segment.
[0010] Optionally, determining the endpoints of the mapping line segment on at least one connecting line segment connected to the mapping line segment includes: When the sum of the lengths of the mapped line segment and each of the connecting line segments connected to it is less than or equal to the process-defined length, the endpoint of the shorter connecting line segment that is furthest from the mapped line segment is taken as the endpoint of the mapped line segment to eliminate the connecting line segment. When the sum of the lengths of the mapped line segment and a connecting line segment connected to it is less than or equal to the process-defined length, the endpoint of the connecting line segment furthest from the mapped line segment is taken as the endpoint of the mapped line segment to eliminate the connecting line segment. When the sum of the lengths of the mapped segment and each of the connecting segments connected to it is greater than the process-defined length, the endpoint of the mapped segment is determined only on the longer connecting segment, or the endpoint of the mapped segment is determined on both connecting segments, and the ratio between the eliminated portion lengths of the two connecting segments is equal to the ratio between the lengths of the two connecting segments.
[0011] Optionally, the process of eliminating connecting line segments with a length less than the process-defined length includes: Identify whether the initially optimized edge intersects with a connecting line segment whose length is less than the process-defined length; When there is an intersection between the preliminary optimized edge and the connecting line segment, the intersection is used as the endpoint of the mapping line segment or connecting line segment connected to the connecting line segment, so as to eliminate the connecting line segment; When there is no intersection between the preliminary optimized edge and the connecting line segment, the midpoint of the connecting line segment is used as the endpoint of the mapping line segment or connecting line segment connected to the connecting line segment, so as to eliminate the connecting line segment.
[0012] Optionally, determining the second set of break positions on each processed mapped line segment according to the process-defined length includes: When the length of the mapped line segment is greater than or equal to twice the process-defined length, the mapped line segment is divided equally, and the length of each segment after equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length. The evenly divided positions on the mapped line segment are taken as the second set of interruption positions; The step of determining the third set of break positions on each processed connecting segment according to the process-defined length includes: When the length of the connecting line segment is greater than or equal to twice the process-defined length, the connecting line segment is divided equally, and the length of each segment after equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length. The evenly divided positions on the connecting line segment are taken as the third set of interruption positions.
[0013] Optionally, obtaining the target edge for correction on the semiconductor layout includes: The semiconductor layout is corrected for optical proximity effect to obtain a corrected pattern; Weakness or bad spot patterns are obtained from the corrected pattern; The target edge for correction is determined based on the weakness graph or the bad point graph.
[0014] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of any of the above-described semiconductor layout processing methods.
[0015] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of any of the above-described semiconductor layout processing methods.
[0016] According to another aspect of the present invention, a computer device is also provided, which includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any semiconductor layout processing method.
[0017] The semiconductor layout processing method of this invention first breaks the pattern according to a small preset length, then performs a correction. Based on the correction result, the key line segments are identified, and the required break position is determined in conjunction with the process-limited length to obtain an excellent corrected pattern. This system systematically solves the core pain points of traditional OPC correction, such as high dependence on engineer experience, insufficient solution coverage, and long optimization cycle. Specifically, this setting realizes that the break strategy is driven by an algorithm rather than human experience, thereby eliminating the difference in results caused by different engineers' operations; at the same time, since the break position matches the correction amount changes of each region of the pattern, it can adaptively cover any pattern scenario such as corners, ends, and straight lines, avoiding the coverage blind spots caused by traditional exhaustive attempts; more importantly, this process determines the optimal break position, eliminating the need for many rounds of "adjustment-correction-verification" iterations after discovering bad pixels, shortening the original manual optimization cycle of one to two weeks to meet the timeliness requirement of closed-loop within one week in the production field, and finally outputting the optimized result that meets the mask rule check while ensuring the accuracy of edge placement error. To address the problems of existing processes being heavily reliant on experience, inefficient, and even failing to achieve ideal results, this invention proposes a stable and efficient solution that can significantly improve the efficiency of solving the above problems, shortening the time to less than one day, and achieving ideal results.
[0018] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description
[0019] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic flowchart of a semiconductor layout processing method according to an embodiment of the present invention; Figure 2 This is a partial schematic flowchart of a semiconductor layout processing method according to an embodiment of the present invention; Figure 3 This is a partial schematic flowchart of a semiconductor layout processing method according to an embodiment of the present invention; Figure 4This is a schematic diagram of the modified target edge, the preliminary optimized edge, the target line segment, the mapped line segment, and the connecting line segment in a semiconductor layout processing method according to an embodiment of the present invention; Figure 5 This is a schematic flowchart of a semiconductor layout processing method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a computer program product according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and Figure 8 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation
[0020] This embodiment provides a semiconductor layout processing method. Figure 1 This is a schematic flowchart of a semiconductor layout processing method according to an embodiment of the present invention. The method generally includes: Step S100: Obtain the correction target edge 11 on the semiconductor layout. The semiconductor layout can be the design layout. Obtaining the correction target edge 11 first aims to ensure that the correction target edge 11, after being corrected by OPC, meets the requirements of the photolithography process, thereby making the pattern corresponding to the correction target edge 11 projected onto the photoresist as close as possible to the design requirements.
[0021] In step S200, the target edge 11 is broken once according to a preset length, and optical proximity effect correction is performed on the target edge 11 to obtain the preliminary optimized edge 12 corresponding to the target edge 11. The target edge 11 is divided into several small segments according to a preset length, which can be a small fixed length. Through fine segmentation, a high-precision preliminary correction shape, i.e., the preliminary optimized edge 12, is obtained.
[0022] Step S300: Obtain the target line segment 13 from the preliminary optimized edge 12 based on the distance between the preliminary optimized edge 12 and the corrected target edge 11. Obtaining the target line segment 13 based on the distance allows for the identification of key segments that require special attention.
[0023] Step S400: Determine the break position on the target edge 11 based on the target line segment 13 and the process-defined length. The process-defined length is greater than the preset length and has a large value, representing the minimum segment length allowed by the manufacturing process. When writing the mask pattern, the electron beam lithography machine cannot accurately form line segments that are too short. The process-defined length ensures that the final corrected pattern meets the mask manufacturing constraints. The break position on the target edge 11 determined based on the target line segment 13 and the process-defined length serves as the reference for determining the secondary break. This not only meets the process requirements but also minimizes the risk of bad pixels during optical proximity correction.
[0024] In step S500, the target edge 11 is broken a second time according to the break position, and a second optical proximity effect correction is performed on the target edge 11. The original target edge 11 is re-segmented according to the newly determined break position. The segment length is no longer a small and uniform preset length, but a longer segment with a length variation matching the correction amount distribution. Then, based on the new segmentation, OPC correction is performed again.
[0025] The semiconductor layout processing method of this invention first breaks the pattern by a small preset length, then performs a correction. Based on the correction result, the key line segments are identified, and the required break position is determined by combining the process-limited length to obtain an excellent corrected pattern. This system systematically solves the core pain points of traditional OPC correction, such as high dependence on engineer experience, insufficient solution coverage, and long optimization cycle. Specifically, this setting enables the break strategy to be driven by an algorithm rather than human experience, thereby eliminating the difference in results caused by different engineers' operations. At the same time, since the break position matches the correction amount changes of each region of the pattern, it can adaptively cover any pattern scenario such as corners, ends, and straight lines, avoiding the coverage blind spots caused by traditional exhaustive attempts. More importantly, this process determines the optimal break position, eliminating the need for many rounds of "adjustment-correction-verification" iterations after discovering bad pixels. It shortens the original manual optimization cycle of one to two weeks to meet the timeliness requirement of a closed loop within one week in the production field. Finally, while ensuring the accuracy of edge placement error, it quickly outputs the optimized result that also meets the mask rule check.
[0026] In some embodiments of the present invention, such as Figure 2 As shown, the target line segment 13 is obtained from the preliminary optimized edge 12 based on the distance between the preliminary optimized edge 12 and the corrected target edge 11, including: Step S310: Based on the intersection of the preliminary optimized edge 12 and the corrected target edge 11, the preliminary optimized edge 12 is divided to obtain the initial segment.
[0027] Step S320: In each segment of the initial dividing segment, determine the line segment that is parallel to the corresponding line segment of the target edge 11, and obtain the parallel line segment.
[0028] Step S330: Obtain the distance between each parallel line segment and the corresponding position on the target edge 11.
[0029] Step S340: Take the parallel line segment corresponding to the maximum distance as the target line segment 13.
[0030] The semiconductor layout processing method of this invention achieves accurate quantitative identification of the key segment, i.e., the target line segment 13, eliminating reliance on engineers' experience-based judgment; and provides a deterministic basis for the break position, i.e., the output "target line segment 13" is directly input into step S400 to determine the break position in conjunction with the process-defined length. Since the target line segment 13 corresponds to the area with the largest correction amount, the optimal break position can be determined based on the target line segment 13, thereby achieving the best correction effect.
[0031] In some embodiments of the present invention, such as Figure 3 As shown, the break position on the target edge 11 is determined based on the target line segment 13 and the process-limited length, including: Step S410: On the target edge 11, determine the mapping line segment 14 corresponding to the target line segment 13, and the connecting line segment 15 connected to the mapping line segment 14.
[0032] Step S420: Compare the length of the mapped line segment 14 with the process-defined length, and extend or eliminate the mapped line segment 14 whose length is less than the process-defined length. It should be noted that after the mapped line segment 14 is extended or eliminated, the connecting line segment 15 connected to it will be adaptively changed, such as becoming shorter, eliminated, or extended.
[0033] Step S430: Compare the length of connecting line segment 15 with the process-defined length, and eliminate connecting line segments 15 whose length is less than the process-defined length. It should be noted that after the connecting line segment 15 is eliminated, the connecting line segments 15 or mapped line segments 14 connected to it will be adaptively changed, for example, extended.
[0034] Step S440: The endpoints of the processed mapped line segment 14 and the endpoints of the processed connecting line segment 15 are used as the first set of break positions. The second set of break positions is determined on each processed mapped line segment 14 according to the process-defined length. The third set of break positions is determined on each processed connecting line segment 15 according to the process-defined length. The break positions include the first set of break positions, the second set of break positions and the third set of break positions.
[0035] The semiconductor layout processing method of this embodiment of the invention employs an "extending rather than simple elimination" processing method for the mapped line segment 14 in S420, prioritizing the correction effect of critical areas. In S430, it employs an "elimination of excessively short segments" processing method for the connecting line segment 15, prioritizing mask optimization efficiency. This differentiated processing of the two types of areas avoids the loss of accuracy in critical areas or excessive subdivision of the connecting line segment 15 caused by a "one-size-fits-all" approach, minimizing the number of breakpoints. In S440, breakpoints are inserted within each line segment according to process-defined lengths, ensuring that even the longest line segment is divided into sub-segments conforming to mask manufacturing rules. This allows the secondary OPC to start from an initial state that satisfies constraints and has a well-optimized structure, improving the correction convergence speed and final accuracy.
[0036] In some embodiments of the present invention, the mapping line segment 14 with a length less than the process-defined length is extended or eliminated, including: Obtain the total length of the mapped line segment 14 whose length is less than the process-defined length and the connecting line segment 15 connected to it.
[0037] When the total length is greater than or equal to the process-defined length, the endpoints of the mapping segment 14 are determined on at least one connecting segment 15 connected to the mapping segment 14, such that the length of the mapping segment 14 is equal to the process-defined length.
[0038] When the total length is less than the process-defined length, the midpoint of the mapped line segment 14 is used as the endpoint of the connecting line segment 15 connected to the mapped line segment 14, so as to eliminate the mapped line segment 14.
[0039] The semiconductor layout processing method of this invention transforms the decision between the total length and the process-defined length into explicit mathematical conditions, thereby automating the decision-making process for extension and elimination. Specifically, if there is sufficient space, the line segment is extended to retain it; if space is insufficient, forcibly retaining it would violate masking rules, thus eliminating the line segment 14 to ensure that masking rules are met. This solution, through extension processing, prioritizes retaining these critical regions as independent segments within the allowable total length, ensuring that these hotspots have independent optimization variables during secondary OPC, thereby guaranteeing correction accuracy. Whether extending or eliminating, the final result ensures that the length of the line segment 14 is no less than the process-defined length; after extension, it equals the process-defined length; after elimination, the line segment no longer exists, ensuring that all line segments 14 meet the minimum length requirements of the masking rules, avoiding mask manufacturing failures caused by excessively short segments.
[0040] During the elimination process, the midpoint of the mapped line segment 14 is used as the new endpoint of the connecting line segment 15 to ensure that the endpoint of the connecting line segment 15 after elimination is located at the geometric center of the original mapped line segment 14, so that the shape transition is as smooth as possible, which is beneficial to the stability of subsequent OPC correction.
[0041] In some embodiments of the present invention, determining the endpoints of the mapping segment 14 on at least one connecting segment 15 connected to the mapping segment 14 includes: When the sum of the lengths of the mapped line segment 14 and each connecting line segment 15 connected to it is less than or equal to the process-defined length, the endpoint of the shorter connecting line segment 15 that is furthest from the mapped line segment 14 is taken as the endpoint of the mapped line segment 14, so as to eliminate the connecting line segment 15. When the sum of the lengths of the mapped line segment 14 and a connecting line segment 15 connected to it is less than or equal to the process-defined length, the endpoint of the connecting line segment 15 that is furthest from the mapped line segment 14 is taken as the endpoint of the mapped line segment 14, so as to eliminate the connecting line segment 15. When the sum of the lengths of the mapped segment 14 and each connecting segment 15 connected to it is greater than the process-defined length, the endpoint of the mapped segment 14 is determined only on the longer connecting segment 15, or the endpoint of the mapped segment 14 is determined on both connecting segments 15, and the ratio between the lengths of the eliminated portions on the two connecting segments 15 is equal to the ratio between the lengths of the two connecting segments 15.
[0042] The semiconductor layout processing method of this invention decomposes the extension operation into three explicit conditional branches, each corresponding to a different geometric scenario, and provides specific endpoint determination rules. This approach completely replaces the trial-and-error mode of "trying to lengthen it a little" based on intuition in the traditional process. Shorter connection segments 15 are prioritized for elimination, sacrificing the minimum length of the connection segment 15 in exchange for the compliance of the mapped segment 14. The elimination amount is distributed proportionally to avoid excessive erosion of connection segments 15 on one side, maintaining the balance of the geometric layout. After this step, the remaining connection segments 15 (those not completely eliminated) will enter S430 for length compliance checking. This solution implicitly considers the length of the remaining segments when determining the endpoints, creating favorable conditions for subsequent processing.
[0043] In some embodiments of the present invention, the connection segment 15 with a length less than the process-defined length is eliminated, including: Identify whether there is an intersection between the initially optimized edge 12 and the connecting line segment 15 whose length is less than the process limit.
[0044] When there is an intersection between edge 12 and the connecting line segment 15 in the initial optimization, the intersection is used as the endpoint of the mapping line segment 14 or the connecting line segment 15 connected to the connecting line segment 15, so as to eliminate the connecting line segment 15.
[0045] When there is no intersection between edge 12 and the connecting line segment 15 in the initial optimization, the midpoint of the connecting line segment 15 is used as the endpoint of the mapping line segment 14 or the connecting line segment 15 connected to the connecting line segment 15, so as to eliminate the connecting line segment 15.
[0046] The semiconductor layout processing method of this invention enables refined decision-making for the elimination of connecting line segments 15. When the initially optimized edge 12 intersects with the excessively short connecting line segment 15, this intersection reflects the actual edge position after one OPC correction. Using this intersection as the endpoint after elimination ensures that the elimination operation does not change the corrected key contour features. Subsequent secondary OPCs can start optimization from the same state as the first correction, avoiding discontinuities in correction caused by manual adjustment of the endpoint position. When there is no intersection, the midpoint is selected as the new endpoint. The midpoint is the most natural and balanced merging position, avoiding abrupt changes in the length of adjacent line segments due to bias to one side, which is beneficial to the stability of photolithography imaging. After this elimination step, all connecting line segments 15 with lengths less than the process-defined length have been merged into adjacent mapped line segments 14 or other connecting line segments 15. When entering S440 for final break position determination, the lengths of all remaining line segments meet the minimum requirements of the process-defined length, ensuring that the final mask pattern can pass MRC.
[0047] In some embodiments of the present invention, determining a second set of break positions on each processed mapped line segment 14 according to a process-defined length includes: When the length of the mapped line segment 14 is greater than or equal to twice the process-defined length, the mapped line segment 14 is divided into equal parts, and the length of each segment after the equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length.
[0048] The evenly divided positions on the mapped line segment 14 are used as the second set of break positions.
[0049] The semiconductor layout processing method of this invention maximizes the degree of freedom of optimization while satisfying MRC constraints, ensuring that all sub-segments of the mapping line segment 14 meet the minimum length requirements for mask manufacturing, thus guaranteeing that the final pattern passes MRC. By requiring that the length of each sub-segment of the mapping line segment 14 be less than 1.5 times the process-defined length, insufficient optimization variables due to excessively long sub-segments are avoided. Shorter sub-segments of the mapping line segment 14 provide more degrees of freedom for OPC adjustment, enabling more precise correction of optical proximity effects.
[0050] In some embodiments of the present invention, determining a third set of break positions on each processed connecting segment 15 according to a process-defined length includes: When the length of connecting segment 15 is greater than or equal to twice the process-defined length, the connecting segment 15 is divided into equal parts, and the length of each segment after the equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length.
[0051] The evenly divided positions on the connecting line segment 15 are taken as the third set of break positions.
[0052] The semiconductor layout processing method of this invention maximizes the degree of freedom of optimization while satisfying MRC constraints, ensuring that all sub-segments of the connecting line segment 15 meet the minimum length requirements for mask manufacturing, thus guaranteeing that the final pattern passes MRC. By requiring that the length of each sub-segment of the connecting line segment 15 be less than 1.5 times the process-defined length, insufficient optimization variables due to excessively long sub-segments are avoided. Shorter sub-segments of the connecting line segment 15 provide more adjustment degrees of freedom for OPC, enabling more precise correction of optical proximity effects.
[0053] In some embodiments of the present invention, obtaining the modified target edge 11 on the semiconductor layout includes: Optical proximity effect correction is applied to the semiconductor layout to obtain the corrected pattern.
[0054] Obtain weak or bad pixel images from the corrected image.
[0055] The target edge 11 for correction is determined based on the weak point graph or bad point graph.
[0056] The semiconductor layout processing method of this invention identifies weak / dead pixels and then performs selective optimization. It only performs refined breakpoint re-determination work in weak / dead pixel regions, while other regions can use conventional OPC strategies or directly apply the initial OPC result. This significantly reduces overall computational complexity, improves optimization efficiency, and ensures that optimization resources are always focused on the locations that truly need improvement, avoiding blind optimization and guaranteeing the targeted and effective nature of the optimization work. Furthermore, by pre-screening weak / dead pixels, refined optimization is limited to local areas, minimizing computational costs while ensuring yield.
[0057] In some embodiments of the present invention, such as Figure 5 As shown, the semiconductor layout processing method includes: Step S610: Initial break of the input layout.
[0058] Step S620: Perform OPC optimization on the processed layout to obtain the initial mask layout, and then perform LRC check to find bad pixels.
[0059] Step S630: Select the edges that need to be specially interrupted based on the bad points, and obtain the correction target edge 11.
[0060] Step S640: Break the target edge 11 into small segments; the length of each segment is generally 3-5 nm.
[0061] Step S650: Perform optical proximity effect correction on the target edge 11.
[0062] Step S660: Based on the optimization results, extract the breakpoints, that is, determine the breakpoints on the target edge 11.
[0063] Step S670: The target edge 11 is interrupted a second time according to the interruption position, and the target edge 11 is corrected for optical proximity effect to obtain the target edge mask pattern.
[0064] Step S680: "Paste" the target edge mask pattern back to the corresponding position of the initial mask pattern.
[0065] Step S690: Perform an LRC check.
[0066] The semiconductor layout processing method of this invention first uses initial LRC verification to accurately locate process defects, focusing fine optimization resources on key areas rather than the entire layout, significantly reducing computational costs. Then, the defective areas are corrected using 3-5nm subdivision segments via OPC to accurately compensate for local optical proximity effects with maximum optimization freedom. Next, key breakpoints are extracted from the optimization results to complete secondary segmentation, ensuring the final mask pattern meets MRC manufacturing rules. Finally, the corrected local pattern is "pasted back" to the initial mask layout and verified through a second LRC closed-loop process. While ensuring mask manufacturability, this method effectively repairs defects that are difficult to resolve in the initial process, significantly improving the overall layout imaging quality and mass production yield, while avoiding the waste of computational resources and extended iteration cycles caused by fine-tuning the entire layout.
[0067] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in every case. Furthermore, the method may include additional operations. Within the scope of the technical concept provided by the method in this embodiment, additional variations can be made to the above method.
[0068] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.
[0069] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 6 This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 7This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 8 This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of the semiconductor layout processing method of any of the above embodiments. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the semiconductor layout processing method of any of the above embodiments. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.
[0070] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer. In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing status information of the computer-readable program instructions.
[0071] For the purposes of this embodiment, computer program product 10 is a related product that includes computer program 11.
[0072] For the purposes of this embodiment, computer-readable storage medium 20 is a tangible device capable of holding and storing a computer program 11. It can be any device capable of containing, storing, communicating, propagating, or transmitting the program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.
[0073] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.
[0074] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.
[0075] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.
[0076] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.
Claims
1. A semiconductor layout processing method, characterized in that, include: Obtain the target edge for correction on the semiconductor layout; The target edge to be corrected is interrupted once according to a preset length, and the target edge to be corrected for optical proximity effect once, so as to obtain the preliminary optimized edge corresponding to the target edge to be corrected. The target line segment is obtained from the preliminary optimized edge based on the distance between the preliminary optimized edge and the corrected target edge; The break position on the target edge to be corrected is determined based on the target line segment and the process-defined length; the process-defined length is greater than the preset length. The target edge to be corrected is interrupted a second time according to the interruption position, and the target edge to be corrected is then subjected to a second optical proximity effect correction.
2. The semiconductor layout processing method according to claim 1, characterized in that, The step of obtaining the target line segment from the preliminary optimized edge based on the distance between the preliminary optimized edge and the corrected target edge includes: The initial optimized edge is divided based on the intersection points of the initial optimized edge and the target edge of the correction, to obtain an initial segment; Within each line segment of the initial segmentation, a line segment parallel to the corresponding line segment of the target edge is determined to obtain a parallel line segment; Obtain the distance between each of the parallel line segments and the corresponding position on the correction target edge; The parallel line segment corresponding to the maximum distance is taken as the target line segment.
3. The semiconductor layout processing method according to claim 1, characterized in that, Determining the break position on the target edge based on the target line segment and the process-defined length includes: On the target edge of the correction, determine the mapping line segment corresponding to the target line segment, and the connecting line segment connected to the mapping line segment; Compare the length of the mapped line segment with the process-defined length, and extend or eliminate the mapped line segment whose length is less than the process-defined length. Compare the length of the connecting line segment with the process-defined length, and eliminate connecting line segments whose length is less than the process-defined length; The endpoints of the processed mapped line segments and the endpoints of the processed connecting line segments are used as the first set of break positions. A second set of break positions is determined on each processed mapped line segment according to the process-defined length. A third set of break positions is determined on each processed connecting line segment according to the process-defined length. The break positions include the first set of break positions, the second set of break positions, and the third set of break positions.
4. The semiconductor layout processing method according to claim 3, characterized in that, The process of extending or eliminating mapped line segments whose length is less than the process-defined length includes: Obtain the total length of the mapped line segment whose length is less than the process-defined length and the connecting line segments connected to it; When the total length is greater than or equal to the process-defined length, the endpoints of the mapping segment are determined on at least one connecting segment connected to the mapping segment, such that the length of the mapping segment is equal to the process-defined length. When the total length is less than the process-defined length, the midpoint of the mapped line segment is used as the endpoint of the connecting line segment connected to the mapped line segment, thereby eliminating the mapped line segment.
5. The semiconductor layout processing method according to claim 4, characterized in that, Determining the endpoints of the mapping line segment on at least one connecting line segment connected to the mapping line segment includes: When the sum of the lengths of the mapped line segment and each of the connecting line segments connected to it is less than or equal to the process-defined length, the endpoint of the shorter connecting line segment that is furthest from the mapped line segment is taken as the endpoint of the mapped line segment to eliminate the connecting line segment. When the sum of the lengths of the mapped line segment and a connecting line segment connected to it is less than or equal to the process-defined length, the endpoint of the connecting line segment furthest from the mapped line segment is taken as the endpoint of the mapped line segment to eliminate the connecting line segment. When the sum of the lengths of the mapped segment and each of the connecting segments connected to it is greater than the process-defined length, the endpoint of the mapped segment is determined only on the longer connecting segment, or the endpoint of the mapped segment is determined on both connecting segments, and the ratio between the eliminated portion lengths of the two connecting segments is equal to the ratio between the lengths of the two connecting segments.
6. The semiconductor layout processing method according to claim 3, characterized in that, The process of eliminating connecting line segments whose length is less than the process-defined length includes: Identify whether the initially optimized edge intersects with a connecting line segment whose length is less than the process-defined length; When there is an intersection between the preliminary optimized edge and the connecting line segment, the intersection is used as the endpoint of the mapping line segment or connecting line segment connected to the connecting line segment, so as to eliminate the connecting line segment; When there is no intersection between the preliminary optimized edge and the connecting line segment, the midpoint of the connecting line segment is used as the endpoint of the mapping line segment or connecting line segment connected to the connecting line segment, so as to eliminate the connecting line segment.
7. The semiconductor layout processing method according to claim 3, characterized in that, Determining the second set of break positions on each processed mapped line segment according to the process-defined length includes: When the length of the mapped line segment is greater than or equal to twice the process-defined length, the mapped line segment is divided equally, and the length of each segment after equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length. The evenly divided positions on the mapped line segment are taken as the second set of interruption positions; The step of determining the third set of break positions on each processed connecting segment according to the process-defined length includes: When the length of the connecting line segment is greater than or equal to twice the process-defined length, the connecting line segment is divided equally, and the length of each segment after equal division is greater than or equal to the process-defined length and less than 1.5 times the process-defined length. The evenly divided positions on the connecting line segment are taken as the third set of interruption positions.
8. The semiconductor layout processing method according to claim 1, characterized in that, The step of obtaining the target edge for correction on the semiconductor layout includes: The semiconductor layout is corrected for optical proximity effect to obtain a corrected pattern; Weakness or bad spot patterns are obtained from the corrected pattern; The target edge for correction is determined based on the weakness graph or the bad point graph.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the semiconductor layout processing method according to any one of claims 1 to 8.
10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the semiconductor layout processing method according to any one of claims 1 to 8.