Test instruction generation method and device, electronic equipment and storage medium
By automating the generation of test instruction sequences and their expected results, the problems of low verification coverage and low efficiency in chip system-level testing are solved, achieving more efficient test coverage and defect detection.
Patent Information
- Application Number
- CN202610163668.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-04
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies have low verification coverage and low efficiency in chip system-level testing, making it difficult to detect and fix design defects in a timely manner after the hardware design is frozen.
By randomly determining the target instruction, resource requirement information is generated and sent to the resource management module. Resource allocation information is received, and a test instruction sequence and its expected results are generated using a preset instruction library, thereby achieving automated generation of test instructions.
It improves the verification coverage and efficiency of chip system-level testing, reduces the need for manually writing test instructions, and enhances the ability to detect design defects.
Smart Images
Figure CN122044976A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design and manufacturing technology, and in particular to a test instruction generation method, apparatus, electronic device and storage medium. Background Technology
[0002] Chip verification is typically divided into different stages, such as unit testing (UT), block-level testing (BT), and system-level testing (ST). Among them, system-level testing aims to simulate the chip's operation in a real working environment. By applying complex stimuli to the entire system or key subsystems, it aims to discover potential design flaws in areas such as inter-module interactions, system performance, and hardware-software coordination.
[0003] During system-level testing, the primary incentive is running a specific computational program (kernel). The computational programs used for system-level testing are typically written by the software team based on the application scenario or manually by verification engineers. The former focuses on typical application scenarios, resulting in a relatively singular scenario that makes it difficult to achieve comprehensive random coverage of all chip functionalities. Furthermore, the delivery time is often late, sometimes even after the hardware design freeze (RTL code freeze), preventing the verification team from identifying and fixing hardware issues in a timely manner. The latter approach is not only cumbersome and inefficient but also highly susceptible to human error.
[0004] Therefore, how to improve verification coverage and efficiency in system-level testing of chips has become a technical problem that the industry urgently needs to solve. Summary of the Invention
[0005] This application provides a test instruction generation method, apparatus, electronic device, and storage medium to solve the technical problem of improving verification coverage and verification efficiency in system-level testing of chips.
[0006] This application provides a method for generating test instructions, including: A target instruction is randomly determined; the resource requirement information of the target instruction satisfies the specified resource information. The resource requirement information of the target instruction is sent to the resource management module, and the resource allocation information generated by the resource management module based on the resource requirement information is received; the resource management module is used to manage the hardware resources in the chip under test. The instruction identifier of the target instruction and the resource allocation information are sent to a preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
[0007] In some embodiments, sending the resource requirement information of the target instruction to the resource management module and receiving resource allocation information generated by the resource management module based on the resource requirement information includes: Based on the target instruction's requested resource object, requested resource attribute, requested resource type, and requested resource quantity, the resource requirement information of the target instruction is determined; The resource requirement information is sent to the resource management module, and the resource allocation information sent by the resource management module is received.
[0008] In some embodiments, the resource management module performs the following steps: When the requested resource attribute is an input resource type, a resource usage operation is performed; the resource usage operation includes finding a first hardware resource that meets the requirements, returning the resource index of the first hardware resource, and removing the resource index of the first hardware resource from the resource pool. If the requested resource attribute is an output resource type, a first resource request operation is performed; the first resource request operation includes finding a second hardware resource that meets the requirements and returning the resource index of the second hardware resource; If the requested resource attribute is a temporary resource type, a second resource request operation is performed; the second resource request operation includes finding a third hardware resource that meets the requirements, returning the resource index of the third hardware resource, and adding the resource index of the third hardware resource to the resource pool.
[0009] In some embodiments, the preset instruction library performs the following steps: Upon receiving at least one attribute setting value of the target instruction, the domain segment configuration information of the target instruction is generated based on the at least one attribute setting value; Alternatively, if at least one attribute setting value of the target instruction is not received, the domain segment configuration information of the target instruction may be randomly generated within the preset value range of each attribute.
[0010] In some embodiments, the preset instruction library performs the following steps: When the test instruction sequence is a computational instruction sequence, the computation is carried out at the thread group level and the thread level to generate the expected execution result.
[0011] In some embodiments, the hardware resources include at least one of thread-local registers, thread-beam scalar registers, and base address registers.
[0012] This application provides a test instruction generation apparatus, comprising: The instruction determination module is used to randomly determine the target instruction; the resource requirement information of the target instruction satisfies the specified resource information. The resource allocation module is used to send the resource requirement information of the target instruction to the resource management module and receive the resource allocation information generated by the resource management module based on the resource requirement information; the resource management module is used to manage the hardware resources in the chip under test. The instruction generation module is used to send the instruction identifier of the target instruction and the resource allocation information to a preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
[0013] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the test instruction generation method described above.
[0014] This application provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the test instruction generation method described above.
[0015] This application provides a computer program product, including a computer program that, when executed by a processor, implements the test instruction generation method.
[0016] The test instruction generation method, apparatus, electronic device, and storage medium provided in this application randomly determine target instructions, send the resource requirement information of the target instructions to a resource management module, and receive resource allocation information generated by the resource management module based on the resource requirement information. The method then sends the instruction identifier and resource allocation information of the target instructions to a preset instruction library, enabling the preset instruction library to generate test instruction sequences including the target instructions and the corresponding expected execution results. This achieves the automated generation of various test instruction sequences and their corresponding expected results, eliminating the need for software teams to provide or manually write test instruction sequences. The random generation method improves the verification coverage in chip system-level testing, while the automated execution method improves the verification efficiency in chip system-level testing. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a flowchart illustrating the test instruction generation method provided in this application.
[0020] Figure 2 This is a flowchart of the resource management module provided in this application.
[0021] Figure 3 This is a schematic diagram of the test instruction generation device provided in this application.
[0022] Figure 4 This is a flowchart of the test instruction generation system provided in this application.
[0023] Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation
[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0025] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps, units, or modules is not necessarily limited to those explicitly listed, but may include other steps, units, or modules not explicitly listed or inherent to such processes, methods, products, or devices.
[0026] In order to address the shortcomings of related technologies, Figure 1 This is a flowchart illustrating the test instruction generation method provided in this application, as shown below. Figure 1As shown, the method includes steps 110, 120 and 130.
[0027] Step 110: Randomly determine the target instruction; the resource requirement information of the target instruction meets the specified resource information.
[0028] Specifically, the execution entity of the test instruction generation method provided in this application embodiment is a test instruction generation device or an instruction library control module. This device can be implemented in software, such as a test instruction generation program; or it can be a device that executes the test instruction generation method, such as a mobile terminal, tablet computer, desktop computer, or server.
[0029] A target instruction refers to the basic functional unit (operator, op) used to construct the final test instruction sequence. A target instruction can be a single-function atomic operation, such as the floating-point multiplication instruction (FMUL) or the integer addition instruction (SADD); or it can be a multi-functional instruction composed of multiple basic instructions to implement a complex function, such as the convolution instruction (CONV) or the matrix multiplication instruction (MMA). A variety of target instructions can be predefined and stored in the default instruction library for random selection.
[0030] The specified resource information can be understood as an initial parameter to initiate the instruction generation process, such as the resource number (src number). This information itself can be an integer, a string, or a more complex data structure. After receiving the specified resource information, the instruction library control module determines a specific target instruction according to preset rules or algorithms. This random determination can be a completely random selection, a pseudo-random selection based on the specified resource information as a seed, or a random selection that follows specific constraints (such as prioritizing target instructions with fewer execution times to improve coverage).
[0031] The resource requirement information of a target instruction refers to the hardware resources consumed or occupied by executing that target instruction. Different target instructions require different types and quantities of resources to execute. This resource requirement information can be used to help determine the target instruction. For example, in a resource-constrained scenario, specific resource information can be set so that the instruction library control module randomly selects target instructions with lower resource requirements only within the available resource range.
[0032] Step 120: Send the resource requirement information of the target instruction to the resource management module, and receive the resource allocation information generated by the resource management module based on the resource requirement information; the resource management module is used to manage the hardware resources in the chip under test.
[0033] Specifically, the resource management module provides unified management (including registration, tracking, and allocation) of hardware resources in the entire chip under test (e.g., a Stream Processing Cluster, SPC) to avoid resource conflicts when generating complex instruction sequences.
[0034] Hardware resources are physical or logical units in the chip under test that can be used by program instructions. In a specific embodiment, these hardware resources may include, but are not limited to: Thread Local Registers (TLRs), Warp Scalar Registers (WSRs), memory resources pointed to by Base Address Registers (BARs), semaphores, etc. The resource management module internally maintains one or more resource pools, recording the current status (e.g., idle, occupied, etc.) of all available hardware resources.
[0035] Resource allocation information refers to the result returned by the resource management module after processing a resource request. In the specific execution flow, the instruction library control module sends the resource requirement information for the determined target instruction to the resource management module. Based on this requirement, the resource management module searches for available hardware resources in its maintained resource pool and allocates them. Upon successful allocation, the allocation result (e.g., the unique identifier of the allocated resource, i.e., the resource index) is returned to the instruction library control module as resource allocation information. If there are insufficient resources in the resource pool to meet the requirement, the resource management module can execute an assertion operation to report an error, wait for resource release, or select other alternative resources.
[0036] Step 130: Send the instruction identifier and resource allocation information of the target instruction to the preset instruction library so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
[0037] Specifically, the default instruction library is a collection containing the specific implementation logic of multiple target instructions. An instruction identifier is a name (op name) or code used to uniquely specify a target instruction. The test instruction sequence is the final generated series of machine instructions executable on the chip under test, which can be referred to as the kernel.
[0038] The test commands include Single and Multi data streams, and applicable types can include Tensor Cores (Tcore), Vector Cores (Vcore), and Specific Architecture Accelerators (LSA).
[0039] The expected execution result refers to the theoretical result that should be obtained when the test instruction sequence is executed correctly under ideal conditions; it can be called the Golden result. This result will be used to compare with the actual operating results of the chip to determine whether the chip function is correct.
[0040] The instruction library control module sends the target instruction's instruction identifier (op name) and resource allocation information to the pre-defined instruction library (op library). The pre-defined instruction library locates the specific implementation logic of the target instruction based on the instruction identifier, and then uses the passed-in resource allocation information (e.g., which register is used as the source operand and which register as the target operand) to fill the instruction template, thereby generating the final test instruction sequence. Simultaneously, the logic within the pre-defined instruction library also calculates the corresponding expected execution result based on the target instruction's operational function and specific configuration, and outputs it as well.
[0041] The test instruction generation method provided in this application randomly determines a target instruction, sends the resource requirement information of the target instruction to a resource management module, and receives resource allocation information generated by the resource management module based on the resource requirement information. It then sends the instruction identifier and resource allocation information of the target instruction to a preset instruction library, enabling the preset instruction library to generate a test instruction sequence including the target instruction and the corresponding expected execution results. This achieves the random generation of various test instruction sequences and their corresponding expected results in an automated manner, eliminating the need for the software team to provide or manually write test instruction sequences. The random generation method improves the verification coverage in chip system-level testing, while the automated execution method improves the verification efficiency in chip system-level testing.
[0042] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.
[0043] In some embodiments, the resource requirement information of the target instruction is sent to the resource management module, and resource allocation information generated by the resource management module based on the resource requirement information is received, including: Based on the target instruction's requested resource object, requested resource attribute, requested resource type, and requested resource quantity, determine the target instruction's resource requirement information; Send resource demand information to the resource management module and receive resource allocation information from the resource management module.
[0044] Specifically, after the target instruction is determined, the instruction library control module parses the instruction and transforms its hardware resource requirements into a set of parameters. These parameters together constitute the resource requirement information of the target instruction. These parameters include the requested resource object, the requested resource attribute, the requested resource type, and the requested resource quantity.
[0045] The resource name is used to identify the initiator of the resource request, i.e., the target instruction currently being processed. In a specific embodiment, this parameter can be a string, such as 'tlr0' or 'wsr1', used for debugging and tracing the source of resource allocation.
[0046] The resource attribute defines how the target instruction will use the requested resource. Attributes can include input resource type, output resource type, and temporary resource type. An input resource type indicates that the resource must already contain data before the instruction is executed, serving as the instruction's input operand. An output resource type indicates that the resource is used to store the instruction's execution result. A temporary resource type indicates that the resource is only used temporarily during instruction execution and can be immediately reclaimed after use. By explicitly distinguishing resource usage attributes, the resource management module can implement more granular management. This parameter is typically passed as a string.
[0047] The resource type indicates the specific category of the required hardware resource. In a specific embodiment, the resource type may include thread-local registers (TLRs), thread bundle scalar registers (WSRs), and other types of resources, such as on-chip or off-chip memory resources managed by base address registers (BARs). This parameter enables the resource management module to search and allocate resources in the correct resource pool. This parameter is typically passed as a string.
[0048] The resource request quantity (Resource cnt) defines the number of hardware resources of a specific type and attribute that need to be requested. For example, a target instruction might require two input registers and one output register. This parameter is typically passed as an integer variable.
[0049] Combining the above four parameters forms a complete and clear target instruction resource requirement information, which can be used as the input interface parameter of the resource management module.
[0050] The instruction library control module sends the aforementioned input interface parameters to the resource management module via a pre-defined interface function call. Upon receiving the request, the resource management module parses the parameters and internally executes the corresponding resource lookup and allocation logic. After allocation, the resource management module returns the allocation result, i.e., the resource allocation information, to the instruction library control module. This resource allocation information can be one or more integers representing the index of the allocated hardware resource, or it can be a more complex data structure containing the allocation status and resource index.
[0051] The test instruction generation method provided in this application structured resource requirement information into parameters including the application object, attributes, type, and quantity, which improved the accuracy of resource allocation and increased the verification coverage in chip system-level testing.
[0052] In some embodiments, the resource management module performs the following steps: When the requested resource attribute is the input resource type, perform a resource usage operation; the resource usage operation includes finding the first hardware resource that meets the requirements, returning the resource index of the first hardware resource, and removing the resource index of the first hardware resource from the resource pool; If the requested resource attribute is an output resource type, perform the first resource request operation; the first resource request operation includes finding the second hardware resource that meets the requirements and returning the resource index of the second hardware resource; If the requested resource is a temporary resource, a second resource request operation is performed. The second resource request operation includes finding a third hardware resource that meets the requirements, returning the resource index of the third hardware resource, and adding the resource index of the third hardware resource to the resource pool.
[0053] Specifically, Figure 2 This is a flowchart of the resource management module provided in this application, such as... Figure 2 As shown, when the resource request information received by the resource management module has the resource type "Input" as the requested resource attribute, it indicates that the target instruction requires an existing resource containing valid data as its operand. In this case, the resource management module performs a resource consumption operation.
[0054] The specific implementation of this operation includes: the resource management module, in its maintained resource pool representing currently allocated resources containing valid data, searches for one or more hardware resources that meet the requested resource type. The first hardware resource refers to the hardware resource found for input. After finding it, the resource management module prepares to return the index of the first hardware resource as part of the resource allocation information to the instruction library control module, and removes the resource index of the first hardware resource from the resource pool.
[0055] Because the validity or status of the input resource type may change after it is used by this instruction, or logically, it may have already been consumed. Therefore, to prevent other subsequent instructions from incorrectly using this potentially outdated or occupied resource, the resource management module removes it from the current resource pool. This ensures the correctness of the data flow and the synchronization of resource states.
[0056] When the requested resource attribute in the resource requirement information is "Output," it indicates that the target instruction needs a resource to store its execution result. In this case, the resource management module executes the first resource request operation (requestresource).
[0057] The specific implementation of this operation includes: the resource management module searching for one or more idle hardware resources in its maintained resource pool, which represents currently available resources, based on the requested resource type and quantity. The second hardware resource refers to the hardware resource found for output.
[0058] Once located, the resource management module directly returns the index of the second hardware resource. Simultaneously, the resource management module updates its internal status, marking the resource as occupied and associating it with the newly generated data.
[0059] When the requested resource attribute in the resource requirement information is a temporary resource (Temp), it indicates that the target instruction requires a resource for internal computation only. This resource becomes invalid after the instruction is executed, and its content is meaningless for subsequent instructions. At this time, the resource management module executes a second resource request operation.
[0060] The specific implementation of this operation includes: similar to the output resource type, the resource management module searches for hardware resources that meet the requirements in its idle resource pool. The third hardware resource refers to the temporary hardware resource found in this instance.
[0061] The index of the found third hardware resource is returned to the control unit, and the resource index of the third hardware resource is added to the resource pool.
[0062] Although the resource is used in the current instruction, the resource management module ensures that its status is immediately reset to idle or at a subsequent checkpoint after use, and it is then added back to the pool of available idle resources. This enables rapid resource turnover and efficient utilization.
[0063] The test instruction generation method provided in this application allows the resource management module to adopt three differentiated management strategies—consumption, allocation, and temporary allocation and recycling—based on the three different attributes of resources: input, output, and temporary. This refined resource lifecycle management not only ensures the correctness of the data flow during the generation of complex instruction sequences and avoids resource conflicts, but also significantly improves the utilization rate of hardware resources through the efficient reuse of temporary resources, enabling the system to generate longer and more complex test sequences.
[0064] In some embodiments, the preset instruction library performs the following steps: Upon receiving at least one attribute setting value for a target instruction, generate the domain segment configuration information for the target instruction based on the at least one attribute setting value; Alternatively, if at least one attribute setting value of the target instruction is not received, the domain segment configuration information of the target instruction can be randomly generated within the preset value range of each attribute.
[0065] Specifically, in one embodiment, upon receiving at least one attribute setting value for a target instruction, domain segment configuration information for the target instruction is generated based on that attribute setting value. This embodiment corresponds to scenarios of directed testing or constrained random testing.
[0066] Attribute settings refer to the parameter values explicitly specified by the instruction library control module for this instruction generation. These attributes may include, but are not limited to: data type, dem size, source register (src register), destination register (dst register), etc. These attributes directly determine the behavior and function of the instruction.
[0067] Segment configuration information refers to the specific values of each binary field that constitutes a complete machine instruction.
[0068] When the default instruction library executes the generation logic of a target instruction, it checks whether the instruction library control module has passed specific settings for these attributes. For example, if the source register is specified as register with index number 5, the source register field in the instruction will be configured as 5. This approach allows verification engineers to create very specific test cases to reproduce known defects or to perform stress tests on a specific feature of the design.
[0069] In another specific embodiment, if at least one attribute setting value of the target instruction is not received, the domain segment configuration information of the target instruction is randomly generated within the preset value range of each attribute. This embodiment corresponds to a random testing scenario.
[0070] When the instruction library control module calls the target instruction, it does not provide the set values for one or all attributes, and the default instruction library will activate its internal randomization logic.
[0071] The preset value range refers to a set of legal and valid values predefined by the instruction library control module for each configurable attribute. For example, for a data type attribute, its preset value range could be the set {FP32, FP16, INT8}. In this case, the preset instruction library will randomly select a value from its corresponding preset value range for each unspecified attribute and use this random value to generate the domain segment configuration information. For example, if no data type is specified, the instruction library control module might randomly select INT8.
[0072] It should be noted that the two embodiments described above can be used in combination. For example, a verification engineer can specify the data type attribute as FP16 (directed) while allowing the register index used by the instruction to be randomly selected within the available range (random), thereby achieving highly flexible constrained random verification.
[0073] The test instruction generation method provided in this application has a preset instruction library with the ability to combine targeted generation and random generation. The targeted generation capability ensures the reproducibility of the test and the accurate verification capability for specific scenarios, while the random generation capability can explore unexpected boundary conditions and state combinations in the design, increasing the probability of discovering unknown defects. The combination of the two improves the verification coverage in chip system-level testing.
[0074] In some embodiments, the preset instruction library performs the following steps: When the test instruction sequence is a computational instruction sequence, the computation is carried out at the thread group level and the thread level to generate the expected execution result.
[0075] Specifically, computational instruction sequences refer to instructions whose main function is to perform arithmetic or logical operations, such as integer addition (SADD), floating-point addition (FADD), floating-point multiplication (FMUL), matrix multiplication (MMA), and convolution (CONV).
[0076] Chips used to run artificial intelligence models typically employ massively parallel computing architectures. Computational tasks are distributed to a large number of execution units, which are usually organized into multiple levels. These levels include at least the thread group level and the thread level. Thread group (tg) level: A thread group contains multiple warps or threads that typically collaborate to complete a larger-granularity computational task. Thread level: A thread is the smallest unit of computation.
[0077] The hardware implementation of a chip determines at what level instructions are executed and how data is distributed and accessed between these levels. In order to generate an expected execution result that is completely consistent with the hardware behavior, the software model must accurately simulate this multi-level parallel computing pattern.
[0078] Therefore, when the default instruction library needs to generate the expected result for a computational instruction, it performs the following operation: Step 1: Obtain computation dimension and hierarchy information: Obtain the configuration information of the current instruction, including the dimension and data type of the operands (input / output data), as well as the number of thread groups to which the computation task is assigned and the number of threads in each thread group.
[0079] Step 2: Perform calculations at the thread group level and thread level: Simulate the behavior of each thread one by one using nested loops. The outer loop iterates through all relevant thread groups. The inner loop iterates through all threads within the specified thread group.
[0080] The test instruction generation method provided in this application has a preset instruction library that can generate high-precision expected results for complex parallel computing instructions; by strictly following the hardware thread groups and thread levels to carry out the calculation, the depth and reliability of the verification are improved.
[0081] The apparatus provided in the embodiments of this application is described below. The apparatus described below can be referred to in correspondence with the method described above.
[0082] Figure 3 This is a schematic diagram of the test instruction generation device provided in this application, as shown below. Figure 3 As shown, the device includes: The instruction determination module 310 is used to randomly determine the target instruction; the resource requirement information of the target instruction meets the specified resource information. The resource allocation module 320 is used to send the resource requirement information of the target instruction to the resource management module and receive the resource allocation information generated by the resource management module based on the resource requirement information; the resource management module is used to manage the hardware resources in the chip under test. The instruction generation module 330 is used to send the instruction identifier and resource allocation information of the target instruction to a preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
[0083] The test instruction generation device provided in this application randomly determines a target instruction, sends the resource requirement information of the target instruction to a resource management module, and receives resource allocation information generated by the resource management module based on the resource requirement information. It then sends the instruction identifier and resource allocation information of the target instruction to a preset instruction library, enabling the preset instruction library to generate a test instruction sequence including the target instruction and the corresponding expected execution result. This achieves the random generation of various test instruction sequences and their corresponding expected results in an automated manner, eliminating the need for software teams to provide or manually write test instruction sequences. The random generation method improves the verification coverage in chip system-level testing, while the automated execution method improves the verification efficiency in chip system-level testing.
[0084] Figure 4 This is a flowchart of the test instruction generation system provided in this application, such as... Figure 4As shown, the test instruction generation device (op lib ctrl), the resource management module (resource manager), and the preset instruction library (op library) together constitute the test instruction generation system.
[0085] The test instruction generation device is the overall control unit. It randomly generates a target instruction that meets the resource quantity requirements based on the input resource quantity and sends the instruction identifier of the target instruction to a preset instruction library. Then, it sends the resource requirement information required by the instruction to the resource management module.
[0086] The resource management module is responsible for managing the register resources of the entire chip and, based on the resource requirement information, returns the corresponding resource allocation information to the test instruction generation device.
[0087] The test instruction generation device sends resource allocation information to a preset instruction library. The preset instruction library manages all instructions; once the resources required for an instruction are allocated, it generates an instruction sequence (kernel) and returns it to the test instruction generation device. This instruction sequence can also be called an operator. Finally, each operator needs to return the corresponding expected execution result for comparison and reference.
[0088] The test instruction generation system provided in this application embodiment realizes the random generation of various test instruction sequences and their corresponding expected results in an automated manner, without the need for the software team to provide or manually write test instruction sequences. The random generation method improves the verification coverage in chip system-level testing, and the automated execution method improves the verification efficiency in chip system-level testing.
[0089] Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor, communications interface, and memory communicate with each other via the communications bus. The processor can invoke logical commands stored in the memory to execute the methods described in the above embodiments, for example: The target instruction is randomly determined; the resource requirement information of the target instruction meets the specified resource information; the resource requirement information of the target instruction is sent to the resource management module, and the resource allocation information generated by the resource management module based on the resource requirement information is received; the resource management module is used to manage the hardware resources in the chip under test; the instruction identifier and resource allocation information of the target instruction are sent to the preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
[0090] Furthermore, the logical commands in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0091] The processor in the electronic device provided in this application embodiment can call logical instructions in the memory to implement the above method. Its specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effect, which will not be repeated here.
[0092] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the methods provided in the above embodiments.
[0093] The specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effects, so it will not be repeated here.
[0094] This application provides a computer program product, including a computer program that, when executed by a processor, implements the method described above.
[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A method for generating test instructions, characterized in that, include: A target instruction is randomly determined; the resource requirement information of the target instruction satisfies the specified resource information. The resource requirement information of the target instruction is sent to the resource management module, and the resource allocation information generated by the resource management module based on the resource requirement information is received. The resource management module is used to manage the hardware resources in the chip under test. The instruction identifier of the target instruction and the resource allocation information are sent to a preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
2. The test instruction generation method according to claim 1, characterized in that, The step of sending the resource requirement information of the target instruction to the resource management module and receiving the resource allocation information generated by the resource management module based on the resource requirement information includes: Based on the target instruction's requested resource object, requested resource attribute, requested resource type, and requested resource quantity, the resource requirement information of the target instruction is determined; The resource requirement information is sent to the resource management module, and the resource allocation information sent by the resource management module is received.
3. The test instruction generation method according to claim 2, characterized in that, The resource management module performs the following steps: When the requested resource attribute is an input resource type, a resource usage operation is performed; the resource usage operation includes finding a first hardware resource that meets the requirements, returning the resource index of the first hardware resource, and removing the resource index of the first hardware resource from the resource pool. If the requested resource attribute is an output resource type, a first resource request operation is performed; the first resource request operation includes finding a second hardware resource that meets the requirements and returning the resource index of the second hardware resource; If the requested resource attribute is a temporary resource type, a second resource request operation is performed; the second resource request operation includes finding a third hardware resource that meets the requirements, returning the resource index of the third hardware resource, and adding the resource index of the third hardware resource to the resource pool.
4. The test instruction generation method according to any one of claims 1 to 3, characterized in that, The preset instruction library performs the following steps: Upon receiving at least one attribute setting value of the target instruction, the domain segment configuration information of the target instruction is generated based on the at least one attribute setting value; Alternatively, if at least one attribute setting value of the target instruction is not received, the domain segment configuration information of the target instruction may be randomly generated within the preset value range of each attribute.
5. The test instruction generation method according to any one of claims 1 to 3, characterized in that, The preset instruction library performs the following steps: When the test instruction sequence is a computational instruction sequence, the computation is carried out at the thread group level and the thread level to generate the expected execution result.
6. The test instruction generation method according to any one of claims 1 to 3, characterized in that, Hardware resources include at least one of thread-local registers, thread-beam scalar registers, and base address registers.
7. A test instruction generation device, characterized in that, include: The instruction determination module is used to randomly determine the target instruction; the resource requirement information of the target instruction satisfies the specified resource information. The resource allocation module is used to send the resource requirement information of the target instruction to the resource management module and receive the resource allocation information generated by the resource management module based on the resource requirement information. The resource management module is used to manage the hardware resources in the chip under test. The instruction generation module is used to send the instruction identifier of the target instruction and the resource allocation information to a preset instruction library, so that the preset instruction library generates a test instruction sequence including the target instruction and the expected execution result corresponding to the test instruction sequence.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the test instruction generation method according to any one of claims 1 to 6.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the test instruction generation method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the test instruction generation method according to any one of claims 1 to 6.