Data unvarnished transmission method and system based on clock tracking

Abstract

The invention discloses a data unvarnished transmission method and system based on clock tracking. The data unvarnished transmission method comprises the following steps: matching a clock tracking mode of an asynchronous cache circuit according to the linear rate of received serial data; the clock recovery circuit is controlled to analyze the serial data to obtain write-in data and a write-in clock; performing jump edge detection on the serial data to perform data recovery on the serial data to obtain a recovery data sequence and obtain a data rate of the recovery data sequence; writing the write-in data or the recovery data sequence according to the clock tracking mode, the write-in clock, the data rate and the local clock of the deserializer to obtain cache data; obtaining a frequency difference between the target tracking clock and a local clock according to the clock tracking mode, the write-in clock and the data rate, and adjusting the local clock to obtain a read clock; and obtaining read data according to the read clock so as to send the read data to a data receiving end, thereby reducing logic resources occupied in a data unvarnished transmission process.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and specifically to a data pass-through method and system based on clock tracking. Background Technology

[0002] Point-to-point transparent transmission is a fundamental technology for data transmission in MSTP (Multi-Service Transport Platform) networks. In point-to-point transparent data transmission, the TX (transmitter) and RX (receiver) ends are typically asynchronous systems. There is a frequency difference between the clocks of the TX and RX ends. The clock frequency of the TX end needs to track or lock onto the clock frequency of the RX end to eliminate the frequency difference and ensure that the TX end transmits data completely and without errors.

[0003] The circuit that tracks the TX clock frequency to the RX clock frequency needs to dynamically monitor and compare the clock frequencies of the two, and dynamically adjust the TX clock frequency to achieve long-term frequency synchronization. When TX tracks the RX clock frequency to ensure data writing and reading at the same frequency and guarantee data transmission efficiency, existing technologies track the frequency by adding external circuitry or by parsing data packets and adding or deleting redundant bytes according to a frequency-matched FIFO (Asynchronous First-In-First-Out) buffer to eliminate the frequency difference between TX and RX.

[0004] However, the technique of achieving TX and RX clock synchronization through external circuitry typically requires an external clock chip for each TX channel to track the clock, increasing the complexity of the circuit board design. The extensive use of clock chips also leads to a larger circuit board area and increased costs. Simultaneously, ensuring high accuracy and low jitter of the output 8kHz clock requires high clock quality; it must be strictly aligned with the local reference clock, otherwise it cannot be used. On the other hand, frequency tracking through data packet parsing requires analyzing the received data, consuming more chip logic resources. In multi-channel pass-through scenarios, a single chip may not be able to handle the task, requiring multiple chips to complete the data transmission. This increases the complexity and cost of logic circuit design in data pass-through scenarios, and with a large number of chip resources used, power consumption increases significantly, thus affecting device performance. Summary of the Invention

[0005] This invention discloses a data pass-through method and system based on clock tracking, which reduces the logical resources occupied during data pass-through.

[0006] To achieve the above objectives, this invention discloses a data pass-through method based on clock tracking, applicable to a deserializer; wherein the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through method includes: Receive serial data sent by the data transmitter and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data; The clock recovery circuit is controlled according to the clock tracking mode to parse the serial data and obtain the write data and write clock. The serial data is subjected to edge detection according to the clock tracking mode to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence; The asynchronous cache circuit is controlled to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer to obtain cached data. The target tracking clock is determined based on the clock tracking mode, the write clock, and the data rate, and the frequency difference between the target tracking clock and the local clock is obtained. The local clock is then adjusted based on the frequency difference to obtain the read clock. The data is read from the asynchronous cache circuit according to the read clock, and the read data is sent to the data receiving end.

[0007] This invention discloses a clock-tracking-based data pass-through method. It receives serial data and matches it to a clock tracking mode, providing a basis for distinguishing between high-speed and low-speed processing scenarios and ensuring targeted optimization of resource usage in subsequent operations. The method controls a clock recovery circuit to parse the serial data according to the clock tracking mode. In high-speed mode, it directly recovers the write data and write clock, avoiding unnecessary processing steps. It performs edge detection and data recovery based on the clock tracking mode, obtaining the recovered data sequence and data rate in low-speed mode, replacing packet parsing to save logic resources. It combines the clock tracking mode, write clock, data rate, and local clock to control an asynchronous cache circuit to write data or recover the data sequence, ensuring that cache operations adapt to different rate scenarios. Based on the clock tracking mode, write clock, and data rate, it determines the target tracking clock and calculates the frequency difference, adjusting the local clock to obtain the read clock, directly eliminating the frequency difference without the need for external chips. Finally, it reads and sends the cached data according to the read clock, achieving error-free transmission with the sender clock tracking the receiver clock.

[0008] As a preferred example, the deserializer includes a serial transceiver; the receiving of serial data transmitted by the data transmitter and matching the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data includes: The serial transceiver receives the serial data sent by the data transmitter and obtains the line rate of the serial data. When the line rate is greater than the preset line rate threshold, the clock tracking mode of the asynchronous cache circuit is determined to be high-speed mode; When the line rate is less than or equal to a preset line rate threshold, the clock tracking mode of the asynchronous cache circuit is determined to be low-speed mode.

[0009] The above solution uses a serial transceiver to receive data and obtain the line rate, simplifying the data reception process by directly utilizing built-in components and avoiding the need for external circuitry. It automatically determines high-speed or low-speed mode by comparing the line rate with a preset threshold, optimizing resource allocation and performance without requiring complex data parsing operations. Specifically, obtaining the line rate as the decision-making basis reduces processing latency, and the application of the preset threshold ensures the accuracy and automation of mode switching, thus efficiently adapting to different rate scenarios in the initial stages of data pass-through.

[0010] As a preferred example, controlling the clock recovery circuit to parse the serial data according to the clock tracking mode to obtain the write data and the write clock includes: When the clock tracking mode is determined to be high-speed mode, the serial data is sent to the clock recovery circuit; The clock recovery circuit is controlled to perform clock and data synchronization recovery processing on the serial data to obtain the write data sent by the data sending end and the sending clock of the data sending end, and the sending clock is used as the write clock.

[0011] The above solution, when the clock tracking mode is determined to be high-speed mode, directly sends serial data to the clock recovery circuit, avoiding the introduction of external circuits or complex data packet parsing, thereby reducing the need for additional hardware and logic resources; it controls the clock recovery circuit to perform clock and data synchronization recovery processing, ensuring precise alignment of data and clock, directly recovering the write data and transmit clock; and it uses the transmit clock as the write clock, simplifying the clock tracking process, realizing efficient and low-cost parsing operations in high-speed mode, and improving the overall system performance.

[0012] As a preferred example, the step of detecting edge transitions of the serial data according to the clock tracking mode to recover the serial data, obtain a recovered data sequence, and acquire the data rate of the recovered data sequence includes: When the clock tracking mode is determined to be low-speed mode, the serial data is sampled at high speed according to a preset oversampling clock to obtain an oversampling data stream; wherein, the frequency of the oversampling clock is higher than the line rate. Edge detection is performed on the oversampled data stream to obtain the offset value of the edge position in the oversampled data stream; Based on the offset value, insert or delete data bits in the oversampled data to obtain the recovered data sequence; A data validity control signal is generated based on the insertion or deletion operation to restore the data sequence; wherein, the data control signal includes an insertion control signal, a deletion control signal, and an original control signal; wherein, the insertion control signal is used to indicate that the restored data sequence output within multiple consecutive clock cycles contains additional compensated data bits; the deletion control signal is used to indicate that no restored data sequence is output within multiple clock cycles; the original control signal is used to indicate that the insertion or deletion operation does not exist within multiple consecutive clock cycles; The frequency of each type of signal among the inserted control signal, deleted control signal and original control signal within a preset time period is counted, so as to determine the time distribution pattern of the effective control signal of the data based on the frequency and the preset time period; The data rate of the recovered data sequence within the preset duration is obtained according to the time distribution pattern.

[0013] When the clock tracking mode is determined to be low-speed mode, the above scheme performs high-speed sampling based on a preset oversampling clock. This leverages the advantage of high-frequency sampling in capturing data details, avoiding the potential accuracy deficiencies that might result from direct processing in low-speed mode. Edge detection is performed on the oversampling data stream to obtain offset values. Clock differences are identified by detecting data change points, laying the foundation for subsequent adjustments. Data bit insertion or deletion operations are performed based on the offset values ​​to dynamically compensate for clock frequency differences, ensuring the integrity of the restored data sequence. Data valid control signals are generated based on the insertion or deletion operations, including insertion, deletion, and original signals, to monitor data stream changes in real time by indicating the data operation status. The frequency of various signals within a preset duration is statistically analyzed to determine the time distribution pattern based on frequency and duration, quantifying the occurrence pattern of control signals. The data rate is obtained based on the time distribution pattern, and the actual rate is derived from the statistical pattern to achieve accurate measurement. The entire process integrates oversampling and signal analysis, reducing the need for external circuits or complex analysis and optimizing resource utilization.

[0014] As a preferred example, the step of controlling the asynchronous cache circuit to write the write data or the recovered data sequence according to the clock tracking mode, the write clock, the data rate, and the local clock of the deserializer to obtain cached data includes: When the clock tracking mode is determined to be high-speed mode, the write clock is written to the asynchronous cache circuit so that the asynchronous cache circuit caches the write data according to the write clock to obtain cached data; When the clock tracking mode is determined to be low speed mode, the local clock of the deserializer and the data valid control signal corresponding to the data rate are written into the asynchronous buffer circuit in real time. When the data valid control signal is the insertion control signal or the original control signal, the asynchronous buffer circuit buffers the recovered data sequence according to the local clock to obtain buffered data.

[0015] The above scheme controls the write operation based on clock tracking mode, ensuring adaptability in different modes. In high-speed mode, the write clock is directly written to the asynchronous cache circuit, simplifying the caching process and avoiding complex processing. In low-speed mode, the write and data rate are synchronized by writing the local clock and data valid control signal in real time. When the data valid control signal is the insertion control signal or the original control signal, the recovered data sequence is cached according to the local clock, ensuring that the write is only performed when the data is valid, preventing inconsistencies caused by invalid operations.

[0016] As a preferred example, the step of determining the target tracking clock based on the clock tracking mode, the write clock, and the data rate, and obtaining the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock, includes: When the clock tracking mode is determined to be high-speed mode, the write clock is determined to be the target tracking clock; The frequency difference between the write clock and the local clock is obtained, and the frequency of the local clock is adjusted according to the frequency difference to obtain the read clock.

[0017] When determining the clock tracking mode to be high-speed, the above scheme first identifies the high-speed data transmission scenario, ensuring that the adjustment process only applies to high line-rate environments, thereby optimizing resource allocation. Next, the write clock is determined as the target tracking clock. This leverages the characteristic that the write clock directly reflects the transmitter clock in high-speed mode, simplifying the target clock selection process without requiring additional logic or external components. Then, the frequency difference between the write clock and the local clock is obtained. By directly comparing their frequencies, the difference is precisely quantified, providing an accurate basis for adjustment. Finally, the frequency of the local clock is adjusted based on the frequency difference to obtain the read clock. This allows the local clock to dynamically match the transmitter clock, achieving frequency synchronization while reducing circuit complexity and cost, and improving data transmission efficiency.

[0018] As a preferred example, the step of determining the target tracking clock based on the clock tracking mode, the write clock, and the data rate, and obtaining the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock, includes: When the clock tracking mode is determined to be low speed mode, the data rate value is used as the frequency value of the target tracking clock; The difference between the data rate value and the local clock frequency value is obtained, and the local clock frequency is adjusted according to the difference to obtain the read clock.

[0019] When the clock tracking mode is determined to be low-speed mode, the above scheme limits the application scenario and ensures that the method is optimized for the characteristics of low-speed data transmission. Using the data rate value as the target tracking clock frequency value leverages the advantage that the data rate directly reflects the actual transmission rate, making the target frequency more closely match data changes. The difference between the data rate value and the local clock frequency value is obtained, and by calculating the deviation between the actual rate and the local clock, a precise basis for adjustment is provided. The local clock frequency is adjusted according to the difference to obtain the read clock. The local clock is then dynamically calibrated based on this difference to ensure clock synchronization during data reading, thereby improving the accuracy of data transmission.

[0020] As a preferred example, the deserializer includes a serial transmitter; the step of obtaining read data from the asynchronous buffer circuit according to the read clock and sending the read data to the data receiver includes: The read data and the read clock are input to the serial transmitter, so that the serial transmitter performs parallel-to-serial conversion on the read data according to the read clock to obtain parallel data; The serial transmitter is controlled to send the parallel data to the data receiver.

[0021] The above scheme inputs the read data and read clock to the serial transmitter, directly utilizing internal components to process the data, reducing intermediate parsing steps and lowering logic resource consumption and power consumption. The serial transmitter performs parallel-to-serial conversion on the read data based on the read clock, obtaining parallel data. This conversion step, based on the read clock, ensures the accuracy and efficiency of data format conversion, preventing data loss or distortion caused by clock mismatch. Controlling the serial transmitter to send the parallel data to the data receiver achieves efficient end-to-end transparent transmission. The entire process is completed in a closed loop within the deserializer, improving data transmission reliability and system performance.

[0022] On the other hand, the present invention discloses a data pass-through system based on clock tracking, which is applicable to a deserializer; wherein, the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through system includes a pattern matching module, a data parsing module, a data recovery module, a data buffer module, a clock adjustment module, and a data pass-through module; The pattern matching module is used to receive serial data sent by the data sending end and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data. The data parsing module is used to control the clock recovery circuit to parse the serial data according to the clock tracking mode, so as to obtain the write data and the write clock. The data recovery module is used to perform edge detection on the serial data according to the clock tracking mode, so as to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence. The data caching module is used to control the asynchronous caching circuit to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer, so as to obtain cached data; The clock adjustment module is used to determine the target tracking clock according to the clock tracking mode, the write clock and the data rate, and to obtain the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock; The data pass-through module is used to obtain read data from the asynchronous cache circuit according to the read clock, and send the read data to the data receiving end.

[0023] This invention discloses a clock-tracking-based data pass-through system that receives serial data and matches it to a clock tracking mode, providing a basis for distinguishing between high-speed and low-speed processing scenarios and ensuring that subsequent operations optimize resource usage accordingly. The system controls a clock recovery circuit to parse serial data according to the clock tracking mode, directly recovering the write data and write clock in high-speed mode, avoiding unnecessary processing steps. It performs edge detection and data recovery based on the clock tracking mode, obtaining the recovered data sequence and data rate in low-speed mode, replacing packet parsing to save logic resources. Combining the clock tracking mode, write clock, data rate, and local clock, the system controls an asynchronous cache circuit to write data or recover the data sequence, ensuring that cache operations adapt to different rate scenarios. Based on the clock tracking mode, write clock, and data rate, the system determines the target tracking clock and calculates the frequency difference, adjusting the local clock to obtain the read clock, directly eliminating the frequency difference without the need for external chips. Finally, it reads and sends the cached data according to the read clock, achieving error-free transmission by tracking the receiver's clock with the sender's clock.

[0024] As a preferred example, the deserializer includes a serial transceiver; the pattern matching module includes a rate parsing unit and a pattern parsing unit. The rate resolution unit is used to receive the serial data sent by the data sending end through the serial transceiver and obtain the line rate of the serial data; The mode parsing unit is used to determine that the clock tracking mode of the asynchronous cache circuit is a high-speed mode when the line rate is greater than a preset line rate threshold, and to determine that the clock tracking mode of the asynchronous cache circuit is a low-speed mode when the line rate is less than or equal to the preset line rate threshold.

[0025] The above solution uses a serial transceiver to receive data and obtain the line rate, simplifying the data reception process by directly utilizing built-in components and avoiding the need for external circuitry. It automatically determines high-speed or low-speed mode by comparing the line rate with a preset threshold, optimizing resource allocation and performance without requiring complex data parsing operations. Specifically, obtaining the line rate as the decision-making basis reduces processing latency, and the application of the preset threshold ensures the accuracy and automation of mode switching, thus efficiently adapting to different rate scenarios in the initial stages of data pass-through. Attached Figure Description

[0026] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating the data pass-through method based on clock tracking disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the clock-tracking-based data pass-through system disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the deserializer disclosed in an embodiment of the present invention; Figure 4 This is a schematic flowchart of a clock-tracking-based data pass-through method for deserializers disclosed in an embodiment of the present invention; Figure 5 This is a schematic diagram of the position change along a data transition disclosed in an embodiment of the present invention; Figure 6 This is another schematic diagram of data transition along position change disclosed in an embodiment of the present invention; Figure 7 This is a timing diagram of a frequency discrimination module in high-speed mode disclosed in an embodiment of the present invention; Figure 8 This is a timing diagram of a frequency discrimination module in low-speed mode disclosed in an embodiment of the present invention; Figure 9 This is a schematic diagram of the state transition of a frequency control word generation module disclosed in an embodiment of the present invention; Figure 10 This is a schematic diagram of the connection between peripheral data and a deserializer disclosed in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example 1 Reference Figure 1 To improve the accuracy of clock tracking and reduce the cost of data pass-through, this embodiment discloses a data pass-through method based on clock tracking, applicable to a deserializer; wherein, the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through method includes: Step 101: Receive serial data sent by the data transmitter and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data.

[0030] In this embodiment, the step mainly includes: receiving the serial data sent by the data sending end through the serial transceiver and obtaining the line rate of the serial data; when the line rate is greater than a preset line rate threshold, determining that the clock tracking mode of the asynchronous buffer circuit is a high-speed mode; when the line rate is less than or equal to the preset line rate threshold, determining that the clock tracking mode of the asynchronous buffer circuit is a low-speed mode.

[0031] In this embodiment, the above steps use a serial transceiver to receive data and obtain the line rate, directly utilizing built-in components to simplify the data reception process and avoid the need for external circuitry. By comparing the line rate with a preset threshold, the high-speed or low-speed mode is automatically determined, optimizing resource allocation and performance without the need for complex data parsing operations. Specifically, obtaining the line rate as the decision-making basis reduces processing latency, and the application of the preset threshold ensures the accuracy and automation of mode switching, thereby efficiently adapting to different rate scenarios in the initial stage of data pass-through.

[0032] Step 102: Control the clock recovery circuit to parse the serial data according to the clock tracking mode to obtain the write data and write clock.

[0033] In this embodiment, the step mainly includes: when the clock tracking mode is determined to be a high-speed mode, sending the serial data to the clock recovery circuit; controlling the clock recovery circuit to perform clock and data synchronization recovery processing on the serial data to obtain the write data sent by the data sending end and the sending clock of the data sending end, and using the sending clock as the write clock.

[0034] In this embodiment, the above steps, when the clock tracking mode is determined to be high-speed mode, directly send serial data to the clock recovery circuit, avoiding the introduction of external circuits or complex data packet parsing, thereby reducing the additional hardware and logic resource requirements; control the clock recovery circuit to perform clock and data synchronization recovery processing, ensuring accurate alignment of data and clock, directly recovering the write data and transmission clock; and using the transmission clock as the write clock, simplifying the clock tracking process, realizing efficient and low-cost parsing operations in high-speed mode, and improving the overall system performance.

[0035] Step 103: Perform edge detection on the serial data according to the clock tracking mode to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence.

[0036] In this embodiment, the above steps mainly include: when the clock tracking mode is determined to be a low-speed mode, high-speed sampling of the serial data is performed according to a preset oversampling clock to obtain an oversampling data stream; wherein, the frequency value of the oversampling clock is higher than the line rate value; edge detection is performed on the oversampling data stream to obtain the offset value of the edge position in the oversampling data stream; data bit insertion or deletion operations are performed on the oversampling data according to the offset value to obtain a recovered data sequence; a data valid control signal for the recovered data sequence is generated according to the insertion or deletion operation; wherein, the data control signal includes an insertion control signal and a deletion control signal. The system includes an insertion control signal and an original control signal; wherein the insertion control signal is used to indicate that the output recovery data sequence contains additional compensated data bits within multiple consecutive clock cycles; the deletion control signal is used to indicate that no recovery data sequence is output within multiple clock cycles; the original control signal is used to indicate that the insertion or deletion operation does not exist within multiple consecutive clock cycles; the frequency of each type of signal among the insertion control signal, deletion control signal and original control signal is counted within a preset duration to determine the time distribution pattern of the data effective control signal based on the frequency and the preset duration; and the data rate of the recovery data sequence within the preset duration is obtained based on the time distribution pattern.

[0037] In this embodiment, when the clock tracking mode is determined to be low-speed mode, high-speed sampling is performed according to a preset oversampling clock. This leverages the advantage of high-frequency sampling in capturing data details and avoids the potential for insufficient accuracy caused by direct processing in low-speed mode. Edge detection is performed on the oversampling data stream to obtain offset values. Clock differences are identified by detecting data change points, laying the foundation for subsequent adjustments. Data bit insertion or deletion operations are performed based on the offset values ​​to dynamically compensate for clock frequency differences and ensure the integrity of the restored data sequence. Data valid control signals are generated based on the insertion or deletion operations, including insertion, deletion, and original signals, to monitor data stream changes in real time by indicating the data operation status. The frequency of various signals within a preset duration is statistically analyzed to determine the time distribution pattern based on frequency and duration, quantifying the occurrence pattern of control signals. The data rate is obtained based on the time distribution pattern, and the actual rate is derived from the statistical pattern to achieve accurate measurement. The entire process integrates oversampling and signal analysis, reducing the need for external circuits or complex analysis and optimizing resource utilization.

[0038] Step 104: Control the asynchronous cache circuit to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer to obtain cached data.

[0039] In this embodiment, the step mainly includes: when the clock tracking mode is determined to be a high-speed mode, the write clock is written to the asynchronous cache circuit so that the asynchronous cache circuit caches the write data according to the write clock to obtain cached data; when the clock tracking mode is determined to be a low-speed mode, the local clock of the deserializer and the data valid control signal corresponding to the data rate are written to the asynchronous cache circuit in real time; when the data valid control signal is an insertion control signal or the original control signal, the asynchronous cache circuit caches the recovered data sequence according to the local clock to obtain cached data.

[0040] In this embodiment, the above steps control the write operation according to the clock tracking mode, ensuring adaptability in different modes. In high-speed mode, the write clock is directly written to the asynchronous cache circuit, simplifying the caching process and avoiding complex processing. In low-speed mode, the local clock and data valid control signal are written in real time, realizing the synchronization of write and data rates. When the data valid control signal is the insertion control signal or the original control signal, the recovered data sequence is cached according to the local clock, ensuring that the write is only performed when the data is valid, preventing inconsistencies caused by invalid operations.

[0041] Step 105: Determine the target tracking clock based on the clock tracking mode, the write clock, and the data rate, and obtain the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock.

[0042] In this embodiment, the step mainly includes: when the clock tracking mode is determined to be a high-speed mode, determining the write clock as the target tracking clock; obtaining the frequency difference between the write clock and the local clock, and adjusting the frequency of the local clock according to the frequency difference to obtain the read clock; when the clock tracking mode is determined to be a low-speed mode, using the data rate value as the frequency value of the target tracking clock; obtaining the difference between the data rate value and the frequency value of the local clock, and adjusting the frequency of the local clock according to the difference to obtain the read clock.

[0043] In this embodiment, when determining the clock tracking mode to be high-speed mode, the method first identifies the high-speed data transmission scenario to ensure that the adjustment process is only applicable to high line rate environments, thereby optimizing resource allocation. Next, the write clock is determined as the target tracking clock. This leverages the characteristic that the write clock in high-speed mode directly reflects the transmitter clock, simplifying the target clock selection process without requiring additional logic or external components. Then, the frequency difference between the write clock and the local clock is obtained. By directly comparing their frequencies, the difference is precisely quantified, providing an accurate basis for adjustment. Finally, the frequency of the local clock is adjusted according to the frequency difference to obtain the read clock. This allows the local clock to dynamically match the transmitter clock, achieving frequency synchronization while reducing circuit complexity and cost, and improving data transmission efficiency. In low-speed mode, the method is optimized for the characteristics of low-speed data transmission. The data rate value is used as the frequency value of the target tracking clock, taking advantage of the fact that the data rate directly reflects the actual transmission rate, making the target frequency more closely match the data changes. The difference between the data rate value and the local clock frequency value is obtained, and the deviation between the actual rate and the local clock is calculated to provide a precise basis for adjustment. The local clock frequency is adjusted according to the difference to obtain the read clock. The local clock is then dynamically calibrated based on this difference to ensure clock synchronization when reading data, thereby improving the accuracy of data transmission.

[0044] Step 106: Obtain read data from the asynchronous cache circuit according to the read clock, and send the read data to the data receiving end.

[0045] In this embodiment, the step mainly includes: inputting the read data and the read clock to the serial transmitter, so that the serial transmitter performs parallel-to-serial conversion on the read data according to the read clock to obtain parallel data; and controlling the serial transmitter to send the parallel data to the data receiving end.

[0046] In this embodiment, the above steps input the read data and read clock to the serial transmitter, directly utilizing internal components to process the data, reducing intermediate parsing steps and lowering logic resource consumption and power consumption. The serial transmitter performs parallel-to-serial conversion on the read data according to the read clock to obtain parallel data. This conversion step, based on the read clock, ensures the accuracy and efficiency of data format conversion and prevents data loss or distortion caused by clock mismatch. Controlling the serial transmitter to send the parallel data to the data receiver achieves efficient end-to-end transparent transmission. The entire process is completed in a closed loop within the deserializer, improving the reliability of data transmission and system performance.

[0047] On the other hand, refer to Figure 2 This embodiment also discloses a data pass-through system based on clock tracking, applicable to a deserializer; wherein, the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through system includes a pattern matching module 201, a data parsing module 202, a data recovery module 203, a data buffer module 204, a clock adjustment module 205, and a data pass-through module 206.

[0048] The pattern matching module 201 is used to receive serial data sent by the data sending end and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data.

[0049] The data parsing module 202 is used to control the clock recovery circuit to parse the serial data according to the clock tracking mode, so as to obtain the write data and the write clock.

[0050] The data recovery module 203 is used to perform edge detection on the serial data according to the clock tracking mode in order to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence.

[0051] The data caching module 204 is used to control the asynchronous caching circuit to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer, so as to obtain cached data.

[0052] The clock adjustment module 205 is used to determine the target tracking clock according to the clock tracking mode, the write clock and the data rate, and to obtain the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock.

[0053] The data pass-through module 206 is used to obtain read data from the asynchronous cache circuit according to the read clock, and send the read data to the data receiving end.

[0054] In this embodiment, the deserializer includes a serial transceiver; the pattern matching module 201 includes a rate parsing unit and a pattern parsing unit.

[0055] The rate resolution unit is used to receive the serial data sent by the data sending end through the serial transceiver and obtain the line rate of the serial data.

[0056] The mode parsing unit is used to determine that the clock tracking mode of the asynchronous cache circuit is a high-speed mode when the line rate is greater than a preset line rate threshold, and to determine that the clock tracking mode of the asynchronous cache circuit is a low-speed mode when the line rate is less than or equal to the preset line rate threshold.

[0057] The data pass-through method and system based on clock tracking provided in this embodiment receive serial data and match it with a clock tracking mode, providing a basis for distinguishing between high-speed and low-speed processing scenarios and ensuring that subsequent operations optimize resource usage accordingly. It controls the clock recovery circuit to parse serial data according to the clock tracking mode, directly recovering the write data and write clock in high-speed mode, avoiding unnecessary processing steps. It performs edge detection and data recovery according to the clock tracking mode, obtaining the recovered data sequence and data rate in low-speed mode, replacing data packet parsing to save logic resources. It combines the clock tracking mode, write clock, data rate, and local clock to control the asynchronous cache circuit to write data or recover the data sequence, ensuring that cache operations adapt to different rate scenarios. Based on the clock tracking mode, write clock, and data rate, it determines the target tracking clock and calculates the frequency difference, adjusting the local clock to obtain the read clock, directly eliminating the frequency difference without the need for external chips. Finally, it reads the cached data according to the read clock and sends it, achieving error-free transmission by tracking the receiver's clock with the sender's clock.

[0058] Example 2 To address the technical problems in existing technologies, such as increased tracking costs due to the addition of clock chips or the occupation of logic resources due to data packet parsing, this embodiment discloses a deserializer. This deserializer converts an external clock circuit into a logic circuit, reducing the need for external circuit design and chip usage. Furthermore, it allows for direct fine-tuning of the data clock frequency by dynamically adjusting the frequency control word, eliminating the need for high-precision clock frequencies. By dynamically controlling the clock, the read speed of the asynchronous FIFO is adjusted, ensuring the waterline clock operates within a safe and stable range, and data is transmitted correctly without affecting performance in all aspects.

[0059] Specifically, the deserializer provided in this embodiment includes, as follows: Figure 3 The circuit structure is shown below. Figure 3As shown, the deserializer includes an oversampling recovery module (recover module), a bit width conversion module (bshift module), an asynchronous first-in-first-out buffer module (asynchronous FIFO module), a frequency discriminator module (frequency_discriminator module), a frequency control word generation module (frequency_controlword_generate module), and a digital phase-locked loop (DPLL).

[0060] from Figure 3 It can be seen that the oversampling recovery module operates in low-speed mode. That is, after receiving the mode signal (model signal) from the host computer, it acquires the clock signal (FINAL_RXCLK0 signal) from the data receiver and performs edge detection on the parallel data (rx0_final_data) generated after sampling the data according to the local clock at the data receiver to obtain the valid data bits in the data. It then generates the data operation signal corresponding to the valid data bits and outputs the corresponding data-to-width conversion module. Figure 3 As shown, the oversampling recovery module outputs sampled data (Sample_data), a valid representation signal of the sampled data (Sample_data_vld), data processed by the sampling recovery module (Data_interp), and a valid flag signal of the processed data (Data_interp_vld).

[0061] Next, the bit-width conversion module receives data and flags from the oversampling recovery module to concatenate low-bit-width data into higher-bit-width data, and performs actual data insertion or deletion operations based on the add / delete flags. Specifically, from Figure 3 It can be seen that the key output of the bit width conversion module is the data_out_vld signal. The effective pulse width of this signal reflects the actual data bandwidth after the addition and deletion compensation. In low-speed mode, it serves as an equivalent indicator signal reflecting the original clock frequency difference at both ends.

[0062] The asynchronous first-in-first-out (FIFO) cache module is used for data writing and data reading; wherein, from Figure 3It can be seen that the write side (wr_clk) of the asynchronous FIFO buffer module is driven by the RX recovery clock, and the read side (rd_clk) is driven by the TX clock adjusted by DPLL. This buffer is used to cache data caused by instantaneous differences between the two clocks, preventing data loss or duplication. It is important to note that the write enable signal (write_en) of the asynchronous FIFO buffer module is jointly controlled by data_out_vld and full_flag (full flag). The read enable signal (read_en) of the asynchronous FIFO buffer module remains valid after the data volume in the FIFO reaches a certain depth (e.g., half-full, address = 4096). The read waterline signal (rdusedw) output by the asynchronous FIFO buffer module is used to reflect the amount of unread data in the FIFO in real time, serving as an important feedback indicator for system stability. Simultaneously, the asynchronous FIFO buffer module feeds back full / empty flag signals (full_flag / empty_flag) to prevent overflow or empty reads.

[0063] The frequency discrimination module is a sensor that measures the frequency difference between two clocks. Within the gate period of the reference pulse (generated by an external low-frequency crystal oscillator), the two clocks under test are counted respectively, and the absolute value of the frequency difference and the frequency relationship between the two are calculated by comparing the count values.

[0064] The frequency control word generation module receives the output of the frequency discrimination module and, in conjunction with the FIFO read waterline (rdusedw), determines whether the current system is in coarse or fine adjustment mode, and accordingly decides the adjustment amount of the frequency control word (delta_code0 ~ delta_code5). Here, delta_code0 represents an adjustment of 0 increments in the frequency control word; delta_code1 represents an adjustment of 1 increment; delta_code2 represents an adjustment of 2 increments; delta_code3 represents an adjustment of 3 increments; delta_code4 represents an adjustment of 4 increments; and delta_code5 represents an adjustment of 5 increments. In the coarse adjustment mode, when the frequency difference is greater than 100Hz, adjustments are made in larger steps according to the magnitude of the difference to achieve rapid convergence. In the fine adjustment mode, when the frequency difference is repeatedly less than 100Hz, fine adjustment is initiated. Minor adjustments are made based on whether the FIFO waterline is within a safe range and its changing trend to maintain long-term stability.

[0065] The digital phase-locked loop is a controlled clock generator used to receive frequency control words from the frequency control word generation module and dynamically adjust the frequency of its output clock accordingly. Its adjusted TX transmit clock also serves as the read clock (rd_clk) for the asynchronous FIFO.

[0066] according to Figure 3 The deserializer shown in this embodiment provides a clock-tracking-based data pass-through method for transmitting data by directly fine-tuning the clock frequency of the data through dynamic adjustment of the frequency control word. Specifically, the method includes, as follows: Figure 4 The steps shown are as follows: Step 401: Obtain the serial data sent by the data transmitter, and when the line rate of the serial data is found to be higher than a preset threshold, process the serial data through a preset clock recovery circuit to identify the write clock and write data, and control the asynchronous first-in-first-out cache module to cache the write data according to the write clock to obtain cached data.

[0067] In this embodiment, after receiving serial data from the data transmitter via the deserializer corresponding to the data receiver, the line rate value of the serial data is obtained, and the line rate value is compared with a preset line rate threshold to determine the transmission mode of the serial data. If the line rate value is less than or equal to the line rate threshold, the transmission mode of the serial data is determined to be a low-speed mode; and if the line rate value is greater than the line rate threshold, the transmission mode of the serial data is determined to be a high-speed mode.

[0068] When the serial data is determined to be in high-speed mode, the clock data recovery circuit (CDR) inside the SERDES deserializer can function normally, recovering a clock synchronized with the transmitting clock of the peer from the data stream. At this time, the serial data is directly fed into the write end of the asynchronous FIFO via a data selector. The data write enable signal (write_en) is jointly determined by the data valid signal output by the bit-width conversion module (data_out_vld, typically a constant valid pulse in high-speed mode) and the FIFO's full flag (full_flag): write_en = data_out_vld && !full_flag. Data is written to the FIFO using the RX recovery clock as the synchronous clock to obtain buffered data.

[0069] Step 402: When the line rate is detected to be lower than or less than a preset threshold, the serial data is subjected to edge detection by the oversampling recovery module and the bit width conversion module to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence. The asynchronous first-in-first-out buffer module is then controlled to write the recovered data sequence according to the data rate and the local clock of the deserializer to obtain buffered data.

[0070] In this embodiment, with the deserializer's CDR (Continuous Data Retrieval) disabled, taking 8x oversampling as an example, 1 bit of valid data typically consists of 8 consecutive 0s or 8 consecutive 1s, and 4 valid bits consist of 32 bits of oversampled data. In the oversampling recovery module, the position of the valid data transition edge is detected. After determining the position of the transition edge, data farther from the transition edge position is selected as valid data for recovery. For example, in 8x oversampling, the data edge position is at bit 0, so the valid data position is at bit 4. The process of determining the sampling position typically requires several clock cycles, so the oversampled data used for recovery also needs to be delayed and timed to ensure consistency between the oversampled data and the sampling position information. If the deserializer and the data transmitter share the same reference clock, the position of the received data transition edge is fixed. When the reference clock is asynchronous, the position of the received data transition edge will be offset, leading to two extreme cases when the circuit samples the data. Assuming the input data width is 32 bits, the data sampling process is as follows: Figure 5 or Figure 6 As shown. From Figure 5 It can be seen that if the current sampling point is 7 and the previous sampling point was 0, then the data from the two samples is considered duplicated, and the current sampling point is discarded. From Figure 6 It can be seen that if the current sampling point position is 0 and the sampling position of the previous sampling point is 7, then it is determined that 1 bit of valid data was collected less between the two samplings (the data in between was not sampled), so the 0th bit of the previous data is inserted before the current valid data.

[0071] Once the input data bit width and oversampling factor are determined, the output data bit width is also determined. When a discard operation occurs, the output data bit width is (32 / 8) - 1; when an insertion operation occurs, the output data bit width is (32 / 8) + 1; under other normal conditions, the output data bit width is 32 / 8. In actual use, the input of the oversampled data recovery module is connected to the data output of SERDES. The output of the oversampled data recovery module is connected to the bit width conversion module and continuously outputs valid data with a width of (32 / 8) * 2. In a homogeneous system, without any additions or deletions, VLD is a 2-division clock in the RX clock domain. In an asynchronous system, VLD will have two consecutive cycles of being pulled high or low.

[0072] Taking STM1 as an example, during the oversampled data processing, it's necessary to delete oversampled bits or add undersampled bits. The recover module restores the 32-bit data (8x oversampled) to 4-bit data and outputs addition and deletion flags. The bshift module concatenates the 4-bit data into 8-bit data and performs the addition / deletion operations. Originally, the RX user clock was 38.88MHz, outputting 4 bits of valid data per clock cycle. After passing through the bshift module, it becomes two 38.88MHz clock cycles outputting 8 bits. When four addition operations accumulate, two consecutive 38.88MHz clock cycles will output 8 bits of valid data; when four deletion operations accumulate, two consecutive 38.88MHz clock cycles will not output 8 bits of valid data. The data_out_vld signal also changes accordingly to the addition / deletion operations: it's pulled high for two consecutive clock cycles for addition and low for two consecutive clock cycles for deletion. After additions and deletions, the data indicated by `data_out_vld` is the original data sent by the other end. The reference pulse is a high level generated by the clock count of the low-frequency crystal oscillator for a specified time, held low for four clock cycles, and then pulled low. For example, if the specified reference pulse generation time is 1ms, it will go high once every 1ms, and the two clocks being discriminated will output a 1ms count value. If it is 1s, it will go high once every 1s, and the two clocks being discriminated will output a 1s count value.

[0073] In this embodiment, the asynchronous first-in-first-out (FIFO) buffer module is controlled to perform data caching based on the signal output by the bshift module and the local clock of the deserializer. This allows the asynchronous FIFO buffer module to cache the data based on the signal and the local clock, and when the data is determined to be valid based on the signal, it then caches the data based on the local clock to obtain cached data.

[0074] Step 403: Obtain the frequency difference between the target tracking failure and the local clock according to the frequency discrimination module, and adjust the local clock according to the frequency difference and the frequency control word generation module to obtain the read clock.

[0075] In this embodiment, the frequency discrimination module also needs to distinguish whether the RX clock is locked to data based on the operating mode. When operating in oversampling mode, it needs to discriminate the RX clock and TX clock based on whether the data_out_vld generated by the bit width conversion module is high; when operating in normal mode, it can directly discriminate the TX clock and RX clock. Specifically, the frequency discrimination module in high-speed mode is as follows: Figure 7 As shown, the frequency discrimination module in low-speed mode is as follows: Figure 8As shown. Specifically, in the frequency discrimination module, a reference clock output pulse is required, typically a low-frequency crystal oscillator clock on the board. The other two clocks being discriminated are counted independently using the reference pulse. Whenever the reference pulse goes high, the frequency counter results are compared, and the absolute value of the frequency difference between the two clocks is output, along with the frequency values ​​of the two clocks. The output results serve as an important basis for the clock follower module to adjust the clock frequency. The clocks being discriminated are the clocks on both sides of the FIFO: the write-side clock (RX recovery clock) and the read-side clock (TX clock).

[0076] When the system is asynchronous and the line rate is greater than 1Gbps, CDR can be enabled to lock data. The RX recovery clock frequency follows the peer's transmit clock frequency, and there is a frequency difference between it and the local TX clock frequency. The RX recovery clock can be directly used for frequency discrimination in the frequency discrimination module. If the line rate is too low, CDR cannot lock data. In this case, CDR locks the local reference clock, and the RX recovery clock frequency is the same as the local TX clock frequency. The RX recovery clock cannot be directly used for frequency discrimination. In this situation, the data_out_vld signal from the oversampling recovery module is needed as the frequency discrimination indicator signal.

[0077] Taking STM1 as an example, if the peer sends 155.52 Mbps of data, and the local clock uses a 1.24416 Gbps line rate to collect it, this is an 8x oversampling. If the phase of the peer data and the local clock remains relatively constant (same source system), then the edge position and sampling position will also remain constant. If there is a frequency difference between the peer data and the local clock, their phase will gradually change. If the local clock is greater than the peer's transmitting clock, the local clock will collect 1 bit more at some times, and vice versa. The accumulation of this change will cause the data edge position and sampling position to change.

[0078] Taking a reference clock of 25MHz as an example, its clock period is 40ns, f = 1(s) / t(ns). In the digital domain, f becomes the count value, that is, how many times 40ns need to be counted to obtain 1s. A reference pulse is obtained through the reference clock, and this reference pulse is the start and end point of the count for the two clocks being discriminated. Assuming that I set the reference pulse interval to 1s, that is, the two clocks being discriminated are the number of counts within 1s, then this number of counts is their frequency. Then, the two frequencies are subtracted and the absolute value is taken to obtain the absolute value of the frequency. In this embodiment, the absolute value of the frequency difference, that is, the counters of the two clocks being discriminated, are defined as 32 bits. The frequency difference register is defined as 33 bits, and the highest bit forms the sign bit. Whether the sign bit of the highest bit is 1 can be used to determine whether to invert the value of the 33-bit register and add 1 to obtain the absolute value. For example, when the 32nd bit is 1, the difference is a negative number. In this case, the [31:0] bits are inverted and 1 is added to obtain the absolute value of the frequency difference. If the 32nd bit is 0, then [31:0] is directly assigned to the absolute value of the frequency difference.

[0079] After obtaining the frequency difference from the frequency discrimination module, the state transition of the frequency control word generation module is as follows: Figure 9 As shown, from Figure 9 It is known that the frequency control word directly affects the currently adjusted clock frequency. A word that is too large or too small will lead to inaccurate clock tracking, causing the clock transmitted to the TX to change too quickly, thus affecting the reception of the next-level device. Using frequency discrimination as the generation condition for the frequency control word allows for precise control of the increment size of the frequency control word to be adjusted. Furthermore, the DPLL can control the output clock frequency to increase by 4Hz when the code value increases by 1.

[0080] The frequency difference needs to be considered in both positive and negative directions. When the TX clock frequency is greater than the RX clock frequency, the frequency control word needs to be decreased; when the TX clock frequency is greater than the RX clock frequency, the frequency control word needs to be increased. Adjusting the size of the frequency control word according to different needs can quickly converge the frequency control word and achieve rapid clock locking. When the frequency difference between TX and RX clock frequencies is greater than 100Hz, it enters the unlocked state. In the unlocked state, there are three adjustment levels: when the frequency difference is greater than 3000, the adjustment value is delta_code0; when the frequency difference is greater than 1000 but less than 3000, the adjustment value is delta_code1; and when the frequency difference is greater than 100 but less than 1000, the adjustment value is delta_code2.

[0081] When the frequency difference between the TX and RX clocks is less than 100Hz for ten consecutive times, the system enters a locked state and fine-tuning mode. When the frequency difference is greater than 100Hz, the system exits the locked state and fine-tuning mode. In the locked state, two adjustment levels are defined: when the FIFO current threshold is within the set safe range, the adjustment value is delta_code3; if it is within the threshold range but the threshold difference exceeds the set value within one second, the adjustment will be delta_code4 on top of delta_code3; if it exceeds the set safe threshold, the adjustment value is delta_code5. Setting six code values ​​requires satisfying the condition delta_code0 > delta_code1 > delta_code2 > delta_code5 > delta_code3. Here, "ten consecutive times" refers to ten consecutive frequency discrimination comparison results. If the reference pulse is specified as 1ms, then ten times is 10ms. For state transitions, the system only enters the state machine once after each comparison result is output to determine and adjust the code value. When adjustments are first made, the two clocks are significantly different, so a coarse adjustment is initiated, quickly bringing the clocks within a smaller range. Once within this smaller range, fine adjustment begins, with minimal changes in the code value. Each adjustment is based on the current comparison result, with a reference pulse specified as 1ms, so adjustments are made every 1ms. No further adjustments are made afterward, so there is no lag or jitter.

[0082] from Figure 3 As we can see, the read clock is a dynamically adjusted clock. When the read clock is greater than the write clock, the read threshold decreases; when it is less than the write clock, the read threshold increases. Therefore, 4096 is used as the starting condition for reading to prevent rapid readout or overflow. The data read by the FIFO must be continuous, so the read enable needs to be kept on after 4096, and the normal operation of the FIFO is ensured by controlling the clock speed.

[0083] Step 404: Read the cached data from the asynchronous first-in-first-out module according to the read clock, and send the obtained read data to the data receiving end.

[0084] In this embodiment, the write enable signal of the FIFO is jointly controlled by `full_flag` and `data_out_vld`, where `write_en = ((data_out_vld && !full_flag) == 1'b1) ? 1'b1 : 1'b0`. Because the bit-width conversion module's addition and deletion operations also change `data_fifo_vld_in`, the FIFO's write bandwidth varies with `data_out_vld`. The FIFO's read enable signal only goes high after half the FIFO depth has been written, to avoid data errors caused by rapid reads. If the FIFO depth is set to 8K, the read enable signal only goes high when the read pointer address is 4096. The FIFO's read waterline `rdusedw` indicates the address of the FIFO currently being read. When the bandwidths at both ends are strictly consistent, the waterline will not move up or down. When they are inconsistent, the read waterline moves up when the write data bandwidth increases and down when the write data bandwidth decreases.

[0085] In this embodiment, as Figure 9 As shown, in a practical FPGA system, various peripheral data connections to the deserializer are made through a hard-core clock selector (such as BUFGMUX) and a conventional data selector. From Figure 9 As can be seen, the connection enables the selection of the data source (raw data or processed data) entering the core processing module based on the model signal; and the selection of which RX channel data to forward to the TX channel according to user configuration. The clock generated by the DPLL is reliably distributed to the target TX transmitter and the asynchronous FIFO read side. The switching process involves channel reset and re-tracking. Since the reset time is much longer than the clock switching settling time, jitter or glitches at the moment of switching do not affect the final function of the system.

[0086] In the clock-tracking-based data pass-through method provided in this embodiment, all modules of the deserializer are implemented using digital logic, reducing costs and hardware design complexity, and facilitating portability to other similar projects. Simultaneously, the method supports dynamic switching between high-speed and low-speed operation, compatible with data processing in both modes, making its application scenarios more flexible and broader. Furthermore, the frequency control word generated by the frequency discrimination result is more precise with smaller frequency offsets, allowing for the cascading of more channels; moreover, directly using the Tx clock to track the Rx clock eliminates the need for decoding, simplifying code design and saving logic resources.

[0087] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A data pass-through method based on clock tracking, characterized in that, Suitable for deserializers; wherein the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through method includes: Receive serial data sent by the data transmitter and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data; The clock recovery circuit is controlled according to the clock tracking mode to parse the serial data and obtain the write data and write clock. The serial data is subjected to edge detection according to the clock tracking mode to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence; The asynchronous cache circuit is controlled to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer to obtain cached data. The target tracking clock is determined based on the clock tracking mode, the write clock, and the data rate, and the frequency difference between the target tracking clock and the local clock is obtained. The local clock is then adjusted based on the frequency difference to obtain the read clock. The data is read from the asynchronous cache circuit according to the read clock, and the read data is sent to the data receiving end.

2. The data pass-through method based on clock tracking according to claim 1, characterized in that, The deserializer includes a serial transceiver; The receiving data transmitter sends serial data and matches the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data, including: The serial transceiver receives the serial data sent by the data transmitter and obtains the line rate of the serial data. When the line rate is greater than the preset line rate threshold, the clock tracking mode of the asynchronous cache circuit is determined to be high-speed mode; When the line rate is less than or equal to a preset line rate threshold, the clock tracking mode of the asynchronous cache circuit is determined to be low-speed mode.

3. The data pass-through method based on clock tracking according to claim 2, characterized in that, The step of controlling the clock recovery circuit to parse the serial data according to the clock tracking mode to obtain the write data and the write clock includes: When the clock tracking mode is determined to be high-speed mode, the serial data is sent to the clock recovery circuit; The clock recovery circuit is controlled to perform clock and data synchronization recovery processing on the serial data to obtain the write data sent by the data sending end and the sending clock of the data sending end, and the sending clock is used as the write clock.

4. The data pass-through method based on clock tracking according to claim 2, characterized in that, The step of detecting edge transitions in the serial data according to the clock tracking mode to recover the serial data, obtaining a recovered data sequence, and acquiring the data rate of the recovered data sequence includes: When the clock tracking mode is determined to be low-speed mode, the serial data is sampled at high speed according to a preset oversampling clock to obtain an oversampling data stream; wherein, the frequency of the oversampling clock is higher than the line rate. Edge detection is performed on the oversampled data stream to obtain the offset value of the edge position in the oversampled data stream; Based on the offset value, insert or delete data bits in the oversampled data to obtain the recovered data sequence; A data validity control signal is generated based on the insertion or deletion operation to restore the data sequence; wherein, the data control signal includes an insertion control signal, a deletion control signal, and an original control signal; wherein, the insertion control signal is used to indicate that the restored data sequence output within multiple consecutive clock cycles contains additional compensated data bits; the deletion control signal is used to indicate that no restored data sequence is output within multiple clock cycles; the original control signal is used to indicate that the insertion or deletion operation does not exist within multiple consecutive clock cycles; The frequency of each type of signal among the inserted control signal, deleted control signal and original control signal within a preset time period is counted, so as to determine the time distribution pattern of the effective control signal of the data based on the frequency and the preset time period; The data rate of the recovered data sequence within the preset duration is obtained according to the time distribution pattern.

5. The data pass-through method based on clock tracking according to any one of claims 2-4, characterized in that, The step of controlling the asynchronous cache circuit to write the write data or the recovered data sequence according to the clock tracking mode, the write clock, the data rate, and the local clock of the deserializer to obtain cached data includes: When the clock tracking mode is determined to be high-speed mode, the write clock is written to the asynchronous cache circuit so that the asynchronous cache circuit caches the write data according to the write clock to obtain cached data; When the clock tracking mode is determined to be low speed mode, the local clock of the deserializer and the data valid control signal corresponding to the data rate are written into the asynchronous buffer circuit in real time. When the data valid control signal is the insertion control signal or the original control signal, the asynchronous buffer circuit buffers the recovered data sequence according to the local clock to obtain buffered data.

6. The data pass-through method based on clock tracking according to claim 2, characterized in that, The step of determining the target tracking clock based on the clock tracking mode, the write clock, and the data rate, and obtaining the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock, includes: When the clock tracking mode is determined to be high-speed mode, the write clock is determined to be the target tracking clock; The frequency difference between the write clock and the local clock is obtained, and the frequency of the local clock is adjusted according to the frequency difference to obtain the read clock.

7. The data pass-through method based on clock tracking according to claim 2, characterized in that, The step of determining the target tracking clock based on the clock tracking mode, the write clock, and the data rate, and obtaining the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock, includes: When the clock tracking mode is determined to be low speed mode, the data rate value is used as the frequency value of the target tracking clock; The difference between the data rate value and the local clock frequency value is obtained, and the local clock frequency is adjusted according to the difference to obtain the read clock.

8. The data pass-through method based on clock tracking according to any one of claims 6-7, characterized in that, The deserializer includes a serial transmitter; the step of obtaining read data from the asynchronous buffer circuit according to the read clock and sending the read data to the data receiver includes: The read data and the read clock are input to the serial transmitter, so that the serial transmitter performs parallel-to-serial conversion on the read data according to the read clock to obtain parallel data; The serial transmitter is controlled to send the parallel data to the data receiver.

9. A data pass-through system based on clock tracking, characterized in that, This is applicable to a deserializer; wherein the deserializer includes a clock recovery circuit and an asynchronous buffer circuit; the clock recovery circuit is signal-connected to the asynchronous buffer circuit; the data pass-through system includes a pattern matching module, a data parsing module, a data recovery module, a data buffer module, a clock adjustment module, and a data pass-through module; The pattern matching module is used to receive serial data sent by the data sending end and match the clock tracking mode of the asynchronous buffer circuit according to the line rate of the serial data. The data parsing module is used to control the clock recovery circuit to parse the serial data according to the clock tracking mode, so as to obtain the write data and the write clock. The data recovery module is used to perform edge detection on the serial data according to the clock tracking mode, so as to recover the serial data, obtain the recovered data sequence, and acquire the data rate of the recovered data sequence. The data caching module is used to control the asynchronous caching circuit to write the write data or the recovery data sequence according to the clock tracking mode, the write clock, the data rate and the local clock of the deserializer, so as to obtain cached data; The clock adjustment module is used to determine the target tracking clock according to the clock tracking mode, the write clock and the data rate, and to obtain the frequency difference between the target tracking clock and the local clock, so as to adjust the local clock according to the frequency difference to obtain the read clock; The data pass-through module is used to obtain read data from the asynchronous cache circuit according to the read clock, and send the read data to the data receiving end.

10. The data pass-through system based on clock tracking according to claim 9, characterized in that, The deserializer includes a serial transceiver; the pattern matching module includes a rate parsing unit and a pattern parsing unit. The rate resolution unit is used to receive the serial data sent by the data sending end through the serial transceiver and obtain the line rate of the serial data; The mode parsing unit is used to determine that the clock tracking mode of the asynchronous cache circuit is a high-speed mode when the line rate is greater than a preset line rate threshold, and to determine that the clock tracking mode of the asynchronous cache circuit is a low-speed mode when the line rate is less than or equal to the preset line rate threshold.

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