Multi-mode data-driven clock recovery method and apparatus

Abstract

A multi-mode data-driven clock recovery method and apparatus are disclosed. The method includes, in a vector signaling mode of data reception: generating a plurality of data-driven phase error signals from a plurality of mutually orthogonal sub-channel outputs using a plurality of vector signaling comparators; generating a composite data-driven phase error signal from the plurality of data-driven phase error signals to adjust a local voltage-controlled oscillator used to sample the plurality of mutually orthogonal sub-channel outputs; in a non-return-to-zero signaling mode of data reception: operating one or more of the vector signaling comparators as non-return-to-zero mode comparators; generating a non-return-to-zero output from a respective differential input signal for each non-return-to-zero mode comparator and adjusting a respective voltage-controlled oscillator used to sample the non-return-to-zero output based on a phase error measurement of the non-return-to-zero output.

Description

[0001] This application is a divisional application of patent application No. 201880049361.1, filed on May 22, 2018, entitled "Multi-mode data-driven clock recovery circuit".

[0002] Cross-reference to related applications

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 509714, filed May 22, 2017, by Armin Tajalli and Ali Hormati, entitled “Multi-mode Data-Driven Clock Recovery Circuit,” the contents of which are incorporated herein by reference in their entirety for all purposes.

[0004] References

[0005] The following prior art applications are incorporated herein by reference in their entirety for all purposes:

[0006] The U.S. patent application, titled "Orthogonal Differential Vector Signaling," was filed on May 20, 2010, with publication number 2011 / 0268225, application number 12 / 784414, and inventors Harm Cronie and Amin Shokrollahi. It is hereinafter referred to as "Cronie 1."

[0007] U.S. patent application No. 2011 / 0302478, application No. 12 / 982777, application date December 30, 2010, inventors Harm Cronie and Amin Shokrollahi, entitled "High pin utilization, high power utilization chip-to-chip communication with common-mode noise immunity and synchronous switching output noise immunity", hereinafter referred to as "Cronie 2";

[0008] The U.S. patent application with application number 13 / 030027, application date February 17, 2011, inventors Harm Cronie, Amin Shokrollahi and Armin Tajalli, entitled “Method and System for Noise-resistant, High Pin Utilization and Low Power Communication Using Sparse Signaling Codes”, hereinafter referred to as “Cronie 3”;

[0009] The U.S. patent application with application number 13 / 176657, application date July 5, 2011, inventors Harm Cronie and Amin Shokrollahi, entitled “Method and System for Low-Power High-Pin-Utilization Communication Using Superimposed Signaling Codes”, hereinafter referred to as “Cronie 4”;

[0010] The U.S. patent application with application number 13 / 542599, application date July 5, 2012, inventors Armin Tajalli, Harm Cronie and Amin Shokrollahi, entitled “Method and Circuit for Efficient Balanced Code Processing and Detection”, hereinafter referred to as “Tajalli 1”;

[0011] The U.S. patent application with application number 13 / 842740, filed on March 15, 2013, and inventors Brian Holden, Amin Shokrollahi, and Anant Singh, entitled "Time-biased tolerance method and system for vector signaling codes for inter-chip communication and advanced detector for vector signaling codes for inter-chip communication", hereinafter referred to as "Holden 1";

[0012] The U.S. provisional patent application, entitled "Clock Embedded Vector Signaling Code", with application number 61 / 946574 and application date of February 28, 2014, is authored by Amin Shokrollahi, Brian Holden and Richard Simpson, and is referred to as "Shokrollahi 1".

[0013] The U.S. patent application with application number 14 / 612241, filed on August 4, 2015, and inventors Amin Shokrollahi, Ali Hormati, and Roger Ulrich, entitled “Method and Apparatus for Low Inter-symbol Interference Ratio and Low Power Inter-chip Communication”, hereinafter referred to as “Shokrollahi 2”.

[0014] The U.S. patent application with application number 13 / 895206, filed on May 15, 2013, and inventors Roger Ulrich and Peter Hunt, entitled “Circuit for Efficiently Detecting Vector Signaling Codes for Inter-Chip Communication by Difference Sum”, hereinafter referred to as “Ulrich 1”;

[0015] The U.S. patent application with application number 14 / 816896, application date August 3, 2015, inventors Brian Holden and Amin Shokrollahi, entitled "Orthogonal Differential Vector Signaling Code with Embedded Clock", hereinafter referred to as "Holden2";

[0016] The U.S. patent application with application number 14 / 926958, filed on October 29, 2015, and inventors Richard Simpson, Andrew Stewart, and Ali Hormati, entitled "Clock Data Alignment System for Vector Signaling Code Communication Links", hereinafter referred to as "Stewart 1";

[0017] The U.S. patent application with application number 14 / 925686, application date October 28, 2015, inventor Armin Tajalli, entitled "Improved Phase Interpolator", hereinafter referred to as "Tajalli 2";

[0018] The application number is 62 / 286717, the application date is January 25, 2016, the inventor is Armin Tajalli, and the title is "Voltage Sampling Driver with Greater High Frequency Gain", hereinafter referred to as "Tajalli 3";

[0019] The U.S. provisional patent application, entitled "High-Performance Phase-Locked Loop," was filed on April 22, 2016, with Armin Tajalli as the inventor. It is referred to as "Tajalli 4."

[0020] The U.S. Provisional Patent Application No. 62 / 395993, filed on September 16, 2016, with Armin Tajalli as the inventor, entitled “Matrix Phase Detection Element for Phase-Locked Loops”, hereinafter referred to as “Tajalli 6”;

[0021] In addition, the following prior art references are cited in this application:

[0022] The patent number is 6509773, the application date is April 30, 2001, the inventor is Buchwald et al., and the title is "Phase Interpolation Apparatus and Method", hereinafter referred to as "Buchwald".

[0023] "Linear Phase Detection Using Two-Stage Latches", A. Tajalli et al., IEE Electronics Letters, 2003, hereinafter referred to as "Tajalli 5";

[0024] "Low-jitter, low-phase-noise 10GHz subharmonic injection-locked phase-locked loop with 65nm CMOS self-aligned DLL", Hong-Yeh Chang, Yen-Liang Yeh, Yu-Cheng Liu, Meng-Han Li and Kevin Chen, IEEE Transactions on Microwave Theory and Technique, Vol. 62, No. 3, March 2014, pp. 543-555, hereinafter referred to as "Chang et al."

[0025] "Low Phase-Noise 77GHz Fraction-N Frequency-Locked Loop with Delay-Locked Loop-Based Reference Multiplier for FMCW Radar", Herman Jalli Ng, Rainer Stuhlberger, Linus Maurer, Thomas Sailer and Andreas Stelzer, Proceedings of the 6th European Conference on Microwave Integrated Circuits, October 10-11, 2011, pp. 196-199, hereinafter referred to as "Ng et al."

[0026] "Design for Highly Noise Robust Clock Data Recovery Using Bandwidth Adaptive Hybrid PLL / DLL", Han-Yuan Tan, Harvard University Doctoral Dissertation, November 2006, hereinafter referred to as "Tan".

[0027] The patent number is 7492850, the application date is August 31, 2005, the inventors are Christian Ivo Menolfi and Thomas Helmut Toifl, and the title is "Phase-locked loop device with adjustable phase shift" in the United States, hereinafter referred to as "Menolfi";

[0028] "An uncorrected fractional-N frequency divider ring PLL using phase / current hybrid mode phase interpolation", Romesh Kumar Nandwana et al., IEEE Solid State Circuits Journal, Vol. 50, No. 4, April 2015, pp. 882-895, hereinafter referred to as "Nandwana". Technical Field

[0029] The embodiments of the present invention generally relate to communication system circuits, and more particularly to obtaining a stable and phase-correct receiver clock signal from a high-speed multi-line communication used for chip-to-chip communication. Background Technology

[0030] In modern digital systems, digital information must be processed efficiently and reliably. In this context, digital information is understood as information contained within discrete values ​​(i.e., discontinuous values). Digital information can be represented not only by bits and sets of bits, but also by numbers within a finite set.

[0031] To increase overall bandwidth, most chip-to-chip or device-to-device communication systems use multiple lines for communication. Each or each pair of these lines can be called a channel or link, and multiple channels form a communication bus between electronic devices. At the physical circuit level, the bus within a chip-to-chip communication system typically consists of packaged electrical conductors between the chip and the motherboard, packaged electrical conductors on the printed circuit board (PCB), or packaged electrical conductors within cables and connectors between PCBs. Furthermore, in high-frequency applications, microstrip or strip PCB lines can also be used.

[0032] Common bus line signal transmission methods include single-ended signaling and differential signaling. In applications requiring high-speed communication, these methods can be further optimized in terms of power consumption and pin utilization (especially in high-speed communication). Recently proposed vector signaling methods offer a more optimized trade-off between power consumption, pin utilization, and noise robustness in inter-chip communication systems. Such vector signaling systems convert the transmitter's digital information into a different representation space in the form of vector codewords, and select different vector codewords based on the characteristics of the transmission channel and the design constraints of the communication system to achieve a better trade-off between power consumption, pin utilization, and speed. This process is referred to as "encoding" in this application. The encoded codewords are transmitted from the transmitter to one or more receivers as a set of signals. The receivers invert the received signals corresponding to the codewords back into the original digital information representation space. This process is referred to as "decoding" in this application.

[0033] Regardless of the encoding method used, the signal received by the receiving device must be sampled at intervals (or its signal value must be recorded in other ways). Moreover, regardless of the delay, interference, and noise conditions of the transmission channel, the sampling interval must ensure that the sampled value optimally represents the original transmitted value. This clock data recovery (CDR) operation must not only be able to determine the appropriate sampling time but also be able to continuously determine the appropriate sampling time in order to dynamically compensate for constantly changing signal propagation conditions.

[0034] Many known CDR systems employ phase-locked loops (PLLs) or delay-locked loops (DLLs) to synthesize a local receive clock with frequencies and phases suitable for achieving accurate data sampling. Summary of the Invention

[0035] In order to reliably detect data values ​​transmitted by a communication system, the receiver must accurately measure the amplitude of the received signal value at carefully selected time points. Currently, there are various known methods that can facilitate such reception measurements, including receiving one or more dedicated clock signals associated with the transmitted data stream, extracting embedded clock signals from the transmitted data stream, and synthesizing a local receive clock based on known properties of the transmitted data stream.

[0036] Generally, the receiver implementation of this timing method is called clock data recovery (CDR), and often uses phase-locked loops (PLLs) or delay-locked loops (DLLs) to synthesize a local receive clock with the desired frequency and phase characteristics.

[0037] In both PLL and DLL implementations, an error signal is generated by comparing the relative phase of the received reference signal and the local clock signal (or, in some other implementations, their relative frequencies) using a phase detector. This error signal is then used to correct the phase and / or frequency of the local clock source, thereby minimizing the error. Because this feedback loop characteristic results in a fixed phase relationship (e.g., a 0-degree or 90-degree phase difference) between the reference signal and the local clock in a given PLL implementation, the phase difference is typically set to a target value (e.g., a 45-degree phase difference) different from the aforementioned value by introducing additional fixed or variable phase adjustment to facilitate data detection by the receiver.

[0038] In the method and system of this application: a data-driven phase comparison circuit receives multiple data signals in parallel from multiple multi-input comparators (MICs) connected to a multi-line bus, and receives one or more phases of a local oscillator signal, wherein at least one MIC is connected to at least three lines of the multi-line bus, and the data-driven phase comparison circuit includes multiple partial phase comparators; multiple partial phase error signals are generated using the partial phase comparators, each partial phase error signal being generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal among the multiple data signals, and by comparing the corresponding phase of the local oscillator signal with the corresponding data signal when it is determined that a transition has occurred in the corresponding data signal; and a composite phase error signal is generated by summing the multiple partial phase error signals, the composite phase error signal being used to lock the local oscillator that generates one or more phases of the local oscillator signal.

[0039] In this embodiment, the phase detection element is combined with the phase adjustment element, thereby reducing circuit node capacitance and circuit delay. These improvements further increase loop stability and improve PLL latch-up characteristics. The improved PLL latch-up characteristics include a larger loop latch-up bandwidth, which reduces clock jitter and improves power supply noise suppression.

[0040] In this embodiment, the received reference clock signal is further converted into multiple reference clock phases via a delay-locked loop, thereby transforming the PLL phase comparison operation into multiple comparisons between the reference clock phases and local clock phases. Subsequently, the results of the multiple comparisons are summed or weighted summed, and the summed result is used as the error feedback signal of the PLL. In another embodiment of this application, multiple comparisons are performed between a single received reference clock phase and multiple local clock phases, and the weighted sum of the results of the multiple comparisons is used as the error feedback signal of the PLL. In at least one other such embodiment, the weighted sum includes two-dimensional time-domain filtering. Attached Figure Description

[0041] Figure 1 A block diagram of one implementation that can encode and transmit five data bits and a clock signal via an eight-line communication channel.

[0042] Figure 2 To and Figure 1 Block diagram of a transmitter-compatible receiver implementation.

[0043] Figure 3 for Figure 2 A detailed block diagram of one implementation of the clock recovery circuit used in the receiver.

[0044] Figure 4A , Figure 4B , Figure 4C The diagram shows three implementations of phase detectors suitable for use in phase-locked loop elements of clock recovery circuits.

[0045] Figure 5 This is a schematic diagram of one implementation that integrates an XOR phase detector and a clock phase interpolator.

[0046] Figure 6A This is a schematic diagram of a clock-controlled data latch. Figure 6B This is a schematic diagram of another implementation of a clock-controlled data latch that integrates a clock phase interpolator.

[0047] Figure 7A and Figure 7B This is a schematic diagram of an implementation that integrates a state machine phase detector and a clock phase interpolator.

[0048] Figure 8 A schematic diagram of a charge pump implementation suitable for further integration with a phase comparator implementation.

[0049] Figure 9 This is a block diagram illustrating another implementation of comparing multiple phases of a reference clock with multiple local clock phases.

[0050] Figure 10 Another implementation block diagram showing multiple comparisons between a single reference clock and multiple local clock phases.

[0051] Figure 11A This is a weighted XOR phase detector according to some implementations.

[0052] Figure 11B A block diagram illustrating a matrix phase comparison implementation between M reference phases and N local clock phases.

[0053] Figure 12A and Figure 12B for Figure 5A block diagram of an alternative implementation of an integrated phase detector and phase interpolator implementation.

[0054] Figure 13A This is a timing diagram of a folded phase detector according to some embodiments.

[0055] Figure 13B This is a timing diagram of the reverse clipping effect according to some implementation methods.

[0056] Figure 14A and Figure 14B The following are timing diagrams of an array XOR phase detector and a single XOR phase detector according to some implementations.

[0057] Figure 15 The diagram shows an XOR-based phase comparator and a correction signal applied to a loop filter, according to some embodiments.

[0058] Figure 16 The image shows a time-domain error signal generated by a matrix row-based phase comparator according to some implementations.

[0059] Figure 17 The diagram illustrates phase interpolation achieved, according to some implementations, by inserting locking points between two adjacent diagonals of a two-dimensional phase comparator matrix.

[0060] Figure 18 The diagram illustrates the higher resolution achieved by the phase interpolator in a diagonal multiphase detector structure according to some embodiments.

[0061] Figures 19A to 19D The diagram shows various partial phase comparator architectures according to some implementations.

[0062] Figure 20 The diagram illustrates an exemplary XOR phase comparator architecture according to some implementations.

[0063] Figure 21 The following is an illustration based on some implementation methods. Figure 20 The timing diagram of the output current Iout of the XOR phase comparator is shown.

[0064] Figure 22 This is a simulated phase comparator response according to some implementations.

[0065] Figure 23 The results are simulations of phase-locked loop bandwidth based on some implementation methods.

[0066] Figure 24 This is a block diagram of an oversampled multiphase feedback phase-locked loop (MPLL) according to some implementations.

[0067] Figure 25This is a block diagram of a receiver according to some implementation methods.

[0068] Figure 26 This is a block diagram of a clock recovery circuit that operates on a detected data signal according to some implementation methods.

[0069] Figure 27 This is a block diagram of a matrix phase comparator that operates on a detected data signal according to some implementation methods.

[0070] Figure 28 This is a flowchart of a method according to some implementation methods.

[0071] Figure 29 This is a block diagram of an edge-triggered binary (Bang-Bang) phase detector.

[0072] Figure 30 This is a block diagram of a linear edge-triggered phase detector.

[0073] Figure 31 To and Figure 30 The waveform associated with the linear edge-triggered phase detector is shown.

[0074] Figure 32 This is a block diagram of a multi-mode data-driven clock recovery circuit according to some implementation methods.

[0075] Figure 33 This refers to an integrated non-return-to-zero (ENRZ) multiple-input comparator (MIC) network according to some implementations.

[0076] Figure 34 This is a block diagram of a sampling device employing predictive decision feedback equalization (DFE) according to some implementation methods.

[0077] Figure 35 This refers to a MIC network according to some implementation methods.

[0078] Figure 36 This is a flowchart of a method according to some implementation methods. Detailed Implementation

[0079] As described in Cronie 1, Cronie 2, Cronie 3, and Cronie 4, extremely high-bandwidth data communication links can be established between two integrated circuit devices within a system, for example, through vector signaling codes. Figure 1As shown in the implementation, vector signaling code symbols transmitted via multiple data communication channels jointly transmit the codeword of the vector signaling code. Depending on the specific vector signaling code used, the number of channels constituting the communication link can be as few as two, or as many as eight or more. Furthermore, one or more clock signals can be transmitted on independent communication channels, or the clock signal can be transmitted as a sub-channel component of the vector signaling code. Figure 1 In this embodiment, the illustrated communication link 120 consists of eight lines 125 that together transmit five data values ​​100 and a clock 105 between the transmitter 110 and the receiver 130.

[0080] Each symbol (e.g., each symbol transmitted in any single communication channel) can use multiple signal levels (typically three or more). When operating at channel rates above 10 Gbps, deep pipelined or parallel signal processing is required, further complicating the receiving behavior and rendering receiving methods where the previous received value is known as the current received value unusable.

[0081] The embodiments described in this application can also be applied to prior art permutation and sorting methods not covered by the vector processing methods in Cronie 2, Cronie 3, Cronie 4 and / or Tajalli 1. More generally, these embodiments can be applied to any communication or storage method that requires the mutual coordination of multiple channels or channel elements to generate a coherent overall result.

[0082] Receiver data detection

[0083] The following examples use a typical high-speed receiver implementation from Stewart 1 as background. This implementation is for illustrative purposes only and does not constitute a limitation.

[0084] like Figure 2 As shown, this exemplary data receiver includes eight identical continuous-time linear equalization (CTLE) processing stages 210, which operate on the aforementioned... Figure 1 The signals received by the eight lines shown as 120.

[0085] As described in *Tajalli 1*, *Holden 1*, and *Ulrich 1*, efficient detection of vector signaling codes can be achieved by linearly combining the input signals using a multi-input comparator (MIC) or mixer. For the 5b6w code used by the illustrated receiver above, five data bits can be detected by processing a weighted subset of the six received input data signals using five such mixers, without further decoding. Similarly, clock signal detection can be achieved by processing a combination of two received clock signals using an additional mixer. Figure 2 In this process, by using the above-mentioned set of six MIC mixers 220 to process the received and equalized signal, six detection signals MIC0 to MIC5 can be generated.

[0086] Because of the high data rates involved, multiple parallel receive processing stages can be used in the illustrated receiver. In one embodiment, the five detected data signals MIC0 to MIC4 are processed by four parallel receive data processing stages, each processing stage 230 including five data samplers and a downstream buffer. The outputs of these four processing stages are then recombined into a received data stream. Figure 2 In the scenario shown, the recombination process is performed by multiplexer 240.

[0087] Clock recovery circuitry (also known in the art as clock data recovery (CDR)) supports the aforementioned sampling measurements by extracting timing information from the data line itself or from a dedicated clock signal input, and uses the extracted information to generate a clock signal to control the time interval used by the data line sampling device. The actual clock extraction operation can be performed by well-known circuits such as phase-locked loops (PLLs) or delay-locked loops (DLLs), which can also generate higher-frequency internal clocks, multiple clock phases, etc., during operation to support receiver operation. Figure 2 In this implementation, the detected clock signal is obtained by MIC5 and then processed by 300 to extract the sampling clock with the correct timing for the four data processing stages.

[0088] Other implementations may omit a dedicated line for transmitting a separate clock signal, instead requiring the receiver to extract the clock from signal transitions occurring within the data line itself. It is well known in the art that the successful application of this technique presupposes a sufficiently high density of transitions occurring in the data line (or, in other words, a sufficiently small time interval between adjacent transitions), and / or that the PLL's frequency stability during idling is sufficient to maintain accurate data sampling time during non-transition time intervals. Several suitable vector signaling codes capable of ensuring the aforementioned transition density are described in *Shokrollahi 1*. Alternatively, to ensure the minimum required transition density at the receiver, existing coding techniques that force transitions, such as commonly used 8b10b and 64b66b codes, can be used to encode all or a subset of the data to be transmitted. In one implementation, bit-level transition coding can be performed on the composite data bitstream, or on the bitstream applied to a given subchannel, or on bits modulated within a given transmit and / or receive slicer subchannel, or on bits modulated within a given subchannel (or each subchannel) of each slicer.

[0089] Phase-locked loop overview

[0090] Existing literature provides a detailed description of phase-locked loops (PLLs). A typical PLL consists of a phase detector that compares an external reference signal with an internal clock signal, a low-pass filter that generates a clock signal by smoothing the resulting error value, and a variable-frequency clock source (typically a voltage-controlled oscillator (VCO)) that controls the smoothed error value to generate the aforementioned internal clock signal for processing by the phase detector. In a well-known variation of this PLL design, a clock divider can be placed between the VCO and the phase detector to lock the high-frequency clock output to a low-frequency reference signal.

[0091] In an alternative implementation, the variable frequency clock source is replaced by a variable delay element, such that its output (optionally multiple tap outputs) represents one or more successive time-delayed forms of the original input signal, rather than successive oscillator periods to be phase-compared with a reference input signal. For the purposes of this application, in such applications, particularly when associated with components such as phase detectors, phase interpolators, and charge pumps, a delay-locked loop (DLL) is considered to have equivalent functionality to a PLL.

[0092] Various forms of phase detectors are known in this art. As one example, without limitation, Figure 4AThe simplified XOR gate shown can be used to compare two square wave signals. Those skilled in the art will recognize that such a digital XOR output is a waveform with a variable duty cycle. When the two input signals have a 90-degree phase difference, this waveform, after being low-pass filtered into an analog error signal, can generate a proportional error signal centered at the range of its analog signal.

[0093] Figure 4B The diagram shows a more complex state machine phase detector. This phase comparator consists of two edge-triggered latches, clocked by the reference clock signal and an internal clock signal, respectively. A first received clock edge causes one of the "before" or "after" outputs to begin generating an output signal. Once either output begins, the latches reset to wait for the next comparison time interval. In other embodiments, a timing delay can be set in the reset path to achieve the additional reset pulse timing control shown by the "hold" signal in the diagram. Generally, the "before" and "after" phase comparison outputs serve as the "rising" and "falling" inputs of a charge pump, whose output is the aforementioned analog error value. That is, the rising signal can activate the first transistor circuit that charges the capacitor, thereby increasing the analog voltage; while the falling signal can activate the second transistor circuit that discharges the capacitor, thereby decreasing the voltage. Therefore, when the phase difference between the two input clock signals is 0 degrees, the analog error value remains unchanged, keeping the phase-locked loop in a stable locked state. Various known implementations of equivalent state machine phase detectors exist in the art, and these implementations can be equally applied in this application, but this does not imply any limitation on the invention. Some state machine implementations may be sensitive to both the phase difference and frequency difference between the input signals, thereby facilitating faster PLL locking at startup.

[0094] like Figure 4C As shown, a simple edge-clocked D flip-flop can also be used as a phase detector. At each rising edge of the local clock (CkPLL), the D input samples the state of the reference input (CkRef) (a square wave in this example). If its state is "high" (e.g., it has undergone a transition), the Q output is also "high," indicating that the reference signal is "forward"; if its state is "low" (e.g., it has not undergone a transition), the Q output is also "low," indicating that the reference signal is "backward." Compared to the previous example, this so-called binary (Bang-Bang) phase detector provides less subtle variation in the error results, allowing for a higher level of filtering to achieve loop stability.

[0095] Those skilled in the art will recognize that similar functional operation can be achieved regardless of the type of phase detector used in the PLL design; therefore, in general terms, the choice of phase detector is not a limitation. Furthermore, secondary design factors, including lock-in time, stability, and power consumption, must also be considered during the design process.

[0096] Receiver clock recovery

[0097] Figure 3 The illustrated receiver employs a PLL implementation. This PLL uses the received clock signal R5 as its phase-locked reference signal. In some implementations, a logic level shifter 310 may be used as an interface between the signal level provided by the detection MIC and the preferred phase comparator input level. The phase comparator 320 generates an output value after comparing the reference clock with the local clock provided by the VCO. This output value is low-pass filtered to provide an error value for subsequent correction of the operating frequency of the VCO 340. In some implementations, the phase comparator 320 outputs a digital waveform that needs to be converted into an analog error signal via implicit or explicit digital-to-analog conversion, or via an interface element such as a charge pump. In some implementations, this conversion may be combined with or in part with the entire low-pass filtering operation, this combination being only a non-limiting example, and may be accomplished through a digital filtering action illustrated as a charge pump switching action controlled by a digital control signal to generate an analog signal output.

[0098] In one embodiment, a ring oscillator 340, consisting of a series of identical gate devices forming a closed loop, is used as the timing source for the PLL's internal voltage-controlled oscillator (VCO). The frequency of the VCO can be changed by analog adjustment of at least one of the ring oscillator's gate propagation delay, gate rise / fall time, and gate switching threshold. This can be achieved using a switching capacitor bank, wherein, as a non-limiting embodiment, capacitive elements are selectively combined in parallel and / or series by applying a digital control signal, thereby changing the RC time constant. Furthermore, the output switching rise / fall time of the ring oscillator can be changed by increasing or decreasing the gate drive current source, thereby achieving effective delay adjustment. By sampling the output at equal intervals along the series of gate devices constituting the ring oscillator (i.e., sampling every equal number of ring oscillator gates), four data phase sampling clocks can be obtained, referred to in this application as the 0-degree clock, 90-degree clock, 180-degree clock, and 270-degree clock, respectively.

[0099] In one embodiment, the ring oscillator consists of eight identical sets of logic gates (i.e., one set of inverter circuits), such that the phase difference between any two sets is 45 degrees. In this embodiment, for example, the 0-degree, 90-degree, 180-degree, and 270-degree outputs can be obtained from the second, fourth, sixth, and eighth outputs, respectively. Since such a clock is periodic, the final tap point can be considered logically adjacent to the initial tap point, and the 0-degree and 360-degree phase differences are considered equivalent to each other. Because various variations of this design are known in the art, the number of components within the ring oscillator and the specific tap points providing the specific outputs should not be construed as constituting any limitation. For example, the 0-degree tap point can be located anywhere, because those skilled in the art will recognize that, regardless of the initial phase, the PLL can align the ring oscillator phase with the external reference phase during normal operation. Similarly, in other equivalent designs, the output clock phase may not have a square wave duty cycle; one example is the use of AND or OR gates with inputs obtained from different tap positions. In the illustrated receiver, the VCO preferably operates at a multiple of the receiving reference clock frequency; therefore, a frequency divider 350 is provided upstream of the phase detector to divide the VCO output by a corresponding coefficient. In one embodiment, the correct sampling clock rate is obtained by employing a binary (coefficient of 2) frequency divider 350. In another embodiment, instead of using a frequency divider, the VCO output is directly provided to the phase interpolator.

[0100] Each of the four sampling clock phases is appropriately timed to sample received data for one of the four parallel processing stages. Specifically, the internal clock ph000 is aligned to optimally trigger the data sampler in processing stage phase 0, the internal clock ph090 is aligned to optimally trigger the data sampler in processing stage phase 1, the internal clock ph180 is aligned to optimally trigger the data sampler in processing stage phase 2, and the internal clock ph270 is aligned to optimally trigger the data sampler in processing stage phase 3.

[0101] To offset the overall phase of the locked PLL signal from the phase of the reference clock input, a phase interpolator 360 provides its local clock output to the phase comparator. The output phase of this phase interpolator is controllably positioned between its input clock phases. Thus, under the control of the signal phase offset correction function, not only is the PLL locked to its fixed phase relationship, but the phase delay introduced by the fixed-phase offset phase interpolator 360 relative to the internal clock signal provided by the ring oscillator 340 is also controlled. Phase interpolators known in the art exist, such as those described in *Buchwald 1* and *Tajalli 2*.

[0102] In one embodiment, a phase interpolator 360 receives multiple local clock phases with a 90-degree phase difference from a ring oscillator 340. The phase interpolator can be controlled to select two adjacent clock input phases and then interpolate between them, thereby generating an output with a selected phase offset between the two selected values. For descriptive purposes, it can be assumed that the phase detectors used lock the PLL such that the phase difference between the two phase detector inputs is zero. Thus, in this example, when clock phases of 0 degrees and 90 degrees are applied as inputs to the phase interpolator, the phase of the PLL can be adjusted to lead the reference clock input by 0 to 90 degrees.

[0103] It is readily understood that using two clocks with different degrees and / or other phase detector designs can still yield equivalent results with similar phase shifts. However, as mentioned above, the locked phase difference in this case differs from the previous example. Therefore, the specific selected phase clock and specific phase detector design described in this application do not constitute a limitation.

[0104] In the prior art, Nandwana describes a fractional-N divider clock multiplier PLL, in which a single reference clock is compared in phase with two local clocks obtained by different integer division ratios, and phase quantization errors are offset by interpolation between two dynamically selected phase error results.

[0105] Phase detector with interpolator

[0106] As communication channel data rates increase, the inherent and parasitic circuit node capacitances cause circuit delays and limit the effective loop response bandwidth, making it increasingly difficult to maintain acceptable PLL locking range and accuracy. Figure 5 The illustration shows an embodiment that provides improved response characteristics suitable for such high-speed operation. Those skilled in the art will recognize that this embodiment is a CMOS design that provides symmetrical operation for positive and negative output offsets and integrates elements from both a phase interpolator and a phase detector design. This tight integration reduces node capacitance and facilitates the required high-speed operation, while its balanced differential structure simplifies the control of charge and discharge currents.

[0107] Consistent with conventional designs, the PLL's VCO (or clock divider driven by the VCO) provides local oscillator inputs to phase interpolator elements 510 and 515, which are used to jointly set the effective local clock phase. As shown, there are four local oscillator phases offset from each other by 90 degrees, corresponding to two phases in an orthogonal relationship and their complementary signals, thus labeled +I, +Q and -I, -Q respectively, enabling phase adjustment across the entire 360 ​​degrees, or "four-quadrant" phase adjustment. In other embodiments, the number of local oscillator phases can be reduced to two, or a phase difference other than 90 degrees can be used, or clock phases can be selected from a set of four or more inputs. As a non-limiting example, at least two clock phases to be interpolated can be selected from a set of eight input clock phases.

[0108] In a first embodiment, the phase interpolation element 510 includes four mixer elements, each mixer element including a pair of differential transistors and a controlled current source, and having a common differential output driven by the four parallel mixer elements. Therefore, the configuration of the current source IA(i) controls the amount of the local oscillator phase +I supplied to the common output ckp. Similarly, the current source IA(-i) controls the amount of the complementary output phase -1 in the output, IA(q) controls the amount of phase +Q, and IA(-q) controls the amount of phase -Q. It will be readily understood by those skilled in the art that the four current sources can be configured to generate an output clock at Ckp with any desired phase relationship relative to the PLL local clock input.

[0109] Similarly, the current sources IB(i), IB(-i), IB(q), and IB(-q) of the phase interpolator element 515 can be configured to obtain an output clock at the Ckn terminal with any desired phase relationship relative to the PLL local clock input. Typically, CkPLLp and CkPLLn can be configured to have a complementary relationship, thereby providing balanced complementary positive and negative current amplitudes to the phase detector 520. However, non-complementary IA and IB values ​​can also be configured to obtain specific results. As a non-limiting example, in one implementation, the IA and IB values ​​can be adjusted separately, thereby obtaining a higher resolution phase adjustment compared to implementations that maintain completely complementary IA and IB values.

[0110] The second input to the phase detector 520 is an external reference clock CkRef+ / CkRef-, used to generate the phase error output currents VCOctl+ / VCOctl-. In an improved embodiment, the two external reference clocks have opposite polarities but are not necessarily complementary phases, so that the positive polarity comparison result and the negative polarity comparison result represent different phase comparison results. This improved embodiment can be combined with non-complementary IA and IB bias configurations to achieve independent local clock phase adjustment during the different phase comparison processes described above. That is, in one embodiment, the CkRef input at the top of the phase comparator 520 is a first phase selected from the available reference clock phases in the circuit, and the current IA is adjusted to provide a corresponding insertion phase offset relative to the selected first phase. At the same time, the CkRef input at the bottom of the phase comparator 520 is a second phase selected from the available reference clock phases in the circuit, and the current IB is adjusted to provide a corresponding insertion phase offset relative to the selected second phase. These two relative phase offsets are equal in magnitude.

[0111] The value of the phase interpolator current source can be configured by external control logic, including but not limited to hardware configuration registers, control processor output registers, and hardware CDR adjustment logic.

[0112] Other phase detector implementation methods

[0113] Figure 5 The phase detector 520 in the illustrated embodiment is a... Figure 4A The same XOR device is used to generate the phase error output VCOctl by mixing the local clock CkPLL with the external reference clock CkRef. Figure 12A In other embodiments shown, a folded phase detector 1220 is employed, which is driven by current generated by a phase interpolator 510 combined with a current-absorbing device Ifix2 and a phase interpolator 520 combined with a current source Ifix1. The following will discuss... Figure 12A The folded phase detector embodiment shown is described in further detail. Consistent with the embodiment described above, the current sources IA(i), IA(-i), IA(q), and IA(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator output CkPLLp in a desired manner. In the above, current sources IB(i), IB(-i), IB(q), and IB(-q) are configured to insert the PLL clocks i, -i, q, and -q into the interpolator outputs CkPLLn and In the middle, phase comparator 1220 is also driven by received reference clocks CkRef+ and CkRef- to produce phase comparison results: phase error (+) and phase error (-). In some embodiments, the relative DC component of the inserted clock signal can be determined by monitoring a circuit node labeled "circuit balance feedback," and then the relative DC component can be adjusted by adjusting the values ​​of the configured current sources in 510 and 515. In some embodiments, each current source IA and IB receives seven control bits. It should be noted that the embodiments of the present invention are not limited to receiving seven control bits, and any number of control bits can be used, for example, depending on the design constraints of the phase interpolator resolution. In some embodiments, current sources IA and IB are equal (e.g., IA = IB for + / -i and + / -q). In such embodiments, the resolution of phase interpolators 510 and 515 is 7 bits. In other embodiments, additional resolution can be achieved by shifting IB relative to IA, or by shifting IA relative to IB. In one exemplary embodiment, IA = IB + 8, where 8 is the decimal shift amount of the control bit of each current source IB obtained by adding it to the control bit of each current source IA. In this embodiment, the P-side phase interpolator 510 and the N-side phase interpolator 515 receive two different VCO phases, and the phase detector acquires information from the different phases of the VCO. Because the phase interpolators 510 and 515 fuse information from different VCO phases, the PLL has more detailed PLL phase information, and the bandwidth of this PLL is higher than that of a conventional PLL.

[0114] The implementation of "IA = IB + shift amount" is a special case of a matrix phase comparator with two phase comparators. The first phase comparator (NMOS-side XOR comparator) compares the reference phase with a set of VCO feedback phases, and the second comparator (PMOS-side XOR comparator) compares the reference clock phase with another set of VCO feedback phases. Unlike the phase comparator in *Nandwana*, the VCO feedback phases in the above implementation have the same frequency, differing only in phase, and the current source value selected for interpolation between the phase comparison results is typically a static value, rather than a dynamically selected value cycle-by-cycle. The implementation of the matrix phase comparator will be described in more detail below. Accordingly, in some implementations, the PMOS+NMOS interpolator can be considered as two independent phase interpolators. In contrast, *Nandwana* only has one phase interpolator. Furthermore, if there is a significant difference between the PMOS-side weights and the NMOS-side weights, a smaller matrix PLL with a larger bandwidth can be constructed. In at least one implementation, there is a 20% gain difference between the two sides, where the bandwidth can also be increased proportionally.

[0115] In some implementations, the following methods may be used: Figure 12A The folded structure shown. Figure 12A and Figure 5 The illustrated implementation is similar, but differs in that a folded phase detector 1220 is used instead of phase detector 520. As shown, the folded phase detector 1220 includes current sources Ifix1 and Ifix2, which can be configured to provide a larger voltage margin to the PMOS phase interpolator current source IA and the NMOS phase interpolator current source IB. Furthermore, the phase detector 1220 includes a pair of transistor branches connected to CkPLLp and CkPLLn. For illustrative purposes, it is assumed that phase interpolators 510 and 515 only have IA(i) and IB(i), with these two current sources turned on to represent the VCO phase ph0000. When CkRef is offset by 90 degrees relative to ph0000, the folded phase detector 1220 will be in a locked state. Figure 13A As shown, during the first 180 degrees (1) of a cycle, for the preceding 90 degrees (2), the PMOS phase interpolator 510 charges the (-) terminal of the phase error signal with current Ip via transistor 1206. Simultaneously, the NMOS phase interpolator 515 discharges the (-) terminal of the phase error signal with current In via transistor 1208. Similarly, during the following 90 degrees (3), the (+) terminal of the phase error signal is charged with current Ip via transistor 1202 and discharged with current In via transistor 1204. As shown, Ifix2 draws a fixed amount of current from the current provided by the PMOS phase interpolator 510, and Ifix1 provides a certain amount of current to the NMOS phase interpolator 515 to prevent the current source in the NMOS phase interpolator from drawing excessive current from the phase error signal. This technique achieves a reverse clipping effect. Those skilled in the art will note that adjusting the amplitude of each current Ifix by an equal amount can affect the range of the phase error signal. In some implementations, increasing the amplitude of Ifix will reduce the amplitude range of the phase error signal, while decreasing the amplitude of Ifix will increase the amplitude range of the phase error signal. This relationship is as follows: Figure 13B As shown.

[0116] Figure 13B This is a timing diagram of the aforementioned reverse clipping characteristics. Figure 13B The figure shows the amplitude of current Ip under two Ifix2 values, A and B, within the first 180 degrees (1), where A > B. As shown, when Ifix2 = A, the amplitude of Ip is smaller. When Ifix2 = B, the amplitude range of Ip is relatively larger. Those skilled in the art will note that a similar effect can occur when the folded phase detector 1220 performs In discharge.

[0117] In some implementations, such as Figure 12A As shown, circuit balance feedback can be achieved using the back 180 degrees (4). In this circuit balance feedback phase (4), current can be charged via PMOS phase interpolator 510 and discharged via NMOS phase interpolator 515. If there is an imbalance between the charging / discharging currents, the circuit balance feedback signal will be non-zero, thus indicating this imbalance. The cause of this imbalance is, for example, a mismatch between transistors. This circuit balance feedback signal can then be used to adjust Ifix1 or Ifix2 to achieve a balance between the charging / discharging currents. Once balance is achieved, the balance feedback signal becomes zero. In some embodiments, the voltage of the charge pump circuit can be monitored. If they are equal, it indicates that the circuit has reached the correct balance state, i.e., Ip = In. Figure 12B for Figure 12A A simplified schematic diagram of a phase comparator circuit.

[0118] Alternatively, the phase detector described in Tajalli 4, as 520 or 1220, can be used to achieve the same high signal margin phase detection in embodiments employing low supply voltages. Furthermore, in this embodiment, alternatives may include... Figure 4A , Figure 4B and Figure 4C Other phase detectors 520 with all their variations are shown.

[0119] As an example of such an alternative implementation method Figure 4B The state machine phase / frequency detector shown can be used with Figure 5 This is combined with the phase interpolator design.

[0120] Figure 6A This is a schematic diagram of a traditional CML clock latch implementation. The latch consists of output Q and... The clocked feedback latches for the two results are configured such that the states of these two results are determined by the clocked differential inputs D and initialization. Figure 6B The circuit shown is the same, but it uses a phase interpolator 615 to adjust the phase of the clock source. The operating principle of this phase interpolator is explained above. Figure 5 The description.

[0121] When Figure 6B The clock latch circuit was replaced with Figure 4B Each D trigger instance is formed Figure 7A and Figure 7BThe alternative implementation is shown. The D flip-flop 710 is clocked by a received clock CkRef, which is transmitted via a phase interpolator 715. For example, and for illustrative purposes, if no phase difference is set (or when the desired phase difference is 0 degrees), the current source IA will be set to the "mixer" input CkRef at 100% ratio, while the other three current sources will be set to zero current. The D flip-flop 720 is clocked by a local clock CkPLL, which is obtained by setting the current sources IB(i), IB(-i), IB(q), and IB(-q) of the phase interpolator 725, which further controls the relative proportions and polarities of the combined I and Q clocks. In one implementation, as... Figure 3 As shown, I is derived from ph000, -I from ph180, Q from ph090, and -Q from ph270. Furthermore, the reset functions of flip-flops 710 and 720 are driven by a simple CML OR gate 730.

[0122] It should be noted that in this embodiment, most of the functions of the phase interpolator 715 are disabled. Its purpose is only to maintain the same parasitic load characteristics as the phase interpolator 725 in operation, so as to maximize circuit symmetry and minimize side effects such as detection bias and drift by maintaining balanced load characteristics.

[0123] Integrated phase detector, interpolator and charge pump

[0124] As mentioned above, the phase detector output of a PLL is typically used to drive a charge pump circuit, which outputs an analog error signal to control the VCO. The improvements in low capacitance and high circuit speed achieved by integrating the PLL phase detector with a clock-adjusting phase interpolator can be further extended by integrating the charge pump element in the same manner.

[0125] In this integrated implementation, Figure 7A and Figure 7B The charge pump control signals UPp, UPn, DOWNp, and DOWNn provided in the illustrated embodiment are... Figure 8 The generated I shown OUT The output charge pump is directly controlled. Current source I CPC and reference voltage V REF Configurable to I OUT The range can be scaled and adjusted. Those skilled in the art will note that... Figure 8 The circuit has very high symmetry, therefore it can be implemented at V REPLICA and I OUT Precise tracking is performed between the generation of signals.

[0126] Figure 8This is a schematic diagram of a charge pump circuit with improved charge / discharge current balance according to some embodiments. Circuit 800 includes two charge pumps 802 and 804 connected in parallel: two differential pairs within charge pump 804 generate an output current representing the phase error signal generated with rising and falling pulses; as described below, two differential pairs of charge pump 802 are used to set the discharge current equal to the charging current. Specifically, current source I... CPC The corresponding bias voltage V is provided by a current mirror circuit. BP In this manner, the charging current level is set to drive the top current sources 806 and 808 of the two charge pumps, thereby increasing I... CPC Similarly, this is provided to each charge pump 802, 804. When UPn decreases and causes the field-effect transistor (FET) 810 to turn on, node 812 is charged by the charging current I provided by the field-effect transistors 806, 810. CPC Charging (capacitive element 814 can be either a discrete cap or a parasitic cap). Under balanced conditions (i.e., no phase error), the amount of current discharged through the bottom-side field-effect transistor 816 when DOWNp is at a high signal level should restore node 812 to V. REF Value. If the discharge current is too low and the voltage V REPLICA Upgrade to V REF Therefore, amplifier 820 will increase the bias voltage V on discharge current field-effect transistor 818. BN To increase the amount of discharge current to match the charging current I CPC Equal, and make the voltage V on node 812 equal. REPLICA Restore to V REF On the other hand, if V BN If the discharge current set on the field-effect transistor 818 is too high, the voltage V will be affected. REPLICA The voltage will become too low, and amplifier 820 will then reduce the bias voltage V on discharge field-effect transistor 818. BN This restores the charge pump current to balance.

[0127] Second-order PLLs (also known as charge-pumped PLLs) are widely used to implement low-noise, high-performance synthesizers, clock generators, and clock data recovery systems. In these systems, a phase detector (PD) or phase frequency detector (PFD) generates a signal proportional to the phase difference between the reference clock (CkRef) and the feedback clock (CkPLL). The resulting error is integrated by the charge pump circuit (CPC) and the loop filter (LF) to generate a suitable control voltage for a voltage-controlled (sometimes current-controlled) oscillator (VCO). An example loop filter is as follows: Figure 24The RC circuit is shown. Many existing integrated VCOs employ a differential topology capable of providing two complementary outputs. Differential structures offer greater resistance to power supply noise and substrate noise. In high-speed communication systems, LC-tuned VCOs and ring oscillators are two widely used primary controlled oscillators. Both topologies can be used to provide two or more output phases, which is essential for multiphase systems and contributes to the functional improvements described below.

[0128] Other implementations can be obtained through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0129] Input reference signal oversampling

[0130] The reason is, for example, Figure 7A and 7B The reason for using the phase interpolator asymmetrically is that the local clock and the reference clock source are different in nature. The former is derived from a multiphase clock source (such as an oscillator or frequency divider), which itself can provide multiphase inputs for the phase interpolation element to use. The latter is a single-phase clock derived from the same (generally) receiving clock source.

[0131] In the prior art, *Tan* describes a combined DLL / PLL structure in which the PLL's VCO uses two identical voltage-controlled delay lines as input delay lines, which act on the reference clock input and are controlled by a single feedback error signal. *Ng* and *Chang* also describe using the front-end DLL as a frequency multiplier to generate extremely high-frequency clocks.

[0132] However, when tapping such a controlled delay line, if the controlled delay line is configured such that the differential delay between each tap point is proportional to the time between the edges of the received clock, the received clock passing through this delay line will produce a set of outputs with certain multiphase clock characteristics. As a non-limiting example, the equally spaced outputs of a four-tap delay line with a total delay similar to the reference clock period will produce outputs with characteristics similar to the quadrature phase-controlled clock signal. In this example, when each such output is compared with the correctly selected local clock phase, a more accurate total clock error signal can be generated for the PLL's VCO by combining the generated series of phase error results. The various delay forms of the received clock allow for additional phase comparisons of the clock from the VCO, thereby enabling a higher update rate for the controlled loop and increasing the loop bandwidth of the PLL. This reduces jitter and achieves better noise immunity. In other words, this technique increases the loop update rate, allowing the circuit to track and correct the effects of noise and jitter at higher frequencies.

[0133] In order for the aforementioned delay phase comparison to provide meaningful information to the PLL, the delay intervals provided by the delay lines must be coordinated with the time intervals between the local clock phases. This control method can provide the delay element with multiple functions of a delay-locked loop (DLL). Figure 9 As shown in the block diagram, the DLL 910 provides an external clock reference input to the PLL implementation 300 described above. After the received clock signal R5 is provided to the delay line 916 with a tap point, a series of received clock phases 918 are generated. The DLL control loop is provided by a phase comparator 912, which generates an error value by comparing the received clock with the delay clock. This error value is then low-pass filtered by a low-pass filter 915 to generate a delay adjustment signal for controlling the timing of the delay line.

[0134] Thus, in the PLL300, the above simple phase comparison ( Figure 3 The phase of the XOR gate (320) is implemented by a multi-phase comparator (920). In at least one embodiment, an XOR gate compares the phase of each received reference clock signal on N lines (N is, for example, equal to 2, 4, 8, etc., and may also include odd numbers to produce other phases such as 60, 120, 180, 240, 300, etc.) 918 with different clock phases among the N local clock signal phases on line 965 of the phase interpolator (360). Each XOR gate output represents a partial phase error signal that can be converted into an analog signal value, and as described above, by summing all such analog partial phase error signals with a summing circuit (935), a composite analog error result for controlling the ring oscillator (340) can be generated. In another embodiment, the summing 935 is implemented by a weighted summing node similar to the MIC mixer described above, where different weight values ​​selected in the summing enable further control over the static and dynamic operating characteristics of the PLL. Alternatively, the summing operation can also be implemented by driving a corresponding transistor circuit to inject or remove charge from a capacitive element with each XOR output. In another embodiment, each XOR phase comparator may include multiple AND operation elements implemented by transistor branches. Each AND operation element is used to provide a current output to a common summing node, and the magnitude of each current can be set independently, thereby enabling each AND operation element to have a weighting function. Furthermore, Figure 9 The PLL340 can be configured to provide the desired phase offset, wherein each inserted phase has the same offset relative to the tap delay line signal to which it is to be XOR compared.

[0135] In some system environments, such as when the communication protocol uses multiple clock signals, the multi-phase reference clock can be obtained directly from the receiver.

[0136] The additional feedback information provided by the aforementioned comparison operations can also be obtained without the aforementioned delay-locked loop front end. Figure 10 In the illustrated embodiment, a single received reference signal 1018 is input into a multi-phase comparator 920, wherein this single received reference signal is compared with each of two or more phases of a local clock signal 965. Consistent with the previous example, this multi-phase comparison operation differs from the operation described in *Nandwana* in that all local clock phases used for comparison have the same frequency and only phase differences exist. In one embodiment, an XOR gate compares the single received reference clock phase 918 with the clock phase 965 of the phase interpolator 360. The output value of each XOR gate is converted into an analog signal value, and as described above, all these analog signal values ​​are summed to generate a composite analog error result that controls the ring oscillator 340. In another embodiment, a weighted summing node, similar to the MIC mixer described above, performs a summing operation 935. By selecting different weight values ​​for this summing operation, further control over the static and dynamic operating characteristics of the PLL can be achieved. In another embodiment, each XOR phase comparator provides a current output to a common summing node, and the magnitude of each current can be set independently, thereby achieving the weighting function. Specifically, such weighting operations can be used to generate additional poles and / or zeros in the time-domain transfer function of the PLL, thereby enabling further control over loop stability.

[0137] Figure 14A Timing diagram comparing the reference signal CKREF with the four VCO phases (feedback from the PLL):

[0138] XOR(CKREF, VCO′000)

[0139] XOR(CKREF, VCO′045)

[0140] XOR(CKREF, VCO′090)

[0141] XOR(CKREF, VCO′135)

[0142] like Figure 14A As shown, it is assumed that all weight values ​​are equal. However, this assumption is purely illustrative and should not be construed as constituting a limitation in any way. Figure 14A This also includes summing the four XOR outputs. It can be seen that in the locked state, the integral of the bottom waveform is zero, therefore the PLL achieves correct locking. For convenience, Figure 14BA conventional phase detector based on XOR operation is also shown, in which the reference phase is compared with only one VCO phase. In the locked state, the reference phase is phase-shifted by 90 degrees with the VCO phase, and the output of this XOR operation is a rectangular waveform with a zero average value. Thus, the two waveforms ( Figure 14B Simple XOR operation and Figure 14A The difference lies in the array XOR operation, where, in both cases, the average value for a given time period is zero, and the PLL is locked. The implementation using an array phase detector involves more transitions than the case with a single XOR phase detector. Since each transition carries edge-related information, more transitions mean the phase comparator can acquire more information from the VCO and CKREF.

[0143] It is important to note that in array XOR implementations, some comparisons may need to be performed using XNOR. Therefore, system stability can be ensured by carefully selecting between XOR and XNOR for different phase comparisons.

[0144] In at least one embodiment, the weight values ​​used in the summation are set to decrease proportionally to the timing difference between the comparison clock phase and the PLL "normal lock" phase. As a non-limiting example, when the PLL's normal lock phase is ph090, the comparison weight between ph090 and the received reference signal is 1; the comparison weight between ph045 and ph135 ​​(e.g., offset by half a tap distance relative to the normal lock phase) is 1 / 2; the comparison weight between the received reference signal and ph000 and ph180 (e.g., offset by one tap distance relative to the normal lock phase) is 1 / 4; and so on. These different weighted comparison results are added to form a composite signal, which, after being low-pass filtered by 330, becomes the error value used to control the VCO 340 of the PLL.

[0145] In one embodiment employing multiple phase comparators, when equal phase detector weights are used, deterministic jitter is observed at a rate of 12.5 GHz. Although the amplitude of this jitter is extremely small and the jitter occurrence rate is much higher than the loop filter cutoff frequency, this deterministic jitter can still be significantly reduced by adjusting the aforementioned weight values. The weight values ​​decrease proportionally to their distance from the primary reference signal sample. In some embodiments, a discrete-time filter is constructed by using different weight values ​​in the comparator circuitry. This characteristic can be used to simplify the design of the analog filter 330. For example, when the weights used are correct, discrete zero values ​​can be constructed in the time-domain transfer function, thereby creating conditions for achieving loop robustness.

[0146] Consistent with the examples above, other implementations can be obtained through other equivalent combinations of phase comparators, phase interpolators, and charge pump elements.

[0147] Matrix phase comparison

[0148] In some implementations, the bandwidth of the PLL is limited by the loop's update rate, which in turn depends on the reference clock frequency. Of course, the efficiency of the correction loop can be significantly improved by utilizing all available information sources within the system. For example, each VCO phase provides an oscillator phase sample in each reference clock cycle, but when considering all VCO phases, additional information can be obtained from... Figure 14B More detailed information is obtained during the Tref time period shown. In existing PLLs, the VCO only feeds back one phase from its various phases to the phase detector. Therefore, the phase detector can obtain partial information related to the instantaneous phase of the oscillator. The following embodiments employ different loop update rate improvement methods implemented using a two-dimensional phase comparator.

[0149] An element that performs multi-phase comparisons on multiple phases originating from the received reference signal and multiple phases originating from the local PLL clock can be generally referred to as a matrix phase comparator. Figure 11B The diagram shows one implementation of a matrix phase comparator. Figure 11A The diagram illustrates one implementation of each individual phase comparator within this matrix phase comparator. For descriptive purposes, the diagram shows the XOR phase comparators arranged in a 4×4 matrix, but this does not imply any limitation on the invention. Embodiments of this application can form rectangular, square, or sparse matrices with arbitrary numbers of elements M and N in each dimension, where each element is composed of any of the phase comparators described in this application, and any weighting factor calculation method described in this application can be used. Because the local clock phase cycles repeatedly, therefore... Figure 11B As shown, the leftmost and rightmost columns of this matrix should be considered logically adjacent columns in terms of their local clock phase relationship. Figure 11B In this implementation, we assume CKPLL0 = 0°, CKPLL1 = 90°, CKPLL2 = 180°, and CKPLL3 = 270°. It should be noted that these numbers are for illustrative purposes only. Similarly, the fifth local oscillator clock CKPLL4 equals 360° and is in phase with CKPLL0. Therefore, according to the above implementation, the leftmost and rightmost columns should be considered as adjacent columns. In this application, a sparse matrix refers to any implementation where at least one of the above element weight values ​​is zero. In some implementations, one or more reference clock phases may be compared with one or more feedback clock phases. All other feedback clock phases (CkPLL...) NThese phase comparators are used to provide more detailed information related to phase noise in the VCO time domain. Therefore, such phase comparators are more likely to provide correction signals to the loop filter. In other words, multi-phase feedback systems allow the PLL to increase its update rate and correct VCO phase deviations at a higher rate. Similarly, a higher resolution phase comparison can be achieved when there are more available reference clock phases, and correspondingly, correction signals can be applied more promptly in more cases. If only one reference phase is available, the reference clock can still be replicated using controlled clustered delay lines (CDLs). To ensure that all replicated clock phases have similar jitter characteristics over the target frequency range, the delay line control loop needs to have extremely high or extremely low bandwidth. Figure 11B The diagram shows a typical two-dimensional phase comparator, in which any feedback signal phase can be compared with any reference clock phase.

[0150] In the full matrix comparison case, each of the M phases originating from the received reference signal is compared with each of the N phases originating from the local PLL clock. After weighting each obtained phase error signal by a preset or predetermined amount, all (M×N) weighted results are summed to generate a composite phase error signal. Figure 11A The figure shows an embodiment of a partial phase comparator 1110, which consists of an XOR phase detector 1112 and a result weighting factor unit 1118 that receives its output. As shown, each partial phase comparator 1110 receives CKRef(m) and CkPLL(n) and may have a corresponding weighting factor W(m, n), where 0 ≤ m < M-1 and 0 ≤ n < N-1. Figure 11B The diagram illustrates one embodiment of a full-matrix phase comparator 1120, which comprises M×N partial phase comparators 1110. Each partial phase comparator 1110 receives one of M reference phases (referred to in this application as CkRef0, CkRef1, CkRef2, CkRef3) and one of N local phase inputs (referred to in this application as CkPLL0, CkPLL1, CkPLL2, CkPLL3), and generates a weighted result. For example, the multiple weighted results 1131, 1132, 1133, 1134 thus obtained serve as input values ​​to a summing circuit 935 for generating a composite phase error signal 1145.

[0151] Those skilled in the art will recognize that Figure 9The multi-phase comparator 920 shown above is equivalent to the matrix comparator of this invention containing only a subset of matrix elements (i.e., comparator elements on the matrix diagonal). Functionally, by setting the weight values ​​on the entire matrix diagonal to non-zero values ​​and setting all other comparator weight values ​​to zero, the exact same result can be obtained. Similarly, by selectively setting the matrix weighting factors, other desired functions, including the simulation of phase differences and the introduction of loop time-domain zeros, can be obtained in a similar manner. In this implementation, each reference clock phase is compared with its corresponding feedback clock phase, i.e., CkRefm is compared with CkPLLn. The dynamic characteristics of the diagonal comparator are similar to those of a conventional PLL (CPLL), except that its update rate is N times that of the latter. The higher loop update rate enables the diagonal PLL to track input jitter and correct VCO jitter at high frequencies. In summary, the signal (reference) transmission characteristic (STF) and VCO noise (jitter) transmission characteristic (NTF or JTF) of such a system are N times that of a conventional PLL.

[0152] In at least one embodiment, Figure 11B A matrix comparator can be simplified to comparing different phases of the feedback signal (CkPLL) with only one reference clock phase. This type of implementation is particularly noteworthy because generally only one reference clock phase exists. In this implementation, W(m, n) is zero unless m = 0.

[0153] Assuming the above configuration is a four-phase feedback configuration, the correction signal generated by each phase comparator will eventually accumulate on the capacitor of the loop filter. Although Figure 14A The bottom waveform shows that the integral of the correction signal in the locked state is zero, but the main harmonic frequency of this signal is 2f. ref .for Figure 14A As shown in the bottom waveform, any jitter in the reference clock or feedback divider phase will cause a certain degree of deviation at its different edges. Figure 14A The bottom waveform shows the waveform after the correction signal is injected into the loop filter. When... Figure 14A Bottom waveform and Figure 15 Compared to the waveform of a single XOR phase comparator, it is evident that the number of transitions in the comparator output signal during a single reference clock cycle has more than doubled. Although the rise and fall edges of CkRef both produce two transitions in the two waveforms above, the number of transitions due to the feedback signal is significantly higher. Figure 15 Two of them have been increased to Figure 14A (also shown in) Figure 16The eight in ) Based on this, the feedback transfer function of the multi-phase diagonal phase detector differs from that of a conventional phase detector. In the above case, since the feedback path can provide more samples, VCO noise correction can be achieved in more cases and over a wider frequency bandwidth.

[0154] As described above, the multi-phase comparator (i.e., array phase comparator) has opened a new window for the design of low-noise broadband PLLs. The following examples illustrate the performance improvements achieved by the array phase comparator in PLLs.

[0155] In some implementations, the array phase comparator provides dual-edge phase comparison functionality: simultaneously utilizing both edges of the reference clock (rising and falling edges), thus creating the possibility of performing two independent phase corrections within each cycle. This makes it possible to double the bandwidth of the PLL. When the duty cycle of the input reference signal is not 50%, it will be at 2f ref The ripple frequency generates a certain amount of ripple and can increase the deterministic jitter (DJ) of the oscillator. In fact, because the ripple frequency is relatively high, most of the deterministic jitter can be eliminated when the loop filter is designed properly.

[0156] In some implementations, the array phase comparator provides VCO phase comparison functionality. To detect and correct duty cycle and quadrature mismatch (QME) errors, designers typically need to compare different phases of the VCO. In such corrections, the error signals generated by the VCO phase comparisons must be rigorously filtered, and duty cycle distortion or quadrature mismatch is corrected by applying a very low-frequency correction signal at an appropriate location within the system. Furthermore, the above implementations can also be extended to detect and correct VCO random jitter.

[0157] Some implementations of the two-dimensional discrete-time phase comparator create the possibility of implementing a discrete-time filter upstream of the PLL. This possibility can be used to implement a special transfer function that can improve system performance. For example, by correctly selecting the digital filter coefficients (such as the weight values ​​mentioned above), phase noise can be detected and suppressed at specific frequencies, thereby improving the power supply or substrate noise of the system. Some implementations provide phase interpolation functionality: various methods are now available to rotate the phase of the PLL oscillator according to system requirements and precisely adjust the clock recovery time. In some implementations, a diagonal comparator array structure can provide the possibility of rotating the oscillator phase relative to a reference clock phase.

[0158] For a given reference clock CkRefm and a given local oscillator phase CkPLLn, assume W(m,n) = a under condition (mn) = 0, W(m,n) = b under condition |mn| = 1, and W(m,n) = 0 for other m and n conditions (note that due to the above cyclic property, n must be considered as the result modulo the local oscillator phase number). Assume a + b = c and c has a fixed value. In this case, the VCO phase can be rotated by adjusting a and b = ca. If the locking points corresponding to [a,b] = [c, 0] and [a,b] = [0, c] are Ta and Tb respectively, then as follows... Figure 17 As shown, by adjusting a (equivalent to adjusting b=ca in the reverse direction), the lock point of the oscillator can be moved between Ta and Tb.

[0159] The above argument holds for any other consecutive combinations of |mn|=k and |mn|=k+1, where k is an integer smaller than the scale of the phase comparator matrix. Assume a and b are the weights of two consecutive diagonal comparators k and k+1. If a and b are composed of two independent sets of N... b If each bit is controlled digitally, the resulting phase interpolator can have N... b +1 bit resolution. From Figure 18 It can be seen that by making appropriate adjustments between n(a) and n(b) (which are the control bits corresponding to a and b, respectively), additional phase points can be added between any two phase steps of the original phase interpolator.

[0160] The following is an example of diagonal interpolation, where each element of the main diagonal is assigned a weight value 'a', and each element of the adjacent diagonal is assigned a weight value 'b':

[0161] The following is an example of diagonal interpolation, where each element of the main diagonal is assigned a weight value 'a', and each element of the adjacent diagonal is assigned a weight value 'b':

[0162]

[0163] It's important to note that due to the cyclical nature of adjacent columns, the bottom-left element of the matrix is ​​assigned a weight value of 'b'. This ensures that the number of elements with weight values ​​'a' and 'b' is always equal, thus achieving the desired result. Figure 17 The linear symmetric phase relationship is shown. Another example of two adjacent diagonals exhibiting cyclic properties is given below:

[0164]

[0165] In an alternative implementation, interpolation is performed between adjacent rows or columns of the weighting matrix. This concept is very similar to the diagonal implementation described above, where the first column can have a first fixed phase difference, and the second column can have a second fixed phase difference. As mentioned above, each element in the first column can be assigned a weight value 'a', and each element in the second column can be assigned a weight value 'b', where a + b = c. Furthermore, it should be noted that due to the cyclical nature of the local oscillator clock, the leftmost and rightmost columns should be considered adjacent columns. Therefore, by interpolating weight values ​​'a' and 'b' in each column, an intermediate phase can be provided between the first and second fixed phases.

[0166] In an alternative implementation, interpolation can be performed between adjacent rows or columns of the matrix. This concept is very similar to the diagonal implementation described above, where the first column can have a first fixed phase difference, and the second column can have a second fixed phase difference. As mentioned above, each element in the first column can be assigned a weight value 'a', and each element in the second column can be assigned a weight value 'b', where a + b = c. Furthermore, it should be noted that due to the cyclical nature of the local oscillator clock, the leftmost and rightmost columns should be considered adjacent columns. Therefore, by inserting weight values ​​'a' and 'b' into each column, an intermediate phase can be provided between the first and second fixed phases.

[0167] Phase comparator architecture

[0168] The flexibility and structural simplicity of a matrix comparator may be affected by the complexity of its implementation in terms of both the number of comparators used to fill a matrix of M×N elements and the implementation of the weighting or scaling factor required for each element.

[0169] As a non-limiting example, a PLL that performs a matrix comparison of each of the eight VCO clock phases with a single reference clock input includes: eight comparator matrix elements, each associated with a configurable or adjustable scaling factor; and a summing node for generating the combined error result. Figure 19A In one such embodiment shown, each phase comparator 1110 employs a multiplicative digital-to-analog converter structure to implement the same weighting factor as 1118. In some embodiments, the weighting signal may selectively activate one or more switching elements, such as transistor switches and current sources. Thus, the more switching elements activated, the greater the weight value applied to the partial phase error signal.

[0170] Because the distributed capacitance of the digital-to-analog converter structure within the signal path may excessively degrade signal integrity, in an alternative embodiment, the digital-to-analog converter structure is not included in the signal path. In this second embodiment, the digital-to-analog converter element 1116 is used to... Figure 19BThe supply voltage of the digital buffer element 1115 shown is scaled or adjusted to generate a scaled or weighted signal output.

[0171] The use of resistive digital-to-analog converters may be incompatible with circuit applications requiring low-power operation; therefore, another implementation employs switched capacitor technology. Figure 19C In the third embodiment shown, a scaled or regulated supply voltage is dynamically generated for the buffer 1115 by transferring the measured charge from one or more source capacitors C1 to the power rail capacitor C2 of the buffer. In this illustrative example, as shown, the charge transfer function is implemented by switch SW1. As is well known in the art, in practical embodiments, a switching transistor may be used, and one or both of C1 and C2 may be composed of discrete capacitors and parasitic or distributed capacitors.

[0172] As an alternative, Figure 19D The fourth embodiment shown does not attempt to adjust or modify the signal output of a single phase comparator. Instead, it generates partial phase error signals through a set of parallel phase comparators 1113, which, when combined, produce a composite phase error signal. In one such embodiment, the output drive capability of a single phase comparator 1113 is limited, for example, by the size of its output driver transistor. As an example, the composite phase error signal can be generated by passively summing the individual partial phase error signals, and the weighting or control of the total output amplitude can be achieved by enabling or disabling the phase comparators within the set individually (e.g., under thermometer code control) or in groups (e.g., under binary weighted code control).

[0173] During high-speed simulation of the fourth implementation, it was discovered that the logic gate propagation time of the XOR phase detection element experiences transient output fluctuations, meaning fluctuations more subtle than the overall characteristics of the entire XOR gate. It should be noted that the XOR function can be performed according to the well-known Boolean equations. The logic gates were decomposed into independent NOT, AND, and OR logic components, and observations showed that the aforementioned fluctuations originated from deviations between different current paths in the logic gate implementation. Correspondingly, Figure 20 In one implementation, transistors are arranged in series and used to calculate logic quantities separately. The x·y transistor branches form four signal paths 2010, 2020, 2030, and 2040. Each path also includes an adjustable or settable impedance, which is implemented by a resistor or a current supply / suction device, or in some embodiments by transistor geometry scaling operations for constraining the current within the corresponding signal path. Figure 21The timing diagram of the output signal Iout generated by input signals X and Y.

[0174] Adjusting the impedance of the four signal paths, achieved by introducing path impedance, scaling transistor size, or directly adjusting the current, can be used to control the overall output amplitude of the XOR gate, thereby achieving the desired weighting function. For example, when considering... Figure 20 When the impedance of each signal path is composed of four parallel resistors (each controlled by a transistor switch), the weighted signal can use a portion of a four-bit thermometer code t0-t3 (a non-limiting example) to achieve four different current levels within signal path 1920 (e.g., ...). Figure 21 As shown), this adjusts a segment of the total output Iout. Similarly, in this example, t4-t7 adjusts signal segment 2120, and t8-t... 11 Adjust signal segment 2130, t 12 -t 15 Adjust signal segment 2140. Although the weight values ​​of the four signal segments are adjusted in exactly the same way in some embodiments, this is not necessarily required. For example, as described above for... Figure 5 In order to improve the overall adjustment resolution, t0-t3 and t4-t7 can be set to be the same as t8-t 11 and t 12 -t 15 Different values. As another example, t0-t3 and t8-t... 11 It can be set to be the same as t4-t7 and t 12 -t 15 Different values ​​are used to intentionally introduce a DC offset into the output.

[0175] Independent adjustment of the four segments for each XOR operation also facilitates various operations of the aforementioned matrix comparator, including interpolation. For example, as described above, two such... Figure 20 The XOR comparator shown, with its output connected to a common summing node, can be used to compare the reference clock with the phases of two local clocks. When interpolation control values ​​a, b, c, d are applied to the first XOR operation segment (t0-t3, t4-t7, t8-t...),... 11 , t 12 -t 15 When the weighted signals of the first and second local clock phase comparisons are represented by 1-a, 1-b, 1-c, and 1-d respectively, the results of the summing nodes correspond to the interpolation operation between the first and second local clock phase comparison results, wherein the above interpolation control value can realize the adjustment of the effective clock phase.

[0176] Alternatively, scaling transistors or explicit supply / sink circuits can be used to replace resistors for current control. Consistent with embodiments using resistors, the total output Iout can be adjusted by enabling and disabling different numbers of parallel current paths. The various portions of the aforementioned weighted signals together form the weighted signals t0-t of the corresponding partial phase comparators. 15 .

[0177] The adjustable or configurable components described in this application may be combined with or equivalent to similar prior art components, including but not limited to R-2R ladder structures controlled by transistor switches, resistor chain structures controlled by transistor switches, equal-weighted or binary-weighted resistors constructed in series or parallel and controlled by transistor switches, and fixed and / or configurable current sources and sinking devices.

[0178] The specific values ​​and quantities given in each example are for illustrative purposes and do not imply limitation.

[0179] simulation

[0180] Figure 22 The steady-state responses of two different similar phase comparators are shown. In both simulations, XOR-based phase comparator units were used. The gain of the diagonal phase comparator changes with the input phase difference similarly to that of the single XOR phase comparator. The main difference between the two phase comparators is that the error signal generated by the diagonal phase comparator is a time-distributed signal. However, the response of the matrix row phase comparator is different. It can be seen that the time offset of the response curve varies depending on the row of the matrix comparator selected. Figure 22 The figures show the response curves for two different scenarios.

[0181] In an MCPLL (Matrix Phase Comparator-based CPLL) designed using existing 28nm CMOS technology, the VCO is selected as K. VCO A current-guided architecture of approximately 20 GHz / V is used, employing R1 = 100 Ω in parallel with C1 = 20 pF and ICPC = 100 μA. Figure 24 The loop filter is shown. The reference clock frequency is 6.25 GHz and N... div =1. The XOR CPLL is based on a 2R×2F architecture (comparing two reference phases with two feedback phases in each reference clock cycle), while the MCPLL uses a 2R×4F architecture.

[0182] Figure 23 The diagram shows the transmission characteristics of two PLLs simulated at the transistor level. As shown, since the input signal sampling frequency is 2fref, the Nyquist rate of this system is fref. For this reason, as... Figure 22 As shown, both PLLs exhibit no signal at fref = 6.25 GHz. For both PLLs, parasitic poles of the VCO and CPC output cause peak values ​​of 1.2 dB and 2.4 dB for the CPLL and MPLL, respectively. It can also be observed that the MCPLL's transfer characteristic curve approaches 0 dB in the 100 MHz to 1.2 GHz range. The cutoff frequencies of the two PLLs are 2.48 GHz (40% of fref) and 5.02 GHz (80% of fref), respectively. Therefore, they offer better jitter tracking performance. Furthermore, the MCPLL generates an RMS jitter of 55 femtoseconds, while the CPLL generates an RMS jitter of 79 femtoseconds. Due to its higher bandwidth, the MCPLL's VCO can perform phase noise filtering over a wider range. For this reason, this architecture can significantly reduce the generated jitter, achieving performance similar to that based on a low-voltage VCO.

[0183] Data-driven phase comparator

[0184] In some implementations, the matrix phase comparator architecture described above can be used to extract clock signals from transitions occurring within multiple data sub-channels, for example, from transitions within sub-channels of a vector signaling code transmitted via a multi-line bus. In such implementations, the vector signaling code suitable for the above combination is a vector signaling code capable of ensuring transition density relative to time, such as the vector signaling code described in Shokrollahi 1. Figure 25 The image shows a receiver that uses a data-driven phase comparator. The receiver monitors the transitions of the data signals received in parallel from MIC0 to MIC4 to provide clock phase information for the clock recovery circuit 2600, thereby enabling phase control of the sampling clocks ph000, ph090, ph180, and ph270. Figure 26 A more detailed view of the clock recovery circuit 2600 employing a matrix phase comparator 2610.

[0185] When considering a system that monitors multiple data inputs, several operational considerations readily become apparent. First, since any data bit received within successive unit intervals can remain in a "1" or "0" state, only data transitions between these states are related to the PLL phase. Specifically, between any two successive unit intervals, a transition may or may not occur within any given data bit. In fact, any data bit may not transition within a given clock interval. If a transition occurs, the matrix phase comparator can update the PLL clock phase using the moment the transition occurs. However, if no transition occurs, the PLL clock can remain unchanged. If two or more data lines experience transitions within the same clock interval, the timing errors of all these transitions can be summed according to the characteristics of the matrix phase comparator described above.

[0186] The aforementioned characteristics indicate that a state machine phase detector is a suitable candidate for the phase comparison element within the comparison matrix because such a design can be configured to respond only to signal transitions and not to signal levels, and can also be configured to output a "no change" result when no signal transition occurs. In some embodiments, the partial phase comparator 2712 may take the form of an edge-triggered binary (Bang-Bang) detector for generating a partial phase error signal when a transition is determined to have occurred. Figure 29 The diagram illustrates an example of an edge-triggered binary (Bang-Bang) phase detector. In some embodiments, the partial phase comparator may take the form of a linear edge-triggered phase detector used to generate a partial phase error signal when a transition is determined to have occurred. Figure 31 As shown Figure 30 The block diagram and corresponding waveform of the linear edge-triggered phase detector are shown.

[0187] Another implementation may employ a data signal transition detector, one example of which includes an XOR gate that compares the data signal with a form that is slightly delayed, for example, by passing through a logic buffer gate. Such implementations output a logic pulse at each transition, and the edge of the pulse can be compared with the PLL clock edge using any of the aforementioned phase detectors. In an improved implementation, gating or time-windowing in some phase detectors can also be used to ensure that any partial phase detector that does not receive a data signal transition within a given time interval generates a "no change" error result.

[0188] Figure 26 The diagram shows one implementation of the multi-line clock recovery circuit 2600. MIC0 to MIC4 are the detected clock signals... Figure 2The example uses a vector signaling code subchannel (i.e., the decoded data bits) with similar code. Any transition in the detected vector signaling code subchannel generates a partial phase error signal relative to one or more local clock phases, each of which (in this example) is a rising, falling, or constant analog signal. The summation 2650 of all partial phase error signals is processed by a low-pass filter 2660, and the result is used to adjust the frequency of the VCO 2670. In some implementations, if the transmission medium has a large difference in the propagation speed for different propagation modes, eye diagram closure may occur in the subchannels, resulting in time offsets between the subchannels. To compensate for such time offsets between subchannels, the phase interpolator 2690 can be configured to independently adjust the phase of each local oscillator signal according to the corresponding data signal, thereby correcting for such subchannel-specific time offsets. Alternatively, subchannel-specific time offset compensation can also be achieved by introducing a subchannel-specific delay with an analog delay element (not shown).

[0189] Figure 27 The diagram shows another embodiment of the matrix phase detector 2610, which comprises a matrix of phase component detectors 2710. As a non-limiting embodiment, consistent with Tajalli 4, each phase detector 2710 further includes an edge-sensitive state machine phase detector, a charge pump, and a configurable weighting function. Thus, the matrix phase detector 2610 compares each of the detected data signals MIC0 to MIC4 with the four phases ph0, ph090, ph180, and ph270 of the local PLL clock, and then weights 2715 the phase comparison results generated by each comparison 2712. In one specific embodiment, the resulting weighted result is an analog current, and therefore, at the current summing node 2650, all these results 2720, 2730, 2740, 2750, and 2760 can be interconnected and summed to directly generate a composite phase error signal 2655. It will be readily understood by those skilled in the art that similar results can also be generated through explicit voltage summation, numerical calculation, etc., and there are no specific limitations in this regard. In some embodiments, some phase comparators 2710 may further selectively output corresponding partial phase error signals by receiving a Transition_EN enable signal (not shown). In some embodiments, the corresponding Transition_EN(m) signal received by each partial phase comparator 2710 is associated with the corresponding detected data signal received by that partial phase comparator 2710. For example, MIC0 may have an associated enable signal Transition_EN0; MIC1 may have an associated enable signal Transition_EN1; and so on.

[0190] The weight values ​​of each matrix comparison element 2710 of the matrix phase comparator 2610 can be set either uniformly (i.e., any data signal transition has an equal impact on all clock phases) or non-uniformly to minimize the impact on specific clock phases. As described in Tajalli 4, by selectively configuring the matrix weighting factors, other effects, including phase difference simulation and the introduction of loop time-domain zeros, can also be obtained.

[0191] Figure 26 The diagram shows one implementation of the multi-line clock recovery circuit 2600. MIC0 to MIC4 are the detected clock signals... Figure 2 The code used in the example is a similar vector signaling codesubchannel (i.e., the detected data signal or decoded data bits after slicing and sampling). Any transition in the detected vector signaling codesubchannel generates a partial phase error signal relative to one or more local clock phases, each of which (in this example) is a rising, falling, or constant analog signal. The sum of all partial phase errors 2650 is processed by a low-pass filter 2660, and the result is used to adjust the frequency of the VCO 2670.

[0192] Figure 28 The following is a flowchart of method 2800 according to some embodiments. As shown, method 2800 includes: receiving 2802 a plurality of data signals in parallel from a plurality of multiple multi-input comparators (MICs) connected to a multi-line bus by a data-driven phase comparison circuit, and receiving one or more phases of a local oscillator signal, wherein at least one MIC is connected to at least three lines of the multi-line bus, the data-driven phase comparison circuit including a plurality of partial phase comparators; generating 2804 a plurality of partial phase error signals using the partial phase comparators, each partial phase error signal being generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal from the plurality of data signals and, when it is determined that a transition has occurred in the corresponding data signal, based on a comparison result between the corresponding phase of the local oscillator signal and the corresponding data signal; and generating 2806 a composite phase error signal by summing the plurality of partial phase error signals, the composite phase error signal being used to lock the local oscillator that generated one or more phases of the local oscillator signal.

[0193] In some embodiments, the partial phase error signal is an analog signal generated by a corresponding charge pump circuit. In such embodiments, the method further includes filtering the composite phase error signal.

[0194] In some implementations, the method further includes: for a given partial phase comparator, introducing a sub-channel targeted delay to a corresponding phase of the local oscillator signal, the sub-channel targeted delay being associated with the data signal received by the given partial phase comparator.

[0195] In some implementations, the comparison result between the corresponding phase of the local oscillator signal and the corresponding data signal is formed by a linear edge-triggered phase detector. Alternatively, the comparison result between the corresponding phase of the local oscillator signal and the corresponding data signal may be formed by an edge-triggered binary (Bang-Bang) phase detector.

[0196] In some embodiments, the method further includes applying a weight value to the partial phase error signal. In some embodiments, the overall transition density of the plurality of data signals is higher than a preset threshold. In some embodiments, the method further includes outputting a no-change result when it is determined that no transition has occurred. In such embodiments, outputting the no-change result includes setting the partial phase comparator to a high-impedance state.

[0197] PLL startup

[0198] In many communication environments, the minimum transition density of data signals may be low, necessitating that the aforementioned PLL oscillator remain unchanged in frequency over a relatively long operating time. As mentioned above, consistent with the selection of oscillators with good stability, choosing a phase detector design capable of generating a "no-change" output when no data transitions occur helps to meet this requirement.

[0199] However, the startup scenario differs significantly from the above. Because the VCO's initial oscillation frequency may be much higher or lower than its target operating frequency, the received transition density in the data line can be extremely high, especially when the startup phase requires the transmission of training modes or other special data sequences as part of a CTLE conditioning or other receiver calibration process. Therefore, the PLL may take a long time to lock in, or the VCO may operate at an incorrect frequency.

[0200] Tajalli 3 describes a PLL initialization "frequency lock-in assist" structure consisting of an additional phase / frequency detector. This structure forces the PLL into normal operating mode by overcoming spurious frequency offsets, and is then replaced by a normal phase comparator.

[0201] Multi-mode data-driven clock recovery circuit

[0202] In some implementations, a data-driven clock recovery circuit can be used to operate in a variety of modes, including conventional modes. Figure 32 The diagram illustrates an exemplary multi-mode data-driven clock recovery circuit according to some embodiments. As shown, this multi-mode data-driven clock recovery circuit includes multiple sub-channels 3202a / 3202b / 3202c, which can employ, for example... Figure 33 The sub-channel MIC shown is in form and can have the same characteristics as... Figure 25 A similar multi-phase receiver configuration. Furthermore, each sub-channel may include a data-driven phase detection (PD) element for generating a corresponding data-driven phase error signal indicating whether the sampling clock is too early or too late relative to the sampling clock provided by the local oscillator 3210 and / or 3215. Specifically, such a data-driven phase detector may be implemented as follows: Figure 34 As shown, the MIC output is measured by two different slicing elements 3420. It is important to note that each slicer uses an offset voltage based on the predicted DFE, with one slicer using a positive predicted DFE correction value +H1 and the other using a negative predicted DFE correction value -H1. These two values ​​are applied through the connection lines used for DFE compensation. Thus, one of the predicted DFE correction values ​​is associated with a predicted (or "unexpanded") DFE correction value assuming the previous data bit is "1", and the other predicted DFE correction value is associated with a predicted (or "unexpanded") DFE correction value assuming the previous data bit is "0". In such embodiments, once the DFE unit 3450 makes a data determination for the previous bit transmitted in the corresponding sub-channel, this determination can be used to select the output of one slicer as a valid data signal on which appropriate DFE compensation has been implemented (via multiplexer 3430), while the output of another slicer (with the opposite amplitude offset direction) can provide useful early / late judgment information, which is selected by multiplexer 3460 as the early / late detection result. In some embodiments, the transitions occurring in the sub-channel output are verified by mode detection circuit 3480 to confirm that the early / late indication information is valid information and can therefore be used to form a valid data-driven phase error signal. Charge pump circuit 3205 can receive the early / late indication information and provide a data-driven phase error signal. Subsequently, the data-driven phase error signals are combined to form a composite phase error signal and provided to local oscillator 3210, which may include a loop filter illustrated as a series resistor and capacitor. It should be noted that in Figure 32 In the illustrated embodiment, since the local oscillator control signal is generated in the analog signal domain, the loop bandwidth it provides is typically higher than that achievable by loop control based solely on error filtering and integration / accumulation.

[0203] In the first operating mode, the circuit can use all three sub-channel outputs generated by sub-channels 3202a / 3202b / 3202c. Although the number of sub-channels is shown as three in the figure, this is for illustrative purposes only and is not intended to be a limitation; higher-order orthogonal integrated non-return-to-zero (ENRZ) signaling methods can also be used. In some embodiments, each sub-channel device 3202a / 3202b / 3202c may include not only a microphone but also sampling circuitry. Figure 33 The diagram shows an example construction of a MIC network consisting of three MICs according to some implementation methods. Figure 33 The illustrated MIC network can be used for the ENRZ encoding scheme. As shown, the three MICs are connected to a multi-line bus with four lines w0 to w3. The output of each MIC represents a linear combination of code characters received in the form of signals from the four lines. Each MIC can perform linear combination based on the input permutation of the lines connected to it, wherein each input permutation is determined by the corresponding matrix row among multiple mutually orthogonal matrix rows. Figure 33 The diagram shows three different line input permutations that can be determined by a 4-dimensional Hadamard (H4) matrix. To achieve clock recovery, data signal transitions generate corresponding data-driven phase error signals by comparing the phase of the sampled clock provided by the local oscillator 3210 with the phase of the sampled clock via a phase detector. These data-driven phase error signals are generated by individual charge pump circuits 3205 acting on early / late indication information associated with the sub-channel undergoing the transition. These data-driven phase error signals are summed to generate a composite phase error signal, which is then provided to the local oscillator 3210 to adjust the phase / frequency of the sampled clock generated by the local oscillator 3210. Figure 32 As shown and as described above, the circuit may further include a sub-channel-specific delay element 3225 for compensating for sub-channel-specific time offsets. Furthermore, when no data transition occurs in one or more sub-channels, the output of the corresponding charge pump may output information indicating "no change" by, for example, being set to a high-impedance state by the mode detection circuit 3480 or by other means.

[0204] In conventional operation mode, sub-channel MIC 3202b can be turned off or otherwise disabled, while the circuit can operate in non-return-to-zero (NRZ) operation mode, in which each of sub-channel MICs 3202a and 3202c is used to receive a corresponding differential data signal via a pair of corresponding lines of the four-line bus and generate a corresponding NRZ output accordingly. In this implementation, sub-channel MIC 3202a can be connected to lines w0 / w1 and disconnected from lines w2 / w3. Similarly, sub-channel MIC 3202c can be connected to lines w2 / w3 and disconnected from lines w0 / w1. The NRZ output of sub-channel MIC 3202c can be used to generate a phase error signal, which is used to regulate a second local oscillator 3215 via the rightmost charge pump circuit. This second local oscillator may have a frequency and / or phase relationship independent of local oscillator 3210. Selection circuit 3220c (e.g., a multiplexer) generates early / late indication information associated with sub-channel 3202c by directing the sampling clock generated by local oscillator 3215 to a sampler within sub-channel MIC 3202c. Selection circuits 3220a and 3220b are illustrated for the purpose of depicting a scenario where a symmetrical load effect is applied to each sub-channel MIC. In other embodiments, since sub-channels 3202a and 3202b are connected only to local oscillator 3210 in most preferred embodiments (e.g., ...), ... Figure 32 As shown), selection circuits 3220a and 3220b can therefore be omitted. In some embodiments, selection circuits 3220a and 3220b are included for load application purposes and to keep the circuitry of each sub-channel MIC consistent. In such embodiments, selection circuits 3220a and 3220b connected to the local oscillator 3215 can be multiplexers with their selection inputs connected to VDD or ground. It should be noted that the sub-channel combination in NRZ mode can vary, and Figure 32 The configuration shown is only one possible configuration. In some embodiments, similar operations can be implemented with a different number of sub-channels than described above, for example in... Figure 25 In the embodiment shown and described in detail below, five sub-channel MICs are used, which are connected to a multi-line bus containing six lines.

[0205] In some implementations, the operating mode of the multi-mode clock recovery circuit is set to Orthogonal Differential Vector Signaling (ODVS) mode (such as ENRZ mode) or NRZ mode by a mode controller. The mode controller may include protocol processing hardware for interpreting protocol messages received via a setup bus and for enabling sub-channel MICs to detect ODVS or NRZ mode signals. Such mode signals may take the form of setup parameters contained within messages received as part of a bus negotiation sequence. For example, in ENRZ ODVS mode, the mode controller connects the multiple sub-channel MIC devices to the multi-line bus according to the corresponding line input permutation in a plurality of line input permutation combinations and activates a charge pump associated with local oscillator 3210. Furthermore, the mode controller may, as needed, provide the sampling clock signal output from local oscillator 3210 to multiple samplers associated with the sub-channel MIC devices (in some implementations, only 3220c is signal-connected to the mode controller). Finally, the mode controller may apply a sub-channel-specific delay setting via adjustable sub-channel-specific delay element 3225.

[0206] In NRZ mode, the mode controller enables the plurality of MICs to generate first and second NRZ output values ​​by disabling input values ​​from unused lines of sub-channels MICs 3202a and 3202c (and completely disabling MIC 3202b). It also enables the leftmost charge pump to provide a first local oscillator control signal to the first local oscillator generating the first sampling clock 3210, and the rightmost charge pump to provide a second local oscillator control signal to the second local oscillator 3215 generating the second sampling clock, thereby allowing the two local oscillators 3210 and 3215 to operate independently based on the local oscillator control signals from 3202a and 3202c, respectively. In some embodiments, the mode controller may connect the first and second MICs to corresponding line pairs in adjacent line pairs to, for example, reduce crosstalk effects between adjacent lines.

[0207] In another embodiment, a configurable sub-channel-specific delay element can be introduced between the receiver clock system 3470 and the sampler 3420 of each sub-channel to achieve progressive correction of timing differences between the plurality of sub-channels. Taking the above three-sub-channel system as a non-limiting example, it can be seen that since the signal received from the transition of sub-channel 2 is later than the signals received from sub-channels 1 and 3, the early / late indication information of sub-channel 2 indicates that the clock is "too early," while sub-channels 1 and 3 are not actually like this. The reason for this phenomenon may be the common-mode signal propagation fluctuation within the four lines of the multi-line bus. To address this phenomenon, a small delay can be introduced into the delay element associated with sub-channel 2, thereby shifting its sampling time backward relative to the overall clock time. In at least one embodiment, the clock source can be selected for each sub-channel sampler associated with auxiliary functions such as data and clock edge detection and statistical eye diagram data collection and calibration. In one such implementation, the selection of clock sources includes at least an unmodified clock provided by the receiver clock system and an asymptotically delayed clock provided by a configurable delay element, and may also include an independently adjustable clock for statistical eye diagram sampling.

[0208] Figure 36 The following is a flowchart of method 3600 according to some embodiments. As shown, method 3600 includes: configuring at least one local oscillator among a plurality of local oscillators with a corresponding local oscillator control signal formed according to the outputs of a plurality of MICs connected to a plurality of lines of a multi-line bus. The plurality of MICs are selectively configured 3604 to: (i) in a first mode, generate a plurality of quadrature sub-channel outputs by having at least one MIC compare a group of signals consisting of at least three signals received via corresponding lines of the multi-line bus; and (ii) in a second mode, generate a group of non-return-to-zero (NRZ) outputs by having subgroups of the plurality of MICs compare signals received via corresponding pairs of lines of the multi-line bus. In the first mode, a plurality of data-driven phase error signals are generated based on the plurality of quadrature sub-channel outputs, and a composite phase error signal is formed by combining the plurality of data-driven phase error signals 3606, which is provided to the local oscillator among the plurality of local oscillators. In the second mode, a corresponding local oscillator control signal 3608 is generated for each NRZ output in the set of NRZ outputs, and each of the corresponding local oscillator control signals is provided to the corresponding local oscillator among the plurality of local oscillators in response.

[0209] In some embodiments, the method further includes disabling one of the plurality of MICs in the second mode. In some embodiments, the respective pairs of lines of the multi-line bus include adjacent lines in the second mode, for example, w0, w1 of a first pair and w2, w3 of a second pair.

[0210] In some embodiments, the local oscillator provides a sampling clock to a plurality of samplers operating on the orthogonal subchannel outputs in the first mode. In some embodiments, the method further includes applying a corresponding subchannel-specific delay to the sampling clock before providing it to each of the plurality of samplers.

[0211] In some implementations, the orthogonal subchannel output is an integrated non-return-to-zero (ENRZ) subchannel output.

[0212] In some embodiments, the method further includes: in the first mode, connecting the input terminal of each of the plurality of MICs to a line in the multi-line bus according to a corresponding line input arrangement in a plurality of line input arrangements. In some such embodiments, each line input arrangement in the plurality of line input arrangements corresponds to a corresponding matrix row in a plurality of matrix rows of an orthogonal matrix.

[0213] In some implementations, each data-driven phase error signal is, for example, generated by... Figure 34 The sampler shown has a predictive decision feedback equalization (DFE) function, which is formed based on the selection result of a pair of predicted DFE correction values.

[0214] In some implementations, combining the plurality of data-driven phase error signals includes generating an analog summation of the analog data-driven phase error signals at a common node.

[0215] Although the ENRZ ODVS code has been described in detail in the above embodiments, it should be noted that other ODVS codes can also be used. A specific example is the CNR-5 code or "Glasswing" code described in "Shokrollahi 2". Figure 35 The diagram shows the MIC construction of a through-wing ODVS code according to some embodiments. In such embodiments, from Figure 2The method for receiving a clock signal emitted by MIC5 and transmitted via two dedicated clock lines can be exactly as simple as the method for receiving the same clock signal emitted by MIC4 and transmitted as a sub-channel of a vector signaling code. Such methods of embedding clocks within vector signaling code sub-channels are described in *Shokrollahi 2* and *Holden 3*. All clock embedding implementations described in these two documents can be advantageously combined with the PLL and timing control mechanisms described in this application, but this does not constitute a limitation. Furthermore, each specific implementation can process the sub-channel outputs of MIC0–MIC4 in a similar manner to achieve transition analysis of the received data, and through… Figure 34 The predictive DFE sampler provides early / late indication information for generating data-driven phase error signals. In one such implementation, NRZ mode can be entered by disabling MICs 3520, 3540, and 3550 and enabling MICs 3510 and 3530 to detect differential NRZ signals transmitted via lines w0, w1 and w3, w4, respectively. Furthermore, by enabling... Figure 35 All MICs and Figure 32 Modified to target a total of 5 sub-channel MICs instead of Figure 32 The three sub-channel microphones shown indicate that the device enters ODVS mode.

Claims

1. A method for receiving data, characterized in that, The method includes: In the vector signaling mode for data reception: Multiple data-driven phase error signals are generated from multiple mutually orthogonal sub-channel outputs using multiple vector signaling comparators; A composite data-driven phase error signal is generated from the plurality of data-driven phase error signals to adjust the local voltage-controlled oscillator used to sample the outputs of the plurality of mutually orthogonal sub-channels; In the non-return-to-zero signaling mode for data reception: Operate one or more of the vector signaling comparators as non-return-to-zero mode comparators; For each non-return-to-zero (NRZ) mode comparator, a NRZ output is generated from the corresponding differential input signal, and the corresponding voltage-controlled oscillator used to sample the NRZ output is adjusted based on the phase error measurement of the NRZ output.

2. The method as described in claim 1, characterized in that, Also includes: Switching between the vector signaling mode for data reception and the non-return-to-zero signaling mode for data reception.

3. The method as described in claim 2, characterized in that, Switching between the vector signaling mode for data reception and the non-return-to-zero signaling mode for data reception includes interpreting protocol messages received via the configured bus.

4. The method as described in claim 3, characterized in that, The protocol message is received as part of the bus negotiation sequence.

5. The method as described in claim 1, characterized in that, Operating the vector signaling comparator as a non-return-to-zero mode comparator includes disconnecting one or more corresponding inputs from each of the vector signaling comparators.

6. The method as described in claim 1, characterized in that, The plurality of data-driven phase error signals are generated using multiple charge pumps, and the generation of the composite data-driven phase error signal includes the analog summation result of generating the plurality of data-driven phase error signals.

7. The method as described in claim 1, characterized in that, Each mutually orthogonal subchannel output is also generated based on a corresponding subchannel-specific delay associated with the timing variations between the mutually orthogonal subchannel outputs.

8. The method as described in claim 7, characterized in that, It also includes using the data-driven phase error signal generated from the output of each mutually orthogonal subchannel to adjust the corresponding subchannel-specific delay.

9. The method as described in claim 1, characterized in that, During the vector signaling mode of data reception, the plurality of vector signaling comparators generate the plurality of mutually orthogonal sub-channel outputs by combining line signals received on a multi-line bus, based on input coefficients selected from an Adama matrix of size 4.

10. The method as described in claim 1, characterized in that, Generating each data-driven phase error signal includes (i) generating samples of the mutually orthogonal sub-channel outputs based on one of a pair of prediction-decision feedback equalization correction values, and (ii) generating the data-driven phase error signal based on the samples and the detected data pattern.

11. An apparatus for receiving data, characterized in that, The device includes: A mode controller for selecting between vector signaling mode and non-return-to-zero signaling mode for data reception; Multiple vector signaling comparators are used to generate multiple mutually orthogonal sub-channel outputs from line signals received via multiple lines of a multi-line bus during the vector signaling mode of data reception. A phase detector is used to generate a composite data-driven phase error signal from the sum of multiple data-driven phase error signals generated from the multiple mutually orthogonal sub-channel outputs during the vector signaling mode of the data reception. The phase detector is used to provide the composite data-driven phase error signal to a local voltage-controlled oscillator for sampling the multiple mutually orthogonal sub-channel outputs. One or more vector signaling comparators are configured to operate as non-return-to-zero mode comparators during the non-return-to-zero signaling mode of the data reception, each non-return-to-zero mode comparator being configured to generate a non-return-to-zero output from a corresponding differential input signal; and A phase detector is used to update the corresponding voltage-controlled oscillator based on a phase error measurement performed on each non-return-to-zero output during the non-return-to-zero mode of the data reception.

12. The apparatus as claimed in claim 11, characterized in that, The mode controller is used to interpret protocol messages received via the configured bus to switch between the vector signaling mode and the non-return-to-zero signaling mode of the data reception.

13. The apparatus as claimed in claim 12, characterized in that, The protocol message is received as part of the bus negotiation sequence.

14. The apparatus as claimed in claim 11, characterized in that, The mode controller is used to operate the vector signaling comparator as a non-return-to-zero mode comparator by disconnecting one or more corresponding inputs from each vector signaling comparator.

15. The apparatus as claimed in claim 11, characterized in that, The phase detector includes multiple charge pumps for generating the plurality of data-driven phase error signals, and a summing node for generating the composite data-driven phase error signal by generating an analog summation result of the plurality of data-driven phase error signals.

16. The apparatus as claimed in claim 11, characterized in that, It also includes a sub-channel specific delay element connected to each sub-channel output, each of the sub-channel specific delays being associated with a timing variation between the mutually orthogonal sub-channel outputs.

17. The apparatus as claimed in claim 16, characterized in that, The data-driven phase error signal generated from each mutually orthogonal sub-channel output is also used to adjust the corresponding sub-channel-specific delay connected to the mutually orthogonal sub-channel output.

18. The apparatus as claimed in claim 16, characterized in that, It also includes multiple selection circuits for selecting, respectively, the output of the sub-channel with a specific delay or the output of the mutually orthogonal sub-channels in the vector signaling mode and the non-return-to-zero signaling mode of the data reception.

19. The apparatus as claimed in claim 11, characterized in that, During the vector signaling mode of data reception, the plurality of vector signaling comparators are used to generate the plurality of mutually orthogonal sub-channel outputs by combining input coefficients selected according to a 4-dimensional Hadamard matrix on the line signals received on the multi-line bus.

20. The apparatus as claimed in claim 11, characterized in that, The phase detector is used to generate each data-driven phase error signal by: (i) generating samples of the mutually orthogonal sub-channel outputs based on one of a pair of prediction-decision feedback equalization correction values, and (ii) generating the data-driven phase error signal based on the samples and the detected data pattern.

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