Method for calibrating sampling time deviation of time-interleaved analog-to-digital converter

Abstract

The application belongs to the technical field of time-interleaved analog-to-digital converter, and relates to a sampling time deviation calibration method of a time-interleaved analog-to-digital converter. The application extracts the sampling time deviation information of the time-interleaved analog-to-digital converter by using the deviation direction information obtained by a Mueller-Muller type phase detector in a clock recovery circuit and combining the autocorrelation principle, and adjusts the sampling time of each analog-to-digital converter through calibration logic. Because the deviation direction information obtained by the Mueller-Muller type phase detector in the clock recovery circuit is multiplexed, the hardware overhead of the circuit is greatly reduced, and the area and power consumption of the circuit are reduced.

Description

Technical Field

[0001] This invention belongs to the technical field of time-interleaved analog-to-digital converters, and relates to a method for calibrating the sampling time deviation of a time-interleaved analog-to-digital converter. Background Technology

[0002] As data rates in wired communication links increase, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflection, and crosstalk become more pronounced. Under such high-loss channels, traditional slicer-based receivers struggle to recover high-quality signals. Therefore, more attention is focused on wired receivers based on time-interleaved analog-to-digital converters (ADCs), as they allow for more complex and flexible back-end digital signal processing and stronger equalization capabilities. However, the most significant non-ideal effect faced by time-interleaved ADCs is the discrepancy in sampling times between multiple channels. Various methods exist for extracting this discrepancy information, but each has its own limitations.

[0003] The extraction method based on sinusoidal input FFT involves sending a sinusoidal signal to the receiver input at a frequency equal to the sampling rate. The computer then calculates the FFT of the measured analog-to-digital converter output signal to obtain information about the offset mismatch between the sample-and-hold circuits of different channels. This sinusoidal input FFT extraction method has two drawbacks: firstly, it estimates the mismatch only by testing the highest input frequency; secondly, it cannot achieve real-time calibration of the sampling time deviation while the receiver is operating.

[0004] The autocorrelation extraction method is based on the theory of autocorrelation, which states that there is a linear relationship between the output data of two adjacent analog-to-digital converters (ADCs) and their sampling interval. By continuously accumulating the output data of two adjacent ADCs, the mismatch information between adjacent sampling times can be obtained. The main drawback of this method is that estimating timing deviations through autocorrelation requires the output of the ADC for statistical analysis; the higher the bit depth of the ADC, the greater the hardware overhead.

[0005] This method extracts the sampling deviation by using the output of the phase detector in the clock and data recovery circuit. The Mueller-Muller type clock and data recovery circuit is the most popular form of baud rate clock and data recovery. The Mueller-Muller phase detector receives data and error direction information, and adjusts the overall sampling phase based on this information. Some information is discarded, including information about the sampling distance. However, using the discarded output of the phase detector in the clock and data recovery circuit to extract sampling deviations suffers from limited information; more cycles are needed to acquire the sampling deviation information, which increases loop delay. Summary of the Invention

[0006] To address the aforementioned technical problems, the purpose of this invention is to provide a sampling time deviation calibration method for a time-interleaved analog-to-digital converter. This method reuses the deviation direction information obtained by the Mueller-Muller type phase detector in the clock recovery circuit, which greatly reduces the hardware overhead of the circuit and reduces the circuit area and power consumption.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] In a receiving system based on a time-interleaved analog-to-digital converter (ADC), the clock and data recovery circuits need to average the phase information from all sub-ADCs to ensure proper operation of the frequency and phase integrators in the digital domain, thereby averaging timing mismatches. However, even if the averaged sampling phase is at the desired position, each sub-ADC may sample earlier or later. This averaging function mixes all phase information, thus hiding information about the sampling timing deviation. Therefore, this invention provides a novel sampling timing deviation calibration method and system that reuses the deviation direction information obtained by the Mueller-Muller type phase detector in the clock recovery circuit, combines the autocorrelation principle to obtain the sampling timing deviation information, and adjusts the sampling timing of each ADC through calibration logic.

[0009] In most high-speed links, each parallel data point can be associated with a specific sub-analog-to-digital converter (ADC). With this insight, the output of each digital channel can be used to identify sampling timing skew. In an N×M architecture time-interleaved ADC, there are N channels, each containing M ADCs. The quantized data from each ADC is deserialized once, resulting in 2×N×M ADC Data and Error signals per sampling cycle. Since Data<1: 2×N×M> and Error<1: 2×N×M> are generated by N×M ADCs, each result can be associated with a specific ADC. Therefore, Data<1: 2×N×M> and Error<1: 2×N×M> can be used to identify sampling timing skew. The autocorrelation principle is applied to Error<1: 2×N×M> to obtain the sampling timing skew. Error1, ErrorN+1, Error 2N+1, ..., Error(2M-1)N+1 correspond to the successive approximation analog-to-digital converter (ADC) of channel 1 in a time-interleaved ADC. Error2, Error N+2, Error2N+2, ..., Error(2M-1)N+2 correspond to the successive approximation ADC of channel 2 in a time-interleaved ADC. Error3, Error N+3, Error2N+3, ..., Error(2M-1)N+3 correspond to the successive approximation ADC of channel 3 in a time-interleaved ADC. Error4, Error N+4, Error 2N+4, ..., Error(2M-1)N+4 correspond to the successive approximation ADC of channel 4 in a time-interleaved ADC. ErrorN, Error N+N, Error 2N+N, ..., Error(2M-1)N+N correspond to the successive approximation ADC of channel N in a time-interleaved ADC.

[0010] Due to the deviation direction information at the current moment e k Error, or Error, can be represented as:

[0011] e k =X k —D k h(τ) Formula 1

[0012] In the formula, X k This represents the quantized value of the analog-to-digital converter (ADC) at the current moment. D kData is the decision value of the quantization value of the analog-to-digital converter (ADC) at the current moment; h(τ) is the magnitude of the input signal level.

[0013] Formula 1 provides the deviation direction information at the current moment. E k Includes the quantized value of the analog-to-digital converter (ADC) X k Therefore, the deviation direction information is used. E k replace X k Obtaining the sampling time deviation information is a more preferable method, expressed as:

[0014] Formula 2

[0015] In the formula, e k+1 This provides information on the direction of deviation at the next moment. X k+1 This is the quantized value of the analog-to-digital converter (ADC) at the next moment. D k+1 This is the decision value for the quantization value of the analog-to-digital converter (ADC) at the next moment.

[0016] From the perspective of further simplifying the design, this invention adopts | e k+1 - e k | This achieves the extraction of sampling time deviation information. The basis for the sampling time deviation is:

[0017] Esum = E (| e k+1 - e k |) Formula 3

[0018] In the formula, e k Error indicating deviation direction information at the current moment. e k+1 Error indicating deviation direction information for the next moment. E This represents the expectation, which is an accumulation behavior. Esum This indicates the sampling time deviation information between two adjacent channels.

[0019] Based on the above theoretical analysis, the deviation direction information of the deviation detection is processed. For an N×M architecture, one sampling period will generate 2×N×M terms of deviation direction information Error. According to the sampling time order, the difference between the deviation direction information of the current time of a channel and the deviation direction information of the next time of its adjacent channel is calculated by Formula 4. The absolute value of the result is taken as the adjacent deviation term. Finally, all the adjacent deviation terms of the channel are accumulated to obtain the sampling time deviation information between two adjacent channels.

[0020] Esum i =E(| e i+kN+1 - e i+kN |), i =1,2,…N; k =0,1,2…2M-1; Formula 4

[0021] In the formula, Esum i Indicates channel i With channel i Sampling time deviation information between +1; N is the number of channels, and M is the number of analog-to-digital converters in each channel;

[0022] Esum1 This represents the sampling time deviation information between channel 1 and channel 2; Esum2 This represents the sampling time deviation information between channel 2 and channel 3; Esum3 This represents the sampling time deviation information between channel 3 and channel 4; channel N+1 is channel 1. EsumN This represents the sampling time deviation information between channel N and channel 1; the obtained Esum1~N It will be sent to the offset calibration logic to determine the offset direction and magnitude of the sampling time of the N-channel ADC, and then the delay unit switch will be adjusted.

[0023] Specifically, the sampling time deviation calibration method for a time-interleaved analog-to-digital converter according to the present invention includes the following steps:

[0024] S1. Based on the time-interleaved analog-to-digital converter architecture N×M, determine the number of channels N for which the deviation needs to be extracted and the number of analog-to-digital converters M for each channel; N and M are even numbers greater than or equal to 4.

[0025] Depending on the speed requirements of the high-speed serial port receiver circuit, time-interleaved analog-to-digital converters (ADCs) offer various configuration options, such as 4×8, 6×6, and 8×4. For instance, a 4×8 time-interleaved ADC includes four channels, each containing eight ADCs. Adjusting the sampling timing offset between these four channels requires extracting the sampling offset between them. The other configurations follow a similar pattern, allowing determination of the number of channels requiring offset extraction and the number of ADCs in each channel.

[0026] S2. Judge the quantization results of the time-interleaved analog-to-digital converter. One sampling period generates 2×N×M channels of deviation direction information for the analog-to-digital converter. Error<1: 2×N×M>;

[0027] The process by which the deviation direction information Error is generated is as follows:

[0028] Based on the amplitude range of the input signal level, the maximum reference threshold is set as the maximum level of the input signal, and the minimum reference threshold is set as the minimum level of the input signal. When the quantization result of the analog-to-digital converter is greater than or equal to the maximum reference threshold or less than or equal to the minimum reference threshold, the signal deviation direction information Error is judged as 1. When the quantization result of the analog-to-digital converter is greater than the minimum reference threshold and less than the maximum reference threshold, the deviation direction information Error is judged as -1.

[0029] S3. Based on the deviation direction information Error<1: 2×N×M> of the 2×N×M channel analog-to-digital converter obtained in step S2, using the autocorrelation principle and following the sampling time sequence, calculate the difference between the current time deviation direction information of a channel and the next time deviation direction information of its adjacent channel using Formula 4. Take the absolute value of the result as the adjacent deviation term. Finally, accumulate all the adjacent deviation terms of the channel to obtain the sampling time deviation information between two adjacent channels. Esum i , i =1,2,…N.

[0030] Esum i =E(| e i+kN+1 - e i+kN |), i =1,2,…N; k =0,1,2…2M-1; Formula 4

[0031] In the formula, Esum i Indicates channel i With channel iSampling time deviation information between +1; N is the number of channels, and M is the number of analog-to-digital converters in each channel; E Indicates accumulation; Esum 1 represents the sampling time deviation information between channel 1 and channel 2; Esum 2 represents the sampling time deviation information between channel 2 and channel 3; Esum 3 represents the sampling time deviation information between channel 3 and channel 4; channel N+1 is channel 1. Esum N represents the sampling time deviation information between channel N and channel 1;

[0032] Preferably, to make the results more accurate, the sampling time deviation information between two adjacent channels in multiple sampling periods is obtained.

[0033] S4. Determine the magnitude of the sampling time deviation information between channels and switch the capacitor switch according to the determination result; repeat steps S2~S4 until there is no sampling time deviation between channels;

[0034] If there is no sampling time deviation between the N channels of the successive approximation analog-to-digital converter in an N×M architecture time-interleaved analog-to-digital converter, then the sampling time deviation information... Esum i , i The accumulated values ​​of =1, 2, ..., N should be approximately equal. Conversely, if there is a sampling time skew between the N channels of the successive approximation analog-to-digital converter in a time-interleaved analog-to-digital converter, then the sampling time skew information... Esum i , i The values ​​for 1, 2, ..., N will be different. Based on this fundamental principle, sampling time deviation calibration logic can be set.

[0035] S4.1 Calculate sampling time deviation information Esum i , i =1,2,…N average value Eave And calculate the sampling time deviation information respectively. Esum i , i =1,2,…N and the average value Eave The difference Edif i , i =1,2,…N;

[0036] S4.2, Determine the difference Edif i , i Are the absolute values ​​of the numbers = 1, 2, ..., N greater than the threshold? Eth, Eth = Eave / L, where L ranges from 20 to 50, and the larger the value of L, the higher the precision;

[0037] If the difference Edif i , i The absolute values ​​of the numbers = 1, 2, ..., N are less than or equal to the threshold. Eth This indicates a channel. i With channel i There is no sampling time deviation between +1 and +1, and the control switch of the delay unit remains unchanged;

[0038] If the difference Edif i , i The absolute value of the integers 1, 2, ..., N is greater than the threshold. Eth This indicates a channel. i With channel i A sampling time deviation was detected between +1, and the difference was... Edif i With threshold Eth The larger the difference, the greater the sampling time deviation, and we continue to the next step of judgment;

[0039] S4.3, sequentially determine the difference between two adjacent values. Edif i and Edif i+1 , i Is the product of 1, 2, ..., N less than 0?

[0040] a. When the difference Edif i Sum and Difference Edif i+1 If the product is greater than 0, no action is taken, and the product of the next pair of adjacent differences is evaluated; because the difference... Edif i It is the difference between the sampling time deviation information and its average value, so it is impossible for all differences to be greater than 0. Therefore, when two adjacent differences occur... Edif i and Edif i+1 If the product is greater than 0, no action is taken, and the product of the next pair of adjacent differences is evaluated.

[0041] b. When the difference Edif i Sum and Difference Edif i+1 When the product is less than 0, there are two cases:

[0042] b1, Difference Edif i Greater than 0, difference Edif i+1If less than 0, it indicates a channel. i The sampling time of the +1 successive approximation analog-to-digital converter is far from the channel. i The sampling time of the successive approximation analog-to-digital converter is close to that of the channel. i +2 sampling time of successive approximation analog-to-digital converter; by reducing channels i The sampling time is adjusted by switching the delay unit of the successive approximation analog-to-digital converter with +1.

[0043] b2, Difference Edif i Less than 0, difference Edif i+1 A value greater than 0 indicates a channel. i The sampling time of the +1 successive approximation analog-to-digital converter is close to that of the channel. i The sampling time of the successive approximation analog-to-digital converter is far from the channel. i +2 sampling time of successive approximation analog-to-digital converter; by increasing the number of channels i The sampling time is adjusted by switching the delay unit of the +1 successive approximation analog-to-digital converter.

[0044] c. When two adjacent differences Edif i and Edif i+1 When the product of all terms is equal to 0, there are two cases:

[0045] c1, difference Edif i , i If the sum of 1, 2, ..., N is all equal to 0, then it represents a channel. i With channel i There is no sampling time deviation between +1 and +1, and the control switch of the delay unit remains unchanged;

[0046] c2, Difference Edif i , i Given a sequence of odd or even numbers in the range 1, 2, ..., N, where all numbers are equal to 0, determine if there exist any two adjacent differences where one difference is greater than 0 and the other is less than 0. This includes the following two cases:

[0047] c2.1, if Edif i Greater than 0, Edif i+2 If less than 0, reduce the number of channels. i The sampling time is adjusted by switching the delay unit of the +2 successive approximation analog-to-digital converter;

[0048] c2.2, if Edifi Less than 0, Edif i+2 If the value is greater than 0, then add a channel. i The sampling time is adjusted by switching the delay unit of the +2 successive approximation analog-to-digital converter.

[0049] S4.4 Repeat steps S2 to S4 after each delay unit adjustment until the difference is reached. Edif i , i =1,2,…N is less than the threshold Eth At this point, it will be determined that there is no sampling time deviation, the delay unit switches of N channels remain unchanged, and the sampling time deviation calibration is completed.

[0050] This invention provides a sampling time deviation calibration system for a time-interleaved analog-to-digital converter. The sampling time deviation calibration system includes a sample-and-hold circuit, a time-interleaved analog-to-digital converter, a digital signal processing module, a clock and data recovery circuit, a phase interpolator, a sampling time deviation calibration logic module, and a delay unit.

[0051] The sample-and-hold circuit samples the input analog signal and sends the sampled signal to the time-interleaved analog-to-digital converter for quantization. The quantized signal is then sent to the digital signal processing module, which equalizes and evaluates the quantized signal, outputting the result. Simultaneously, it sends the generated Data and Error signals to the clock and data recovery circuit. Based on the input Data and Error signals, the clock and data recovery circuit adjusts the phase of the output sampling clock of the phase interpolator, generating sampling time deviation information. Esum i , i The signals =1,2,…N are sent to the sampling time deviation calibration logic module; the sampling time deviation calibration logic module then... Esum i , i The value of =1,2,…N will determine the deviation of the sampling time and control the number of control switches of the delay unit based on the judgment result; finally, the sampling clock adjusted by the delay unit is sent to the sample-and-hold circuit to achieve sampling of the input signal at the optimal sampling phase.

[0052] The sample-and-hold circuit includes N channels of sample-and-hold circuits and a sample-and-hold divider-8 circuit that provides a corresponding clock to each channel. Each channel contains 8 sample-and-hold sub-modules. The sample-and-hold circuit of each channel receives the analog signal transmitted from the serial receiver and samples and holds it sequentially according to the clock signal. The N channels of sample-and-hold circuits send out N×M sampled signals to the subsequent N×M analog-to-digital converters for quantization. The sample-and-hold divider-8 circuit receives the four-phase quadrature sampling clock after deviation calibration and divides each clock by eight to generate eight non-overlapping clocks, which are sent to the 8 sample-and-hold sub-modules in each channel, providing the sample-and-hold circuit with the maximum sampling time.

[0053] The sample-and-hold submodule includes a bootstrap switch, which uses periodic charging to keep the gate and source voltages of the sampling NMOS (N-Metal-Oxide-Semiconductor) transistor N4 as constant as possible, thereby improving the linearization capability of the sampling switch.

[0054] The time-interleaved analog-to-digital converter (ADC) includes N successive approximation ADCs and a converter divider-8 circuit providing a corresponding clock for each channel. Each channel contains M successive approximation ADC submodules. Each channel's successive approximation ADC receives the sampled signal from the sample-and-hold circuit and quantizes it sequentially according to the clock signal. The N channels of successive approximation ADCs output N×M quantized signals to the subsequent digital signal processing module. The converter divider-8 circuit receives the offset-calibrated four-phase quadrature sampling clock and divides each clock by eight, generating eight non-overlapping clocks, which are then sent to the M successive approximation ADC submodules in each channel.

[0055] The successive approximation analog-to-digital converter (ADC) includes a capacitor array, a comparator, and logic circuitry. The ADC inputs the sampled signal from the sample-and-hold circuit to the internal capacitor array. The comparator then compares the magnitudes at the differential terminals to determine the switching direction of the capacitor array. The logic circuitry switches the capacitors of the array according to a binary ratio, effectively subtracting the reference voltage from the sampled signal sample with binary weights. This achieves binary convergence of the differential signal, searches for the corresponding binary digital code of the analog signal, and completes the analog-to-digital conversion.

[0056] The digital signal processing module includes a deserializer, a feedforward equalizer, and a decision feedback equalizer. The deserializer receives the N×M quantized signals from the time-interleaved analog-to-digital converter and deserializes them into 2×N×M quantized signals. The feedforward equalizer then equalizes the 2×N×M quantized signals. The decision feedback equalizer then performs decision feedback equalization on the 2×N×M quantized signals equalized by the feedforward equalizer, simultaneously discriminates the signals, outputs the decision result, and transmits the Data<1: 2×N×M> and Error<1: 2×N×M> required by the clock and data recovery circuits.

[0057] The clock and data recovery circuit includes an MMPD (Mueller-Muller Phase Detector), a decimation module, a proportional path gain module, an integral path gain module, a frequency integrator, a phase integrator, and a sampling time deviation information extraction module.

[0058] The Mueller-Muller phase detector receives the Data<1: 2×N×M> and Error<1: 2×N×M> signals transmitted from the digital signal processing module, judges them, and generates 2×N×M channels of Up or Down signals. The decimation module decimates these 2×N×M channels of Up or Down signals into one Up or Down signal. The proportional path gain module, integral path gain module, and frequency integrator combine to filter the single Up or Down signal. The phase integrator then integrates the filtered result to obtain the required phase selection for the phase interpolator. The sampling time deviation information extraction module extracts the sampling time deviation information of the four sampling clocks using the autocorrelation principle and Error<1: 2×N×M>, and then processes the extracted information. Esum i , i =1,2,…N are sent to the sampling time deviation calibration logic module to control the switching of the delay unit.

[0059] The phase interpolator includes a decoder and a CML (Current Mode Logic) type phase interpolator. The decoder receives the phase selection signal transmitted from the clock and data recovery circuit and converts it into the polarity selection and phase switching signals required by the CML type phase interpolator. The CML type phase interpolator receives a four-phase quadrature clock transmitted from the clock path and adjusts the overall phase of the input four-phase quadrature clock according to the polarity selection and phase switching switches, and then sends the adjusted clock to the delay unit.

[0060] The sampling time deviation calibration logic module receives the sampling deviation information extraction module and extracts the deviation information. Esum i , i =1,2,…N, and through certain logical judgments, determine the number of delay unit switches on the N-channel analog-to-digital converter clock path, and send the control code of the number to the delay unit.

[0061] The delay unit includes a decoder and a clock path containing a capacitor switch array. The decoder receives the four-channel analog-to-digital converter delay unit switch control code transmitted from the sampling time deviation calibration logic module and converts it into the switching signals required by the clock path containing the capacitor switch array. The clock path containing the capacitor switch array receives the phase-adjusted N-channel sampled clock signals from the phase interpolator, and then calibrates the sampling deviation of each sampled clock signal. For each additional switch closed in the switch array, an additional unit capacitor is connected to the clock signal, which affects the clock delay. Finally, the calibrated N-channel sampled signals are sent to the sample-and-hold circuit.

[0062] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0063] This invention utilizes the deviation direction information acquired by the Mueller-Muller type phase detector in the clock recovery circuit, combined with the autocorrelation principle, to extract the sampling time deviation information of the time-interleaved analog-to-digital converter (ADC), and adjusts the sampling time of each ADC through calibration logic. Because this method reuses the deviation direction information acquired by the Mueller-Muller type phase detector in the clock recovery circuit, it significantly reduces the hardware overhead, circuit area, and power consumption. Attached Figure Description

[0064] Figure 1 This is a block diagram of sampling time deviation calibration in a time-interleaved analog-to-digital converter in a serial receiver, provided by an embodiment of the present invention.

[0065] Figure 2 This is a circuit diagram of the sample-and-hold circuit provided in an embodiment of the present invention;

[0066] Figure 3 This is a circuit diagram of the bootstrap switch in the sample-and-hold circuit provided in an embodiment of the present invention;

[0067] Figure 4 This is a circuit diagram of a time-interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0068] Figure 5 This is a circuit diagram of the successive approximation analog-to-digital converter in the time-interleaved analog-to-digital converter provided in the embodiments of the present invention;

[0069] Figure 6 This is a circuit diagram of the digital signal processing module provided in an embodiment of the present invention;

[0070] Figure 7 This is a circuit diagram of the clock and data recovery circuit provided in an embodiment of the present invention;

[0071] Figure 8 This is a circuit diagram of the Mueller-Muller phase detector provided in an embodiment of the present invention;

[0072] Figure 9 This is a circuit diagram of the phase interpolator provided in an embodiment of the present invention;

[0073] Figure 10 This is a flowchart of the sampling time deviation calibration logic provided in the embodiments of the present invention;

[0074] Figure 11 This is a circuit diagram of the delay unit provided in an embodiment of the present invention.

[0075] The reference numerals in the attached figures are:

[0076] 200. Sampling Time Deviation Calibration Circuit

[0077] 210. Sample and Hold Circuit

[0078] 211. Channel Sample and Hold Circuit

[0079] 212. Sample and hold frequency divider circuit

[0080] 220. Time-Interleaved Analog-to-Digital Converter

[0081] 221. Successive Approximation Analog-to-Digital Converter for Each Channel

[0082] 2211, Capacitor Array

[0083] 2212. Comparator

[0084] 2213. Logic Circuits

[0085] 222. Converter 8-way divider circuit

[0086] 230. Digital Signal Processing Module

[0087] 231. Deserializer

[0088] 232. Feedforward Equalizer

[0089] 233. Judgment Feedback Equalizer

[0090] 240. Clock and Data Recovery Circuit

[0091] 241. Phase detector

[0092] 242. Extraction Module

[0093] 243. Integral Path Gain Module

[0094] 244. Frequency Integrator

[0095] 245. Phase Integrator

[0096] 246. Sampling Deviation Information Extraction Module

[0097] 247. Proportional Path Gain Module

[0098] 250. Phase interpolator

[0099] 251. Decoder

[0100] 252. CML (Current Mode Logic) type phase interpolator

[0101] 260. Sampling Time Deviation Calibration Logic Module

[0102] 270. Delay Unit

[0103] 271. Decoder

[0104] 272. Clock path containing a capacitor switch array. Detailed Implementation

[0105] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0106] Taking a 4×8 time-interleaved analog-to-digital converter as an example, there are 4 channels, each with 8 analog-to-digital converters (ADCs), for a total of 32 ADCs; Channel 1: ADC1, ADC5, ADC9, ADC13, ADC17, ADC21, ADC25, ADC29; Channel 2: ADC2, ADC6, ADC10, ADC14, ADC18, ADC22, ADC26, ADC30; Channel 3: ADC3, ADC7, ADC11, ADC15, ADC19, ADC23, ADC27, ADC31; Channel 4: ADC4, ADC8, ADC12, ADC16, ADC20, ADC24, ADC28, ADC32.

[0107] The present invention provides a sampling time deviation calibration method for a time-interleaved analog-to-digital converter, comprising the following steps:

[0108] S1. Based on the 4×8 time-interleaved analog-to-digital converter architecture, the number of channels for which the deviation needs to be extracted is 4 and the number of analog-to-digital converters for each channel is 8.

[0109] S2. Judge the quantization results of the time-interleaved analog-to-digital converter. One sampling cycle generates the deviation direction information of 32 channels of analog-to-digital converter. Error<1: 64>;

[0110] After the time-interleaved analog-to-digital converter (ADC) completes the quantization of the signal, it can be judged. The appropriate ADC precision is set according to the required bit error rate. In our applications, when the ADC precision is n bits, the value of n is generally between 3 and 7, and the quantization range of the ADC is 0 to 2. n .

[0111] Taking a 6-bit analog-to-digital converter (ADC) as an example, with a quantization range of 0 to 64, when the input signal level amplitude range is between 16 and 48, an intermediate threshold of 32 is set, and reference thresholds are 48 and 16. When the quantization result of the ADC is greater than or equal to 32, the decision value Data is set to 1; when the quantization result is less than 32, the decision value Data is set to -1. When the quantization result is greater than or equal to 48 or less than or equal to 16, the deviation direction information Error is set to 1; when the quantization result is greater than 16 and less than 48, the deviation direction information Error is set to -1. In this way, the quantization result of the time-interleaved ADC can generate corresponding Data and Error values.

[0112] Because deserialization is halved in speed, one analog-to-digital converter (ADC) can generate two error signals. For example, Error1(ADC1) indicates that this Error1 signal was generated by ADC1. The deviation direction information generated by channels 1-4 is as follows:

[0113] Channel 1: Error1 (ADC1), Error5 (ADC5), Error9 (ADC9), Error13 (ADC13), Error17 (ADC17), Error21 (ADC21), Error25 (ADC25), Error29 (ADC29), Error33 (ADC1), Error37 (ADC5), Error41 (ADC9), Error45 (ADC13), Error49 (ADC17), Error53 (ADC21), Error57 (ADC25), Error61 (ADC29);

[0114] Channel 2: Error2 (ADC2), Error6 (ADC6), Error10 (ADC10), Error14 (ADC14), Error18 (ADC18), Error22 (ADC22), Error26 (ADC26), Error30 (ADC30), Error34 (ADC2), Error38 (ADC6), Error42 (ADC10), Error46 (ADC14), Error50 (ADC18), Error54 (ADC22), Error58 (ADC26), Error62 (ADC30);

[0115] Channel 3: Error3 (ADC3), Error7 (ADC7), Error11 (ADC11), Error15 (ADC15), Error19 (ADC19), Error23 (ADC23), Error27 (ADC27), Error31 (ADC31), Error35 (ADC3), Error39 (ADC7), Error43 (ADC11), Error47 (ADC15), Error51 (ADC19), Error55 (ADC23), Error59 (ADC27), Error63 (ADC31);

[0116] Channel 4: Error4 (ADC4), Error8 (ADC8), Error12 (ADC12), Error16 (ADC16), Error20 (ADC20), Error24 (ADC24), Error28 (ADC28), Error32 (ADC32), Error36 (ADC4), Error40 (ADC8), Error44 (ADC12), Error48 (ADC16), Error52 (ADC20), Error56 (ADC24), Error60 (ADC28), Error64 (ADC32).

[0117] S3. Based on the deviation direction information Error<1: 64> of the 64-channel analog-to-digital converter obtained in step S2, the sampling time deviation information between two adjacent channels is calculated using the autocorrelation principle. Esum1~4 ;

[0118] Esum1=|Error2-Error1|+|Error6-Error5|+|Error10-Error9|+|Error14-Error13+|Error18-Error17|+|Error22-Error21|+|Error26-Error25|+|Error30-Error29|+|Error34-Error33|+|Error38-Error37|+|Error42-Error41|+|Error46-Error45|+|Error50-Error49|+|Error54-Error53|+|Error58-Error54|+|Error62-Error61|;

[0119] Esum 2=|Error3-Error2|+|Error7-Error6|+|Error11-Error10|+|Error15-Error14|+|Error19-Error18|+|Error23-Error22|+|Error27-Error26|+|Error31-Error30|+|Error35-Error34|+|Error39-Error38|+|Error43-Error42|+|Error47-Error46|+|Error51-Error50|+|Error55-Error54|+|Error59-Error58|+|Error63-Error62|;

[0120] Esum 3=|Error4-Error3|+|Error8-Error7|+|Error12-Error11|+|Error16-Error15|+|Error20-Error19|+|Error24-Error23|+|Error28-Error27|+|Error32-Error31|+|Error36-Error35|+|Error40-Error39|+|Error44-Error43|+|Error48-Error47|+|Error52-Error51|+|Error56-Error55|+|Error60-Error59|+|Error64-Error63|;

[0121] Esum4=|Error5-Error4|+|Error9-Error8|+|Error13-Error12|+|Error17-Error16|+|Error21-Error20|+|Error25-Error24|+|Error29-Error28|+|Error33-Error32|+ |Error37-Error36|+|Error41-Error40|+|Error45-Error44|+|Error49-Error48|+|Error53-Error52|+|Error57-Error56|+|Error61-Error60|+|Error1-Error64|;

[0122] Esum1 This represents the sampling time deviation information between channel 1 and channel 2;

[0123] Esum2 This represents the sampling time deviation information between channel 2 and channel 3;

[0124] Esum3 This represents the sampling time deviation information between channel 3 and channel 4;

[0125] Esum4 This represents the sampling time deviation information between channel 4 and channel 1;

[0126] The more accumulation times, the easier it is to distinguish sampling deviation information, but the longer the calibration period will be. A reasonable number of accumulation times should be set, taking into account both the accuracy of deviation information resolution and the calibration period. Esum1~4 This refers to the sampling time deviation information of the four channels in the 4×8 architecture. If the time-interleaved analog-to-digital converter uses a different number of channels, the sampling time deviation information is extracted according to the same principle.

[0127] S4. Determine the magnitude of the sampling time deviation information between channels and switch the capacitor switch accordingly;

[0128] If there is no sampling time deviation among the four successive approximation analog-to-digital converters 221 in the 4×8 architecture time-interleaved analog-to-digital converter 220, then Esum1~4 The accumulated values ​​should be approximately equal. Conversely, if there is a sampling timing deviation among the four channels of the successive approximation analog-to-digital converter 221 in the time-interleaved analog-to-digital converter, then... Esum1~4 The values ​​will be different. Based on this basic principle, sampling time deviation calibration logic can be set.

[0129] S4.1, calculate first Esum1~4 average Eaveand find Esum1~4 Its average Eave The difference Edif1 ~4 .

[0130] S4.2, Next, determine the difference. Edif1~4 Is the absolute value less than the threshold? Eth;Eth The size can be set to Eave / L, the larger L is, the higher the precision.

[0131] If the difference Edif The absolute value of 1 is less than the threshold. Eth This indicates that there is no sampling time deviation between channel 1 and channel 2, and the control switch of the delay unit remains unchanged;

[0132] If the difference Edif The absolute value of 2 is less than the threshold. Eth This indicates that there is no sampling time deviation between channel 2 and channel 3, and the control switch of the delay unit remains unchanged;

[0133] If the difference Edif The absolute value of 3 is less than the threshold. Eth This indicates that there is no sampling time deviation between channel 3 and channel 4, and the control switch of the delay unit remains unchanged;

[0134] If the difference Edif The absolute value of 4 is less than the threshold. Eth This indicates that there is no sampling time deviation between channel 4 and channel 1, and the control switch of the delay unit remains unchanged;

[0135] If the difference Edif1~4 The absolute value is greater than the threshold Eth This indicates that a sampling time deviation has been detected. Edif1~4 and Eth From the perspective of the difference, the larger the difference, the greater the deviation in the sampling time.

[0136] S4.3, sequentially judge Edif1~4 Is the product of two adjacent differences less than 0?

[0137] a. When the difference Edif1 Sum and Difference Edif2 If the product is greater than 0, no action is taken, and the product of the next pair of adjacent differences is evaluated.

[0138] b. If Edif1 and Edif2 The product is less than 0; if Edif1 Greater than 0, Edif2If the value is less than 0, then it can be known that the sampling time of the successive approximation analog-to-digital converter 221 of the second channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the first channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the third channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the second channel. If... Edif1 Less than 0, Edif2 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 of the second channel should be switched to adjust the sampling time.

[0139] like Edif2 and Edif3 The product is less than 0; if Edif2 Greater than 0, Edif3 If the value is less than 0, then it can be known that the sampling time of the successive approximation analog-to-digital converter 221 of the third channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the second channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the fourth channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the third channel. If... Edif2 Less than 0, Edif3 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the third channel should be switched to adjust the sampling time.

[0140] like Edif3 and Edif4 If the product is less than 0, Edif3 Greater than 0, Edif4 If the value is less than 0, then it can be known that the sampling time of the successive approximation analog-to-digital converter 221 of the fourth channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the third channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the first channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the fourth channel. If... Edif3 Less than 0, Edif4 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel should be switched to adjust the sampling time.

[0141] like Edif4 and Edif1 If the product is less than 0, Edif4 Greater than 0, Edif1If the value is less than 0, then it can be known that the sampling time of the successive approximation analog-to-digital converter 221 of the first channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the fourth channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the second channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the first channel. If... Edif4 Less than 0, Edif1 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 of the first channel should be switched to adjust the sampling time.

[0142] c. If Edif1~4 If the product of two consecutive terms equals 0, then we need to determine whether it is... Edif1 and Edif3 =0 or Edif2 and Edif4 Equal to 0;

[0143] like Edif1~4 If all values ​​are 0, it means there is no sampling time deviation and no adjustment is needed;

[0144] in the case of Edif1 and Edif3 If it equals 0, then it is true. Edif2 and Edif4 Make a judgment if Edif2 Greater than 0, Edif4 If the value is less than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel is reduced to adjust the sampling time. Edif2 Less than 0, Edif4 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel is switched to adjust the sampling time.

[0145] in the case of Edif2 and Edif4 If it equals 0, then it is true. Edif1 and Edif3 Make a judgment if Edif1 Greater than 0, Edif3 If the value is less than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the third channel is reduced to adjust the sampling time. Edif1 Less than 0, Edif3 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the third channel is switched to adjust the sampling time.

[0146] If a time-interleaved analog-to-digital converter uses a 6×6 architecture, then following the same principle, Edif1~6 The product of any two consecutive terms equals 0, which is an odd sequence. Edif1 , Edif3 , Edif5All equal to 0, or an even sequence Edif2 , Edif4 , Edif6 All equal to 0; if the odd sequence Edif1 , Edif3 , Edif5 All equal to 0, difference Edif4 If the value is less than 0, determine the difference between the two adjacent values ​​in the sequence containing the given value. Edif2 and Edif6 Does it contain a value greater than 0? This includes the following two cases: Edif4 When less than 0, if Edif2 Greater than 0, regardless of Edif6 If the value is greater than 0, the switching of the delay unit of the successive approximation analog-to-digital converter in the fourth channel is reduced to adjust the sampling time; Edif4 When less than 0, if Edif2 Less than 0, Edif6 If the value is greater than 0, then the delay unit of the successive approximation analog-to-digital converter in the sixth channel is switched to adjust the sampling time; and so on.

[0147] S4.4 Repeat steps S2 to S4 after each delay unit adjustment until... Edif1~4 Less than the threshold Eth At this point, it will be determined that there is no sampling time deviation, the delay unit switches of the four channels remain unchanged, and the sampling time deviation calibration is completed.

[0148] like Figure 1 As shown in the figure, a sampling time deviation calibration system 200 for a time-interleaved analog-to-digital converter in a serial receiver based on deviation direction information acquired by a Mueller-Muller phase detector according to an embodiment of the present invention includes a sample-and-hold circuit 210, a time-interleaved analog-to-digital converter 220, a digital signal processing module 230, a clock and data recovery circuit 240, a phase interpolator 250, a sampling time deviation calibration logic module 260, and a delay unit 270.

[0149] In this embodiment, the time-interleaved analog-to-digital converter adopts a 4-channel architecture with 8 sub-modules per channel. Other numerical architectures under different rate allocation schemes can also adopt the sampling time deviation calibration system of this invention.

[0150] The sample-and-hold circuit 210 samples the input analog signal and sends the sampled signal to the time-interleaved analog-to-digital converter 220 for quantization. The quantized signal is then sent to the digital signal processing module 230, which performs equalization and judgment on the quantized signal, outputting the judgment result. Simultaneously, the generated Data and Error signals are sent to the clock and data recovery circuit 240. Based on the input Data and Error signals, the clock and data recovery circuit 240 adjusts the phase of the output sampling clock of the phase interpolator 250, and simultaneously generates sampling time deviation information. Esum1~4 The signal is sent to the sampling time deviation correction logic module 260. The sampling time deviation correction logic module 260 then... Esum1~4 The magnitude of the delay clock value determines the deviation in the sampling time and controls the number of control switches in the delay unit 270 based on the determination result. Finally, the sampling clock value adjusted by the delay unit 270 is sent to the sample-and-hold circuit 210 to achieve sampling of the input signal at the optimal sampling phase.

[0151] In this specific embodiment, please refer to Figure 2 The sample-and-hold circuit 210 includes four sample-and-hold circuits 211 and a sample-and-hold divider-8 circuit 212 that provides a corresponding clock to each channel. Each channel contains eight sample-and-hold sub-modules. Each channel's sample-and-hold circuit 211 receives the analog signal transmitted from the serial receiver and samples and holds it sequentially according to the clock signal. Here, the four channel sample-and-hold circuits 211 output 32 sampled signals to the subsequent 32 analog-to-digital converters for quantization. The sample-and-hold divider-8 circuit 212 receives the offset-calibrated four-phase quadrature sampling clock and divides each clock by eight to generate eight non-overlapping clocks, which are then sent to the eight sample-and-hold sub-modules in each channel, providing the sample-and-hold circuit with the maximum sampling time.

[0152] In this specific embodiment, please refer to Figure 3The quality of the sampling switch determines the sampling accuracy, which is the upper limit of the ADC's accuracy. Therefore, a switch that can sample linearly and has very low on-resistance is crucial to the design. The sample-and-hold submodule demonstrates the bootstrap switch used in this embodiment. This switch improves the linearity of the sampling switch by periodically charging the gate and source voltages of the sampling NMOS (N-Metal-Oxide-Semiconductor) transistor N4 as constant as possible. The bootstrap switch has two operating phases: a sampling phase and a holding phase. During the sampling phase, ck_sh is low and ck_shb is high. The PMOS (P-Metal-Oxide-Semiconductor) transistor P1 and the NMOS transistor N1 are turned on, and capacitor C1 is connected between the power supply and ground. During this time, capacitor C1 charges to the power supply voltage VDD. During the holding phase, ck_sh is high and ck_shb is low. During this time, all transmission gate switches in the circuit are in the open state, and transistors P1 and N1, which charge C1, are in the off state. The transmission gate effectively superimposes the capacitor voltages to generate a V_boost voltage (V_boost = Vin + VDD). This ensures that the gate-source voltage of the sampling transistor N4 is maintained at the VDD level during the hold phase. In this way, the performance of the sampling switch N4 can be significantly improved.

[0153] In this specific embodiment, please refer to Figure 4 The time-interleaved analog-to-digital converter 220 includes four successive approximation analog-to-digital converters 221 and a converter-8 divider circuit 222 that provides a corresponding clock for each channel. Each channel contains eight successive approximation analog-to-digital converter submodules. Each successive approximation analog-to-digital converter 221 receives the sampled signal from the sample-and-hold circuit 210 and quantizes it sequentially according to the clock signal. Here, the four successive approximation analog-to-digital converters 221 output 32 quantized signals to the subsequent digital signal processing module 230. The converter-8 divider circuit 222 receives the offset-calibrated four-phase quadrature sampling clock and divides each clock by eight to generate eight non-overlapping clocks, which are then sent to the eight successive approximation analog-to-digital converter submodules in each channel.

[0154] In this specific embodiment, please refer to Figure 5The successive approximation analog-to-digital converter 221 includes a capacitor array 2211, a comparator 2212, and a logic circuit 2213. The successive approximation analog-to-digital converter 221 inputs the sampled signal output from the sample-and-hold circuit 210 to the internal capacitor array 2211. The comparator 2212 then compares the magnitudes at both ends of the differential signal to determine the switching direction of the capacitor array. The logic circuit 2213 switches the capacitance of the capacitor array according to a binary ratio, effectively subtracting the reference voltage from the sampled signal sample with binary weights, ultimately achieving binary convergence of the differential signal, searching for the corresponding binary digital code of the analog signal, and completing the analog-to-digital conversion.

[0155] In this specific embodiment, please refer to Figure 6 The digital signal processing module 230 includes a deserializer 231, a feedforward equalizer 232, and a decision feedback equalizer 233. The deserializer 231 receives 32 quantized signals from the time-interleaved analog-to-digital converter 220 and deserializes them into 64 quantized signals. The feedforward equalizer 232 then equalizes the 64 quantized signals. The decision feedback equalizer 233 performs decision feedback equalization on the 64 quantized signals equalized by the feedforward equalizer 232, simultaneously discriminates the signals, outputs the decision result, and transmits the Data<1:64> and Error<1:64> values ​​required by the clock and data recovery circuit 240.

[0156] In this specific embodiment, please refer to Figure 7 The clock and data recovery circuit 240 includes a Mueller-Muller Phase Detector (MMPD) 241, a decimation module 242, a proportional path gain module 242, an integral path gain module 243, a frequency integrator 244, a phase integrator 245, and a sampling time deviation information extraction module 246. The Mueller-Muller phase detector 241 receives the Data<1:64> and Error<1:64> signals transmitted from the digital signal processing module 230, performs judgment, and generates 64 Up or Down signals. The decimation module 242 decimates the 64 Up or Down signals into one Up or Down signal. The proportional path gain module 242, the integral path gain module 243, and the frequency integrator 244 combine to filter the one Up or Down signal. The phase integrator 245 then integrates the filtered result to obtain the required phase selection for the phase interpolator 250. The sampling time deviation information extraction module 246 extracts the sampling time deviation information of the four sampling clocks using the autocorrelation principle and Error<1:64>, and then processes the extracted information. Esum1~4The signal is sent to the sampling time deviation calibration logic module 260 to control the switching of the delay unit.

[0157] In this specific embodiment, please refer to Figure 8 The Mueller-Muller phase detector 241 receives the Data<1:64> and Error<1:64> signals transmitted from the digital signal processing module 230. 64 sub-MMPDs judge the Data<1:64> and Error<1:64> signals and output 64 Up / Down signals to the decimation module 242. Since Data<1:64> and Error<1:64> are generated by a 32-channel analog-to-digital converter, each result of Data<1:64> and Error<1:64> can be associated with a specific analog-to-digital converter. Therefore, Data<1:64> and Error<1:64> can be used to identify sampling time deviations. In the specific implementation of this scheme, the autocorrelation principle is used to obtain the sampling time deviation for Error<1:64>. Figure 8 It can be seen that Error1, Error5, Error9, ..., Error61 correspond to the successive approximation analog-to-digital converter 221 of channel 1 in the time-interleaved analog-to-digital converter 220; Error2, Error6, Error10, ..., Error62 correspond to the successive approximation analog-to-digital converter 221 of channel 2 in the time-interleaved analog-to-digital converter 220; Error3, Error7, Error11, ..., Error63 correspond to the successive approximation analog-to-digital converter 221 of channel 3 in the time-interleaved analog-to-digital converter 220; and Error4, Error8, Error12, ..., Error64 correspond to the successive approximation analog-to-digital converter 221 of channel 4 in the time-interleaved analog-to-digital converter 220. Therefore, the Mueller-Muller phase detector 241 shares Error<1:64> from its input signal with the sampling time deviation information extraction module 246, which can then accumulate the sampling time deviation information between different channels based on the autocorrelation principle.

[0158] In this specific embodiment, please refer to Figure 9The phase interpolator 250 includes a decoder 251 and a CML (Current Mode Logic) type phase interpolator 252. The decoder 251 receives the phase selection signal transmitted from the clock and data recovery circuit 240 and converts it into the polarity selection and phase switching signals required by the CML type phase interpolator 252. The CML type phase interpolator 252 receives a four-phase quadrature clock transmitted from the clock path and adjusts the overall phase of the input four-phase quadrature clock according to the polarity selection and phase switching switches, then sends the adjusted clock to the delay unit 270. In this embodiment, the CML type phase interpolator 252 uses an octagonal phase interpolator to improve phase linearity and reduce amplitude modulation errors. It contains three current-controlled array switches: an I array switch, a Q array switch, and an IQ array switch, which apply their interpolation weights only internally. IP, IN and QP, QN are relative clock input pairs. When the I-array and Q-array switches are controlled, vertical and horizontal segments are created in the phase constellation diagram. Combined with the tilting segments of the IQ array switches, this results in an overall octagonal shape. The advantage of using octagonal phase interpolation is that the amplitude modulation amplitude is significantly reduced at different phase angles, lowering the likelihood of phase deviation during amplitude-to-phase modulation transitions. A more significant advantage of octagonal phase interpolation is its superior interpolation linearity. All three array switches in the octagonal phase interpolation use uniformly sized current switching units, resulting in optimal operating performance. The octagonal phase interpolation has 128 phase states evenly distributed on a phase circle, 32 states per quadrant. Each phase is switched by changing the state of one of the current control elements in one of the three array switches or by flipping one of the two polarity switches in the IQ array switch. By doing so, in-phase glitches are minimized when the rotor position is rotated. The IQ array switch has 17 identical unit-sized current control sections that control the current between its two outputs, plus two fixed-size half-size units permanently fixed to the two outputs. Therefore, this array switch has 18 different output states, with output currents of (17.5, 0.5), (16.5, 1.5), ... (0.5, 17.5). The I-array switch and Q-array switch have the same structure, with each array switch having 14 identical half-unit current control sections, producing 15 output states: (7, 0), (6.5, 0.5), ... (0, 7).

[0159] In this specific embodiment, please refer to Figure 10 The sampling time deviation calibration logic module 260 mainly introduces the logic of sampling time deviation adjustment. This module receives the sampling deviation information extraction module 246 and extracts the information containing the deviation. Esum1~4After certain logical judgments, the number of delay unit switches on the clock path of the four-channel analog-to-digital converter is determined, and the control code for the number is sent to the delay unit 270. The specific logical adjustment steps are as follows: First, the sampling time deviation calibration logic module 260 receives the sampling deviation information extraction module 246 and extracts the information containing the deviation. Esum1~4 If there is no sampling time deviation among the four successive approximation analog-to-digital converters 221 in the time-interleaved analog-to-digital converter 220, then Esum1~4 The accumulated values ​​should be approximately equal. Conversely, if there is a sampling timing deviation between the four channels of the successive approximation analog-to-digital converter 221 in the time-interleaved analog-to-digital converter 220, then Esum1~4 The values ​​will be different. Based on this fundamental principle, sampling time deviation calibration logic can be set. Next, calculate... Esum1~4 average Eave and find Esum1~4 Its average Eave The difference Edif1~4 Secondly, judgment Edif1~4 Is the difference less than the threshold? Eth .if Esum1~4 The difference between Edif1~4 The absolute value is less than the threshold Eth Assuming there is no sampling time deviation, the control switch of the delay unit remains unchanged. If some Edif1~4 The absolute value is greater than the threshold Eth This indicates that a sampling time deviation has been detected. The third step involves sequentially judging... Edif1~4 Is the product of two consecutive terms less than 0? Edif1 and Edif2 Multiplication less than 0 Edif1 Greater than 0, Edif2 If the value is less than 0, then it can be known that the sampling time of the successive approximation analog-to-digital converter 221 of the second channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the first channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the third channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the second channel. Similarly, if... Edif1 Less than 0, Edif2 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the second channel should be switched to adjust the sampling time. Edif2 and Edif3 Multiplication less than 0 Edif2 Greater than 0, Edif3If the value is less than 0, then we know that the sampling time of the successive approximation analog-to-digital converter 221 in the third channel is far from the sampling time of the successive approximation analog-to-digital converter 221 in the second channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 in the fourth channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the third channel. Similarly, if... Edif2 Less than 0, Edif3 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the third channel should be switched to adjust the sampling time. Edif3 and Edif4 Multiplication less than 0 Edif3 Greater than 0, Edif4 If the value is less than 0, then we know that the sampling time of the successive approximation analog-to-digital converter 221 in the fourth channel is far from the sampling time of the successive approximation analog-to-digital converter 221 in the third channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 in the first channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel. Similarly, if... Edif3 Less than 0, Edif4 If the value is greater than 0, the delay unit of the fourth channel's successive approximation analog-to-digital converter 221 should be switched to adjust the sampling time. Edif4 and Edif1 Multiplication less than 0 Edif4 Greater than 0, Edif1 If the value is less than 0, then we know that the sampling time of the successive approximation analog-to-digital converter 221 of the first channel is far from the sampling time of the successive approximation analog-to-digital converter 221 of the fourth channel, and close to the sampling time of the successive approximation analog-to-digital converter 221 of the second channel. Therefore, the sampling time can be adjusted by reducing the switching of the delay unit of the successive approximation analog-to-digital converter 221 of the first channel. Similarly, if... Edif4 Less than 0, Edif1 If the value is greater than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the first channel should be increased to adjust the sampling time. If Edif1 - 4 If the product of two consecutive terms equals 0, then it is necessary to determine whether it is... Edif1 and Edif3 =0 or Edif2 and Edif4 It equals 0, if it is Edif1 and Edif3 If it equals 0, then it is true. Edif2 and Edif4 Make a judgment if Edif2 Greater than 0, Edif4 If the value is less than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel is reduced to adjust the sampling time. Edif2Less than 0, Edif4 If the value is greater than 0, the delay unit of the successive approximation analog-to-digital converter 221 in the fourth channel is switched to adjust the sampling time. If it is... Edif2 and Edif4 If it equals 0, then it is true. Edif1 and Edif3 Make a judgment if Edif1 Greater than 0, Edif3 If the value is less than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the third channel is reduced to adjust the sampling time. Edif1 Less than 0, Edif3 If the value is greater than 0, the switching of the delay unit of the successive approximation analog-to-digital converter 221 in the third channel is increased to adjust the sampling time. After each adjustment of the delay unit, Esum1 - 4 It will be reset to zero and then accumulated again until... Edif1 ~4 Less than the threshold Eth At this point, it will be determined that there is no sampling time deviation, and the delay unit switches of the four channels remain unchanged.

[0160] In this specific embodiment, please refer to Figure 11 The delay unit 270 includes a decoder 271 and a clock path 272 containing a capacitor switch array. The decoder 271 receives the four-channel analog-to-digital converter delay unit switch control code transmitted from the sampling time deviation calibration logic module 260 and converts it into the switch signals required by the clock path 272 containing the capacitor switch array. The clock path 272 containing the capacitor switch array receives the phase-adjusted four-channel sampling clock signals from the phase interpolator 250, and then calibrates the sampling deviation of each sampling clock signal. For each additional switch in the switch array S1, S2, ..., SN, an additional unit capacitor is connected to the clock signal, which will affect the clock delay. Finally, the calibrated four-channel sampling signals will be sent to the sample-and-hold circuit 210.

Claims

1. A method for calibrating the sampling time deviation of a time-interleaved analog-to-digital converter, characterized in that, The method includes the following steps: S1. Based on the time-interleaved analog-to-digital converter architecture N×M, determine the number of channels N for which the deviation needs to be extracted and the number of analog-to-digital converters M for each channel; S2. Judge the quantization results of the time-interleaved analog-to-digital converter. One sampling period generates 2×N×M channels of deviation direction information for the analog-to-digital converter. Error<1: 2×N×M>; S3. Based on the deviation direction information Error<1: 2×N×M> of the 2×N×M channel analog-to-digital converter obtained in step S2, using the autocorrelation principle and following the sampling time sequence, calculate the difference between the current time deviation direction information of a channel and the next time deviation direction information of its adjacent channel using Formula 4. Take the absolute value of the result as the adjacent deviation term. Finally, accumulate all the adjacent deviation terms of the channel to obtain the sampling time deviation information between two adjacent channels. Esum i , i =1,2,…N; Esum i =E(| e i+kN+1 - e i+kN |), i =1,2,…N; k =0,1,2…2M-1; Formula 4 In the formula, Esum i Indicates channel i With channel i Sampling time deviation information between +1; N M represents the number of channels, where M is the number of analog-to-digital converters per channel. E Indicates accumulation; Esum 1 represents the sampling time deviation information between channel 1 and channel 2; Esum 2 represents the sampling time deviation information between channel 2 and channel 3; Esum 3 represents the sampling time deviation information between channel 3 and channel 4; channel N+1 is channel 1. Esum N represents the sampling time deviation information between channel N and channel 1; S4. Determine the magnitude of the sampling time deviation information between channels and switch the capacitor switch according to the determination result; repeat steps S2~S4 until there is no sampling time deviation between channels; S4.1 Calculate sampling time deviation information Esum i , i =1,2,…N average value Eave And calculate the sampling time deviation information respectively. Esum i , i =1,2,…N and the average value Eave The difference Edif i , i =1,2,…N; S4.2, Determine the difference Edif i , i Are the absolute values ​​of the numbers = 1, 2, ..., N greater than the threshold? Eth, Eth = Eave / L, where L ranges from 20 to 50, and the larger the value of L, the higher the precision; If the difference Edif i , i The absolute values ​​of the numbers = 1, 2, ..., N are less than or equal to the threshold. Eth This indicates a channel. i With channel i There is no sampling time deviation between +1 and +1, and the control switch of the delay unit remains unchanged; If the difference Edif i , i The absolute value of the integers 1, 2, ..., N is greater than the threshold. Eth This indicates a channel. i With channel i A sampling time deviation was detected between +1, and the difference was... Edif i With threshold Eth The larger the difference, the greater the sampling time deviation, and we continue to the next step of judgment; S4.3, sequentially determine the difference between two adjacent values. Edif i and Edif i+1 , i Is the product of 1, 2, ..., N less than 0? a. When the difference Edif i Sum and Difference Edif i+1 If the product is greater than 0, no action is taken, and the product of the next pair of adjacent differences is evaluated. b. When the difference Edif i Sum and Difference Edif i+1 When the product is less than 0, there are two cases: b1, Difference Edif i Greater than 0, difference Edif i+1 If less than 0, it indicates a channel. i The sampling time of the +1 successive approximation analog-to-digital converter is far from the channel. i The sampling time of the successive approximation analog-to-digital converter is close to that of the channel. i +2 sampling time of successive approximation analog-to-digital converter; by reducing channels i The sampling time is adjusted by switching the delay unit of the successive approximation analog-to-digital converter with +1; b2, Difference Edif i Less than 0, difference Edif i+1 A value greater than 0 indicates a channel. i The sampling time of the +1 successive approximation analog-to-digital converter is close to that of the channel. i The sampling time of the successive approximation analog-to-digital converter is far from the channel. i +2 sampling time of successive approximation analog-to-digital converter; by increasing the number of channels i The sampling time is adjusted by switching the delay unit of the successive approximation analog-to-digital converter with +1; c. When two adjacent differences Edif i and Edif i+1 When the product of all terms is equal to 0, there are two cases: c1, difference Edif i , i If the sum of 1, 2, ..., N is all equal to 0, then it represents a channel. i With channel i There is no sampling time deviation between +1 and +1, and the control switch of the delay unit remains unchanged; c2, Difference Edif i , i Given a sequence of odd or even numbers in the range 1, 2, ..., N, where all numbers are equal to 0, determine if there exist any two adjacent differences where one difference is greater than 0 and the other is less than 0. This includes the following two cases: c2.1, if Edif i Greater than 0, Edif i+2 If less than 0, reduce the number of channels. i The sampling time is adjusted by switching the delay unit of the +2 successive approximation analog-to-digital converter; c2.2, if Edif i Less than 0, Edif i+2 If the value is greater than 0, then add a channel. i The sampling time is adjusted by switching the delay unit of the +2 successive approximation analog-to-digital converter; S4.4 Repeat steps S2 to S4 after each delay unit adjustment until the difference is reached. Edif i , i =1,2,…N is less than the threshold Eth There is no sampling time deviation between channels, the delay unit switches of N channels remain unchanged, and the sampling time deviation calibration is completed.

2. The method according to claim 1, characterized in that, In step S2, the process of generating the deviation direction information Error is as follows: Based on the amplitude range of the input signal level, the maximum reference threshold is set as the maximum level of the input signal, and the minimum reference threshold is set as the minimum level of the input signal. When the quantization result of the analog-to-digital converter is greater than or equal to the maximum reference threshold or less than or equal to the minimum reference threshold, the signal deviation direction information Error is judged as 1. When the quantization result of the analog-to-digital converter is greater than the minimum reference threshold and less than the maximum reference threshold, the deviation direction information Error is judged as -1.

3. A sampling time deviation calibration system for a time-interleaved analog-to-digital converter as described in any one of claims 1-2, characterized in that, The sampling time deviation calibration system includes a sample-and-hold circuit, a time-interleaved analog-to-digital converter, a digital signal processing module, a clock and data recovery circuit, a phase interpolator, a sampling time deviation calibration logic module, and a delay unit; The sample-and-hold circuit samples the input analog signal and sends the sampled signal to the time-interleaved analog-to-digital converter for quantization. The quantized signal is then sent to the digital signal processing module, which equalizes and evaluates the quantized signal, outputting the result. Simultaneously, it sends the generated Data and Error signals to the clock and data recovery circuit. Based on the input Data and Error signals, the clock and data recovery circuit adjusts the phase of the output sampling clock of the phase interpolator, generating sampling time deviation information. Esum i , i =1,2,…N signals are sent to the sampling time deviation calibration logic module; The sampling time deviation correction logic module is based on Esum i , i The value of =1,2,…N will determine the deviation of the sampling time and control the number of control switches of the delay unit based on the judgment result; finally, the sampling clock adjusted by the delay unit is sent to the sample-and-hold circuit to achieve sampling of the input signal at the optimal sampling phase.

4. The sampling time deviation calibration system according to claim 3, characterized in that, The sample-and-hold circuit includes N channels of sample-and-hold circuits and a sample-and-hold divider-8 circuit that provides a corresponding clock for each channel. Each channel contains 8 sample-and-hold sub-modules. The sample-and-hold circuit of each channel receives the analog signal transmitted from the serial receiver and samples and holds it sequentially according to the clock signal. The N channels of sample-and-hold circuits send out N×M sampled signals to the subsequent N×M analog-to-digital converters for quantization. The sample-and-hold divider-8 circuit receives the four-phase quadrature sampling clock after deviation calibration and divides each clock by eight to generate eight non-overlapping clocks, which are sent to the 8 sample-and-hold sub-modules in each channel to provide the maximum sampling time for the sample-and-hold circuit.

5. The sampling time deviation calibration system according to claim 4, characterized in that, The sample-and-hold submodule includes a bootstrap switch, which keeps the gate and source voltages of the sampling NMOS transistor N4 constant by periodically charging, thereby improving the linearization capability of the sampling switch.

6. The sampling time deviation calibration system according to claim 3, characterized in that, The time-interleaved analog-to-digital converter includes N successive approximation analog-to-digital converters and a converter divider circuit that provides a clock to each channel. Each channel contains M successive approximation analog-to-digital converter sub-modules. Each successive approximation analog-to-digital converter receives the sampled signal transmitted from the sample-and-hold circuit and quantizes it sequentially according to the clock signal. The N successive approximation analog-to-digital converters will send out N×M quantized signals to the subsequent digital signal processing module. The converter's 8-division circuit receives the four-phase quadrature sampling clock after deviation calibration and divides each clock by eight to generate eight non-overlapping clocks, which are then sent to the M successive approximation analog-to-digital converter submodules in each channel. The successive approximation analog-to-digital converter includes a capacitor array, a comparator, and logic circuitry. The successive approximation analog-to-digital converter inputs the sampling signal output from the sample-and-hold circuit to the internal capacitor array, and then compares the magnitudes at both ends of the differential signal through the comparator to obtain the switching direction of the capacitor array. The logic circuit switches the capacitors of the capacitor array according to a binary ratio, which is equivalent to subtracting the reference voltage from the sampled signal sample with binary weights, ultimately achieving the binary convergence effect of the differential signal, searching for the binary digital code corresponding to the analog signal, and completing the analog-to-digital conversion.

7. The sampling time deviation calibration system according to claim 3, characterized in that, The digital signal processing module includes a deserializer, a feedforward equalizer, and a decision feedback equalizer; the deserializer receives N×M quantized signals from a time-interleaved analog-to-digital converter and deserializes them into 2×N×M quantized signals. The feedforward equalizer then equalizes the 2×N×M quantized signals. The decision feedback equalizer then performs decision feedback equalization on the 2×N×M quantized signals equalized by the feedforward equalizer, and simultaneously judges the signals and outputs the decision result. At the same time, it transmits the Data<1: 2×N×M> and Error<1: 2×N×M> required by the clock and data recovery circuit.

8. The sampling time deviation calibration system according to claim 3, characterized in that, The clock and data recovery circuit includes a Mueller-Muller phase detector, a decimation module, a proportional path gain module, an integral path gain module, a frequency integrator, a phase integrator, and a sampling time deviation information extraction module. The Mueller-Muller phase detector receives the Data<1: 2×N×M> and Error<1: 2×N×M> signals transmitted from the digital signal processing module, makes a judgment, and generates 2×N×M Up or Down signals. The extraction module extracts the 2×N×M Up or Down signals into one Up or Down signal. The proportional path gain module, integral path gain module, and frequency integrator are combined to filter one up or down signal; the phase integrator then integrates the filtered result to obtain the required phase selection for the phase interpolator; the sampling time deviation information extraction module extracts the sampling time deviation information of the four sampling clocks using the autocorrelation principle and Error<1: 2×N×M>, and then processes the extracted information. Esum i , i =1,2,…N are sent to the sampling time deviation calibration logic module to control the switching of the delay unit.

9. The sampling time deviation calibration system according to claim 3, characterized in that, The phase interpolator includes a decoder and a CML-type phase interpolator. The decoder receives the phase selection signal transmitted from the clock and data recovery circuit and converts it into the polarity selection and phase switching signals required by the CML-type phase interpolator. The CML-type phase interpolator receives the four-phase quadrature clock transmitted from the clock path and adjusts the overall phase of the input four-phase quadrature clock according to the polarity selection and phase switching switches, and sends the adjusted clock to the delay unit.

10. The sampling time deviation calibration system according to claim 3, characterized in that, The sampling time deviation calibration logic module receives the sampling deviation information extraction module and extracts the deviation information. Esum i , i =1,2,…N, after certain logical judgments, determine the number of delay unit switches on the clock path of the N-channel analog-to-digital converter, and send the control code of the number to the delay unit; The delay unit includes a decoder and a clock path containing a capacitor switch array. The decoder receives the four-channel analog-to-digital converter delay unit switch control code transmitted from the sampling time deviation calibration logic module and converts it into the switch signals required by the clock path containing the capacitor switch array. The clock path containing the capacitor switch array receives the phase-adjusted N-channel sampling clock signals sent by the phase interpolator and then calibrates the sampling deviation of each sampling clock signal. For each additional switch closed in the switch array, an additional unit capacitor is connected to the clock signal, which will affect the clock delay. Finally, the calibrated N-channel sampling signals will be sent to the sample-and-hold circuit.

Images