GaN HEMT device and manufacturing method thereof
By designing a multi-channel stacked structure and an n-type GaN intermediate layer, the challenges of material growth and gate control in multi-channel GaN devices have been solved, enabling GaN HEMT devices with high on-current density and low subthreshold slope, thus promoting their large-scale commercial application.
Patent Information
- Application Number
- CN202610163612.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-15
AI Technical Summary
Multi-channel GaN devices face challenges in material growth, gate control, and manufacturing processes, leading to increased costs and limiting their large-scale commercial application.
A multi-channel stacked structure design is adopted, combining an n-type GaN intermediate layer and a gate trench structure. Current coupling of the multi-channel layers is achieved through the n-type GaN intermediate layer, and the threshold voltage of the sidewall channel and the bottom trench channel is controlled by the n-type doping concentration. This allows for the design of a GaN HEMT device with high on-current density and low subthreshold slope.
GaN HEMT devices with high on-current density, low subthreshold slope, and adjustable threshold voltage have been realized, improving the current transport capability and reliability of the devices and reducing on-resistance.
Smart Images
Figure CN122054635A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a GaN HEMT device and its manufacturing method. Background Technology
[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, exhibits significant advantages in high-frequency and high-power electronic devices due to its excellent physical and electrical properties, such as high electron mobility, high thermal stability, and wide bandgap (3.4 eV). With the rapid development of high-energy applications such as 5G communication, new energy vehicles, and data center power systems, higher performance requirements have been put forward for power devices. Multi-channel GaN power devices, as an extension of the high electron mobility transistor (HEMT) structure, have received widespread attention in recent years. The main feature of multi-channel GaN devices is the introduction of multiple parallel two-dimensional electron gas (2DEG) channels through the multilayer stacked structure of AlGaN / GaN heterojunction. The multi-channel structure design has the following advantages: (1) effectively increases the carrier density per unit area, achieving higher current density and lower on-resistance; (2) can disperse current density, reduce the risk of local hot spots, and improve device reliability and lifespan.
[0003] However, multi-channel GaN devices currently face many technical challenges, including: (1) the material growth process is difficult, requiring the realization of high-quality and high-uniformity heterojunction epitaxy; (2) for three-terminal devices, the multi-channel structure increases the difficulty of gate control of the channel, requiring the introduction of complex gate structure design (such as fin gate, all-around gate, etc.); (3) the high complexity of the manufacturing process leads to a significant increase in cost, which limits its large-scale commercial application. Summary of the Invention
[0004] To address the aforementioned problems, this invention proposes a GaN HEMT device and its manufacturing method, which possesses excellent characteristics such as high on-state current density, low subthreshold slope, and adjustable threshold voltage.
[0005] The technical solution of this invention is:
[0006] A GaN HEMT device, from bottom to top along the vertical direction of the device, includes a substrate 10, a buffer layer 20, a multi-channel layer, and a first dielectric layer 50 stacked together. The multi-channel layer comprises a first channel layer 30, a first barrier layer 40, a second channel layer 31, a second barrier layer 41, a third channel layer 32, a third barrier layer 42, a fourth channel layer 33, and a fourth barrier layer 43 stacked together. The first channel layer 30 is located on the upper surface of the buffer layer 20, and the fourth barrier layer 43 is located on the lower surface of the first dielectric layer 50. The upper surface of the first dielectric layer 50 has... A source electrode 61 and a drain electrode 62 are provided, and the source electrode 61 and the drain electrode 62 extend downward along the vertical direction of the device and sequentially penetrate the fourth barrier layer 43, the fourth channel layer 33, the third barrier layer 42, the third channel layer 32, the second barrier layer 41, the second channel layer 31, and the first barrier layer 40 before extending into the first channel layer 30. The source electrode 61 and the drain electrode 62 also extend to both sides along the lateral direction of the device. A second dielectric layer 70 is provided on the upper surface of the first dielectric layer 50 between the source electrode 61 and the drain electrode 62, and the second dielectric layer 70 extends to both sides along the lateral direction of the device to cover the surface. The surfaces of the source 61 and drain 62 are covered; a gate trench is provided between the source 61 and drain 62, the gate trench extending downwards along the vertical direction of the device and sequentially penetrating the fourth barrier layer 43, the fourth channel layer 33, the third barrier layer 42, the third channel layer 32, the second barrier layer 41, the second channel layer 31, and the first barrier layer 40 before extending into the first channel layer 30, while the junction depth of the lower surface of the gate trench is less than the junction depth of the lower surfaces of the source 61 and drain 62; an n-type GaN intermediate layer 80 is provided at the bottom and sides of the gate trench, and the n-type GaN intermediate layer 80... Layer 80 also extends along the upper surface of the second dielectric layer 70 to both sides of the device; a gate dielectric layer 90 is provided on the surface of the n-type GaN intermediate layer 80, the gate dielectric layer 90 extends along the upper surface of the n-type GaN intermediate layer 80 to both sides of the device to completely cover the upper surface of the second dielectric layer 70; a gate (100) is filled in the gate trench, the gate (100) also extends along the upper surface of the gate dielectric layer 90 to both sides of the device, and in the lateral direction of the device, the width of the gate dielectric layer 90 extending to both sides of the device is smaller than the width of the n-type GaN intermediate layer 80 extending to both sides of the device;
[0007] The device achieves uniform turn-off / turn-on voltages for the sidewall channels and bottom trench channels in the multi-channel layer through the n-type GaN intermediate layer 80, in order to avoid the problem of asynchronous turn-off / turn-on in the gate region.
[0008] Furthermore, the thickness of each channel layer in the multi-channel layer is 10-50 nm, and the thickness of each barrier layer is 5-20 nm.
[0009] Furthermore, the thickness of the n-type GaN intermediate layer 80 is 1-20 nm, and the width of the portion of the n-type GaN intermediate layer 80 extending from the upper surface of the second dielectric layer 70 to both sides of the device is 0.2-5 μm.
[0010] Furthermore, the gate dielectric layer 90 is one or more combinations of silicon nitride, silicon dioxide, aluminum oxide, magnesium oxide and hafnium dioxide, with a thickness of 10-100 nm.
[0011] Furthermore, the gate (100) is one or more of titanium, titanium nitride, aluminum and copper, with a thickness of 200-1000 nm; the gate (100) extends along the upper surface of the gate dielectric layer 90 to both sides of the device, wherein the width of the portion extending towards the source 61 is 0.2-2 μm, and the width of the portion extending towards the drain 62 is 0.2-10 μm, and the extended portion of the gate (100) is used as a metal field plate to control the electric field distribution of the device drift region.
[0012] Furthermore, the first dielectric layer 50 is one of silicon nitride and silicon dioxide, with a thickness of 10-300 nm, and the second dielectric layer 70 is one of silicon nitride and silicon dioxide, with a thickness of 10-200 nm.
[0013] Furthermore, the width of the portion of the source electrode 61 and the drain electrode 62 extending to both sides along the lateral direction of the device is 0.2-2 μm.
[0014] A method for manufacturing a GaN HEMT device includes the following steps:
[0015] Step 1: Epitaxially grow a buffer layer 20 and a multi-channel layer (which includes, from bottom to top, a first channel layer 30, a first barrier layer 40, a second channel layer 31, a second barrier layer 41, a third channel layer 32, a third barrier layer 42, a fourth channel layer 33, and a fourth barrier layer 43) on the substrate 10.
[0016] Step 2: Deposit the first dielectric layer 50;
[0017] Step 3: The source electrode 61 and drain electrode 62 are etched in the first round using wet or dry etching techniques to completely etch the first dielectric layer 50 in this area. On this basis, the multi-channel layer in this area is etched in the second round using dry etching techniques. The etching depth must reach at least the lower interface of the first barrier layer 40. Then, the source electrode 61 and drain electrode 62 metal are grown by evaporation or sputtering, and high-temperature rapid annealing is performed in a nitrogen or vacuum atmosphere to form N-type ohmic contacts between the source electrode 61 and drain electrode 62 and the multiple two-dimensional electron gas channels on the sidewall.
[0018] Step 4: Deposit the second dielectric layer 70;
[0019] Step 5: Use wet or dry etching techniques to perform the first round of etching on the gate structure location, completely etching the first dielectric layer 50 and the second dielectric layer 70 in this area. On this basis, use dry etching techniques to perform the second round of etching on the multi-channel layer in this area. The etching depth must reach at least the lower interface of the first barrier layer 40, so that multiple two-dimensional electron gas channels are completely cut off.
[0020] Step 6: An n-type GaN intermediate layer 80 is grown using a secondary epitaxial growth technique. Based on this, the n-type GaN intermediate layer 80 outside the gate structure region is removed by dry etching.
[0021] Step 7: Deposit the gate dielectric layer 90, and on this basis, grow the gate 100 by means of evaporation or sputtering.
[0022] The beneficial effects of this invention are as follows: Based on the multi-channel epitaxial structure, a high areal density of electron carriers can be obtained to improve the current conduction capability of the device. The current coupling of multiple 2DEG channels is achieved through the n-type GaN intermediate layer 80. By simultaneously and uniformly controlling the intrinsic threshold voltage of the sidewall channels and the low-level trench channels through the n-type doping concentration, the GaN HEMT has the excellent characteristics of high conduction current density, low subthreshold slope and adjustable threshold voltage. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the GaN HEMT with an n-type GaN intermediate layer according to the present invention;
[0024] Figure 2 This is a schematic diagram of the GaN HEMT with an n-type GaN intermediate layer after the first step of the process is completed according to the present invention;
[0025] Figure 3 This is a schematic diagram of the structure of GaN HEMT with an n-type GaN intermediate layer after the second step of the process is completed according to the present invention;
[0026] Figure 4 This is a schematic diagram of the structure after the third step of the GaN HEMT process with an n-type GaN intermediate layer of the present invention is completed;
[0027] Figure 5 This is a schematic diagram of the structure after the fourth step of the GaN HEMT process with an n-type GaN intermediate layer of the present invention is completed;
[0028] Figure 6 This is a schematic diagram of the structure after the fifth step of the GaN HEMT process with an n-type GaN intermediate layer of the present invention is completed;
[0029] Figure 7This is a schematic diagram of the structure after the sixth step of the GaN HEMT process with an n-type GaN intermediate layer of the present invention is completed;
[0030] Figure 8 This is a schematic diagram of the structure after the completion of the seventh step of the GaN HEMT process with an n-type GaN intermediate layer according to the present invention. Detailed Implementation
[0031] The present invention will now be described in further detail with reference to the accompanying drawings.
[0032] like Figure 1 As shown, the GaN HEMT device of the present invention includes, from bottom to top along the vertical direction of the device, a substrate 10, a buffer layer 20, a multi-channel layer, and a first dielectric layer 50 stacked together. The multi-channel layer comprises, in sequence, a first channel layer 30, a first barrier layer 40, a second channel layer 31, a second barrier layer 41, a third channel layer 32, a third barrier layer 42, a fourth channel layer 33, and a fourth barrier layer 43. The first channel layer 30 is located on the upper surface of the buffer layer 20, and the fourth barrier layer 43 is located on the lower surface of the first dielectric layer 50. The upper surface of the first dielectric layer 50 has, respectively, two sides. A source electrode 61 and a drain electrode 62 are provided, and the source electrode 61 and the drain electrode 62 extend downward along the vertical direction of the device and sequentially penetrate the fourth barrier layer 43, the fourth channel layer 33, the third barrier layer 42, the third channel layer 32, the second barrier layer 41, the second channel layer 31, and the first barrier layer 40 before extending into the first channel layer 30. The source electrode 61 and the drain electrode 62 also extend to both sides along the lateral direction of the device. A second dielectric layer 70 is provided on the upper surface of the first dielectric layer 50 between the source electrode 61 and the drain electrode 62, and the second dielectric layer 70 extends to both sides along the lateral direction of the device to cover the surface. The surfaces of the source 61 and drain 62 are covered; a gate trench is provided between the source 61 and drain 62, the gate trench extending downwards along the vertical direction of the device and sequentially penetrating the fourth barrier layer 43, the fourth channel layer 33, the third barrier layer 42, the third channel layer 32, the second barrier layer 41, the second channel layer 31, and the first barrier layer 40 before extending into the first channel layer 30, while the junction depth of the lower surface of the gate trench is less than the junction depth of the lower surfaces of the source 61 and drain 62; an n-type GaN intermediate layer 80 is provided at the bottom and sides of the gate trench, and the n-type GaN intermediate layer 80... Layer 80 also extends along the upper surface of the second dielectric layer 70 to both sides of the device; a gate dielectric layer 90 is provided on the surface of the n-type GaN intermediate layer 80, the gate dielectric layer 90 extends along the upper surface of the n-type GaN intermediate layer 80 to both sides of the device to completely cover the upper surface of the second dielectric layer 70; a gate (100) is filled in the gate trench, the gate (100) also extends along the upper surface of the gate dielectric layer 90 to both sides of the device, and in the lateral direction of the device, the width of the gate dielectric layer 90 extending to both sides of the device is smaller than the width of the n-type GaN intermediate layer 80 extending to both sides of the device.
[0033] The working principle of this invention is as follows: The on-resistance and output current of the device are mainly determined by the number of 2DEG channels in the multi-channel epitaxy. Compared with traditional single-channel epitaxy, it has a higher carrier surface density, thus exhibiting stronger current transport capability. The threshold voltage of the proposed transistor is mainly determined by the work function of the gate electrode, the thickness and dielectric constant of the gate dielectric layer, and the doping concentration and thickness of the n-type GaN intermediate layer. Among these factors, the lower the doping concentration and the thinner the thickness of the n-type GaN intermediate layer, the more positive the threshold voltage of the transistor. Furthermore, when the transistor is in the off state, a voltage bias negative to the threshold voltage is applied to the gate electrode, causing the depletion region to expand and the electrons in the n-type GaN intermediate layer to be completely depleted, thus pinching off the gate channel. When the transistor is in the on state, a voltage bias positive to the threshold voltage is applied to the gate electrode, causing the depletion region to shrink and the electrons in the n-type GaN intermediate layer to be partially or completely recovered, thus turning on the gate channel. Moreover, the n-type GaN intermediate layer near the gate recess structure can achieve current coupling between multiple 2DEG channels, enabling synchronous turn-on and turn-off of multiple channels, thus giving the proposed transistor better subthreshold characteristics.
[0034] like Figures 2-8 As shown, the manufacturing method of the device of the present invention includes:
[0035] Step 1: Epitaxially grow a buffer layer 20 and a multi-channel layer (which includes, from bottom to top, a first channel layer 30, a first barrier layer 40, a second channel layer 31, a second barrier layer 41, a third channel layer 32, a third barrier layer 42, a fourth channel layer 33, and a fourth barrier layer 43) on the substrate 10.
[0036] Step 2: Deposit the first dielectric layer 50;
[0037] Step 3: The source electrode 61 and drain electrode 62 are etched in the first round using wet or dry etching techniques to completely etch the first dielectric layer 50 in this area. On this basis, the multi-channel layer in this area is etched in the second round using dry etching techniques. The etching depth must reach at least the lower interface of the first barrier layer 40. Then, the source electrode 61 and drain electrode 62 metal are grown by evaporation or sputtering, and high-temperature rapid annealing is performed in a nitrogen or vacuum atmosphere to form N-type ohmic contacts between the source electrode 61 and drain electrode 62 and the multiple two-dimensional electron gas channels on the sidewall.
[0038] Step 4: Deposit the second dielectric layer 70;
[0039] Step 5: Use wet or dry etching techniques to perform the first round of etching on the gate structure location, completely etching the first dielectric layer 50 and the second dielectric layer 70 in this area. On this basis, use dry etching techniques to perform the second round of etching on the multi-channel layer in this area. The etching depth must reach at least the lower interface of the first barrier layer 40, so that multiple two-dimensional electron gas channels are completely cut off.
[0040] Step 6: An n-type GaN intermediate layer 80 is grown using a secondary epitaxial growth technique. Based on this, the n-type GaN intermediate layer 80 outside the gate structure region is removed by dry etching.
[0041] Step 7: Deposit the gate dielectric layer 90, and on this basis, grow the gate 100 by means of evaporation or sputtering.
[0042] It should be noted that in this invention, the multi-channel layer is described as 4 layers, but in practice, other numbers of layers are also included. The core of this invention is that multiple channel layers and barrier layers are simultaneously in contact with the n-type GaN intermediate layer, which realizes current coupling between multiple channels and significantly reduces the on-resistance of the device.
Claims
1. A GaN HEMT device, comprising, from bottom to top along the vertical direction of the device, a substrate (10), a buffer layer (20), a multi-channel layer, and a first dielectric layer (50) stacked together, wherein the multi-channel layer comprises, in sequence, a first channel layer (30), a first barrier layer (40), a second channel layer (31), a second barrier layer (41), a third channel layer (32), a third barrier layer (42), a fourth channel layer (33), and a fourth barrier layer (43), wherein the first channel layer (30) is located on the upper surface of the buffer layer (20), and the fourth barrier layer (43) is located on the lower surface of the first dielectric layer (50); a source (61) and a drain (62) are respectively located on both sides of the upper surface of the first dielectric layer (50), and Furthermore, the source (61) and drain (62) extend downward along the vertical direction of the device and sequentially penetrate the fourth barrier layer (43), the fourth channel layer (33), the third barrier layer (42), the third channel layer (32), the second barrier layer (41), the second channel layer (31), and the first barrier layer (40) before extending into the first channel layer (30). The source (61) and drain (62) also extend to both sides along the transverse direction of the device. A second dielectric layer (70) is provided on the upper surface of the first dielectric layer (50) between the source (61) and drain (62), and the second dielectric layer (70) extends to both sides along the transverse direction of the device to cover the surfaces of the source (61) and drain (62). A gate trench is provided between the source (61) and the drain (62). The gate trench extends downward along the vertical direction of the device and sequentially penetrates the fourth barrier layer (43), the fourth channel layer (33), the third barrier layer (42), the third channel layer (32), the second barrier layer (41), the second channel layer (31), and the first barrier layer (40) before extending into the first channel layer (30). At the same time, the junction depth of the lower surface of the gate trench is less than the junction depth of the lower surfaces of the source (61) and the drain (62). An n-type GaN intermediate layer (80) is provided at the bottom and sides of the gate trench. The second dielectric layer (70) extends to both sides of the device along the upper surface of the second dielectric layer (70); a gate dielectric layer (90) is provided on the surface of the n-type GaN intermediate layer (80), the gate dielectric layer (90) extends to both sides of the device along the upper surface of the n-type GaN intermediate layer (80) to completely cover the upper surface of the second dielectric layer (70); a gate (100) is filled in the gate trench, the gate (100) also extends to both sides of the device along the upper surface of the gate dielectric layer (90), and in the transverse direction of the device, the width of the gate dielectric layer (90) extending to both sides of the device is smaller than the width of the n-type GaN intermediate layer (80) extending to both sides of the device; The device achieves the unification of turn-off / turn-on voltages between the sidewall channels and the bottom trench channels in the multi-channel layer through the n-type GaN intermediate layer (80) to avoid the problem of asynchronous turn-off / turn-on in the gate region.
2. The GaN HEMT device according to claim 1, characterized in that, The thickness of each channel layer in the multi-channel layer is 10-50 nm, and the thickness of each barrier layer is 5-20 nm.
3. A GaN HEMT device according to claim 1, characterized in that, The thickness of the n-type GaN intermediate layer (80) is 1-20 nm, and the width of the portion of the n-type GaN intermediate layer (80) extending from the upper surface of the second dielectric layer (70) to both sides of the device is 0.2-5 μm.
4. A GaN HEMT device according to claim 1, characterized in that, The gate dielectric layer (90) is one or more of silicon nitride, silicon dioxide, aluminum oxide, magnesium oxide and hafnium dioxide, with a thickness of 10-100 nm.
5. A GaN HEMT device according to claim 1, characterized in that, The gate (100) is one or more of titanium, titanium nitride, aluminum and copper, with a thickness of 200-1000 nm; the gate (100) extends along the upper surface of the gate dielectric layer (90) to both sides of the device, wherein the width of the portion extending towards the source (61) is 0.2-2 μm, and the width of the portion extending towards the drain (62) is 0.2-10 μm, and the extended portion of the gate (100) is used as a metal field plate to control the electric field distribution of the device drift region.
6. A GaN HEMT device according to claim 1, characterized in that, The first dielectric layer (50) is one of silicon nitride and silicon dioxide, with a thickness of 10-300 nm, and the second dielectric layer (70) is one of silicon nitride and silicon dioxide, with a thickness of 10-200 nm.
7. A GaN HEMT device according to claim 1, characterized in that, The width of the portion of the source (61) and drain (62) extending to both sides along the transverse direction of the device is 0.2-2μm.
8. A method for manufacturing a GaN HEMT device, used in the GaN HEMT device as described in any one of claims 1-7, characterized in that, Includes the following steps: Step 1: Epitaxially grow buffer layer (20), first channel layer (30), first barrier layer (40), second channel layer (31), second barrier layer (41), third channel layer (32), third barrier layer (42), fourth channel layer (33), and fourth barrier layer (43) sequentially on the substrate (10). Step 2: Deposit the first dielectric layer (50); Step 3: Use wet or dry etching process to perform the first round of etching on the source (61) and drain (62) positions, completely etching the corresponding first dielectric layer (50). On this basis, use dry etching process to perform the second round of etching on the multi-channel layer at the source (61) and drain (62) positions. The etching depth must reach at least the lower interface of the first barrier layer (40). Then, use vapor deposition or sputtering to grow the source (61) and drain (62) metals, and perform high-temperature rapid annealing in nitrogen or vacuum atmosphere to form N-type ohmic contacts between the source (61) and drain (62) and the multiple two-dimensional electron gas channels on the sidewall. Step 4: Deposit the second dielectric layer (70); Step 5: Use wet or dry etching process to perform the first round of etching on the gate trench location, completely corresponding the first dielectric layer (50) and the second dielectric layer (70). On this basis, use dry etching process to perform the second round of etching on the multi-channel layer at the gate trench location. The etching depth must reach at least the lower interface of the first barrier layer (40) so that multiple two-dimensional electron gas channels are completely cut off. Step 6: An n-type GaN intermediate layer (80) is grown using secondary epitaxial technology. Based on this, the n-type GaN intermediate layer (80) outside the gate region is etched and removed using dry etching. Step 7: Deposit the gate dielectric layer (90), and on this basis, grow the gate (100) by means of evaporation or sputtering.