Radiation-reinforced depletion type MOSFET structure

Abstract

The invention provides a depletion type metal-oxide-semiconductor field effect transistor (MOSFET) structure with radiation hardening. According to the invention, a traditional polysilicon gate is improved into a separated gate structure; p well buffer layers are introduced below the P well regions on the left side and the right side respectively; and an N-type doped slowly-changing region is introduced between the N + substrate and the N-drift region. According to the invention, the N-type doped slowly-varying region can effectively optimize the longitudinal electric field distribution in the device, alleviate the peak electric field, and inhibit the avalanche breakdown caused by collision ionization, thereby comprehensively improving the single particle resistance of the device; the separation gate structure can effectively prevent a large number of holes from accumulating at the bottom of the central gate oxide layer after heavy ions are incident, and restrain the concentration of an electric field in the gate oxide layer, so that the single event gate penetration (SEGR) resistance of the depletion type MOSFET is remarkably improved; besides, the P-well buffer layer helps to accelerate extraction of transient holes generated by bombardment of radiation particles in the device body, enables the transient holes to flow out of the body rapidly, inhibits starting of a parasitic transistor, and has a good inhibition effect on single event burnout (SEB).

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a radiation-hardened depletion-type MOSFET structure. Background Technology

[0002] In aerospace applications, depletion-type MOSFETs are bombarded by high-energy radiation particles, making them susceptible to single-event effects, namely single-event burn-out (SEB) and single-event gate breakdown (SEGR). SEB is primarily triggered by the conduction of parasitic bipolar transistors. High-energy particles entering the depletion-type MOSFET ionize a large number of transient electron-hole pairs. As these holes drift towards the source and P-well regions, the bulk resistance generates a lateral voltage drop. When this voltage drop exceeds the forward conduction threshold of the source-bulk junction, the parasitic NPN transistor is triggered, leading to severe avalanche breakdown and localized thermal runaway, ultimately resulting in complete device burn-out. SEGR, on the other hand, originates from the concentration of transient electric fields at the bottom of the gate. In traditional depletion-type MOSFET structures, the gate oxide layer continuously spans the central drift region. The large number of holes generated by heavy-ion bombardment accumulates beneath the gate oxide layer as they drift towards the surface, causing a sharp increase in the transient electric field at this location. Once this field exceeds the critical breakdown field strength of the insulating dielectric, a permanent physical short circuit occurs at the gate. Currently, the radiation effect of depletion-type MOSFETs is a major challenge they face in aerospace applications. Summary of the Invention

[0003] To address the problems associated with traditional depletion-mode MOSFETs, this invention proposes a radiation-hardened depletion-mode MOSFET structure. The technical problem solved by this invention is achieved through the following technical solution:

[0004] One embodiment of the present invention provides a radiation-hardened depletion-mode MOSFET structure, comprising:

[0005] N+ substrate region (1);

[0006] The FS gradually varying field cutoff layer (2) is located on the upper surface of the N+ substrate region (1);

[0007] The N-drift region (3) is located on the upper surface of the FS gradually changing field cutoff layer (2);

[0008] The P-well buffer layer is divided into two parts: the left P-well buffer layer (4-1) and the right P-well buffer layer (4-2), which are embedded inside the N-drift region (3);

[0009] The P-well is divided into two parts: the left P-well region (5-1) and the right P-well region (5-2), which are located on the upper surfaces of the left P-well buffer layer (4-1) and the right P-well buffer layer (4-3), respectively.

[0010] The P+ region is divided into two parts: the left P+ region (6-1) and the right P+ region (6-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively.

[0011] The N+ source region is divided into two parts: the left N+ source region (7-1) and the right N+ source region (7-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively, and on the sides of the left P+ region (6-1) and the right P+ region (6-2).

[0012] The N region is divided into two parts: the left N region (8-1) and the right N region (8-2), which are located above the left P well (5-1) and the right P well (5-2), respectively, and on the sides of the left N+ source region (7-1) and the right N+ source region (7-2).

[0013] The gate oxide layer is divided into two parts: the left gate oxide layer (9-1) and the right gate oxide layer (9-2), which are located on the upper surface of the N-drift region (3), and there is a certain interval between the left gate oxide layer (7-1) and the right gate oxide layer (7-2);

[0014] The polysilicon gate is divided into two parts: a left polysilicon gate (10-1) and a right gate (10-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively.

[0015] The isolation oxide layer is divided into two parts: a left isolation oxide layer (11-1) and a right isolation oxide layer (11-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively.

[0016] The source metal (12) is located on the upper surface of the N-drift region (3), the left P+ region (6-1), the right P+ region (6-2), part of the left N+ source region (7-1), part of the right N+ source region (7-2), the left isolation oxide layer (11-1), the right isolation oxide layer (11-2), and both sides of the left gate oxide layer (9-1) and the right gate oxide layer (9-2).

[0017] Preferably, the gate oxide layer is SiO2 or a high-k insulating dielectric.

[0018] Preferably, the insulating oxide layer is SiO2 or a high-K insulating medium.

[0019] Preferably, the source metal is aluminum.

[0020] Preferably, the polysilicon gate is N-type doped, the doping element is phosphorus, and the doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 .

[0021] Preferably, the N+ substrate region is N-type doped, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0022] Preferably, the FS slowly varying field cutoff region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 15 ~1×10 16 cm -3 The thickness is 1~5μm.

[0023] Preferably, the N-drift region is doped using N-type epitaxial doping, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 13 ~1×10 15 cm -3 The thickness is 100~500μm.

[0024] Preferably, the left-side P-well buffer layer is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 1~5μm.

[0025] Preferably, the right-side P-well buffer layer is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 1~5μm.

[0026] Preferably, the left-side P-well is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 17 ~9×10 17 cm -3 The thickness is 1~45μm.

[0027] Preferably, the right-side P-well is p-type doped, with aluminum or boron as the doping element, and a doping concentration of 1×10⁻⁶. 17 ~9×10 17 cm -3 The thickness is 1~45μm.

[0028] Preferably, the left-side P+ region is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0029] Preferably, the right-side P+ region is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0030] Preferably, the left-side N+ source region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0031] Preferably, the right-side N+ source region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0032] Preferably, the left-side N-region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 0.5~2μm.

[0033] Preferably, the right-side N-region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 0.5~2μm.

[0034] Beneficial effects

[0035] This invention proposes a radiation-hardened depletion-mode MOSFET structure. When bombarded by radiated particles, the introduction of a slowly varying field-stop layer (FS) effectively modulates the longitudinal electric field distribution within the device, smoothing the transient peak electric field near the high-low junction and suppressing avalanche breakdown caused by impact ionization. This, in turn, hinders the positive feedback effect formed by internal avalanche breakdown and parasitic transistor conduction, ultimately significantly improving the depletion-mode MOSFET structure's resistance to single-particle burn-out. Furthermore, the separated gate structure allows the central drift region of the device to be directly adjacent to the upper dielectric layer, preventing a large number of holes from accumulating in the vulnerable central region after heavy ion injection. The significant accumulation at the bottom of the gate oxide layer effectively suppresses the concentration of the electric field in the sensitive gate oxide region, greatly improving the single-event gate-breakdown resistance of the depletion-mode MOSFET structure. Furthermore, the introduction of P-well buffer layers beneath the left and right P-well regions helps provide a discharge path for transient single-event charges, accelerating the extraction of holes generated by radiation particle bombardment within the device, allowing them to flow out rapidly, significantly reducing the base voltage drop, and overall reducing the impact of radiation particles on charge carriers within the device. Therefore, it effectively suppresses both single-event burn-out and single-event gate-breakdown. In summary, the depletion-mode MOSFET structure of this invention exhibits excellent radiation resistance. Attached Figure Description

[0036] Figure 1 This invention proposes a radiation-hardened depletion MOSFET structure.

[0037] Figure 2 It is a traditional depletion-type MOSFET structure. Detailed Implementation

[0038] The principles and features of the present invention are described in conjunction with the accompanying drawings. The examples given are for illustrative purposes only and are not intended to limit the scope of the invention.

[0039] Example 1

[0040] One embodiment of the present invention provides a radiation-hardened depletion-mode MOSFET structure, comprising:

[0041] N+ substrate region (1);

[0042] The FS gradually varying field cutoff layer (2) is located on the upper surface of the N+ substrate region (1);

[0043] The N-drift region (3) is located on the upper surface of the FS gradually changing field cutoff layer (2);

[0044] The P-well buffer layer is divided into two parts: the left P-well buffer layer (4-1) and the right P-well buffer layer (4-2), which are embedded inside the N-drift region (3);

[0045] The P-well is divided into two parts: the left P-well region (5-1) and the right P-well region (5-2), which are located on the upper surfaces of the left P-well buffer layer (4-1) and the right P-well buffer layer (4-3), respectively.

[0046] The P+ region is divided into two parts: the left P+ region (6-1) and the right P+ region (6-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively.

[0047] The N+ source region is divided into two parts: the left N+ source region (7-1) and the right N+ source region (7-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively, and on the sides of the left P+ region (6-1) and the right P+ region (6-2).

[0048] The N region is divided into two parts: the left N region (8-1) and the right N region (8-2), which are located above the left P well (5-1) and the right P well (5-2), respectively, and on the sides of the left N+ source region (7-1) and the right N+ source region (7-2).

[0049] The gate oxide layer is divided into two parts: the left gate oxide layer (9-1) and the right gate oxide layer (9-2), which are located on the upper surface of the N-drift region (3), and there is a certain interval between the left gate oxide layer (7-1) and the right gate oxide layer (7-2);

[0050] The polysilicon gate is divided into two parts: a left polysilicon gate (10-1) and a right gate (10-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively.

[0051] The isolation oxide layer is divided into two parts: a left isolation oxide layer (11-1) and a right isolation oxide layer (11-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively.

[0052] The source metal (12) is located on the upper surface of the N-drift region (3), the left P+ region (6-1), the right P+ region (6-2), part of the left N+ source region (7-1), part of the right N+ source region (7-2), the left isolation oxide layer (11-1), the right isolation oxide layer (11-2), and both sides of the left gate oxide layer (9-1) and the right gate oxide layer (9-2).

[0053] Preferably, the gate oxide layer is SiO2 or a high-k insulating dielectric.

[0054] Preferably, the insulating oxide layer is SiO2 or a high-K insulating medium.

[0055] Preferably, the source metal is aluminum.

[0056] Preferably, the polysilicon gate is N-type doped, the doping element is phosphorus, and the doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 .

[0057] Preferably, the N+ substrate region is N-type doped, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0058] Preferably, the FS slowly varying field cutoff region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 15 ~1×10 16 cm -3 The thickness is 1~5μm.

[0059] Preferably, the N-drift region is doped using N-type epitaxial doping, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 13 ~1×10 15 cm -3 The thickness is 100~500μm.

[0060] Preferably, the left-side P-well buffer layer is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 1~5μm.

[0061] Preferably, the right-side P-well buffer layer is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 1~5μm.

[0062] Preferably, the left-side P-well is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 17 ~9×10 17 cm -3 The thickness is 1~45μm.

[0063] Preferably, the right-side P-well is p-type doped, with aluminum or boron as the doping element, and a doping concentration of 1×10⁻⁶. 17 ~9×10 17 cm -3 The thickness is 1~45μm.

[0064] Preferably, the left-side P+ region is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0065] Preferably, the right-side P+ region is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0066] Preferably, the left-side N+ source region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0067] Preferably, the right-side N+ source region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.5~2μm.

[0068] Preferably, the left-side N-region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 0.5~2μm.

[0069] Preferably, the right-side N-region is doped with N-type doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 0.5~2μm.

[0070] Compared to traditional structures (such as) Figure 2 The split gate structure proposed in this embodiment of the invention, consisting of a FS gradually varying field cutoff layer (2), a left P-well buffer layer (4-1), a right P-well buffer layer (4-2), a left polysilicon gate (10-1), and a right polysilicon gate (10-2), is as follows (e.g. Figure 1The introduction of the FS gradual field cutoff layer (2) can effectively improve the longitudinal electric field distribution inside the depletion MOSFET, effectively suppress the avalanche breakdown of the high and low junctions composed of the N-drift region (3) and the FS gradual field cutoff layer (2), thereby enhancing the device's resistance to single-event burnout; changing the traditional gate to a split gate (10-1) and (10-2) can effectively suppress the concentration of electric field in the gate oxide layer (9-1) and (9-2), and improve the resistance to single-event gate breakdown; after introducing the P-well buffer layer (4-1) and (4-2), when high-energy radiation particles bombard the depletion MOSFET, a large number of holes will be generated along the particle trajectory. These deep structures provide a low-impedance discharge path for transient holes, so that the holes are quickly extracted and flow out of the device, which greatly reduces the base voltage drop that triggers the conduction of parasitic transistors, reduces the avalanche positive feedback effect caused by single-event bombardment, and thus significantly improves the overall radiation resistance of the device. In summary, the depletion-type MOSFET structure of the present invention has good radiation resistance performance, with a radiation resistance performance improvement of 20%-25%.

[0071] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating that the indicated technical feature implicitly includes one or more of that feature.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A radiation-hardened depletion-mode MOSFET structure, characterized in that, include: N+ substrate region (1); The FS gradually varying field cutoff layer (2) is located on the upper surface of the N+ substrate region (1); The N-drift region (3) is located on the upper surface of the FS gradually changing field cutoff layer (2); The P-well buffer layer is divided into two parts: the left P-well buffer layer (4-1) and the right P-well buffer layer (4-2), which are embedded inside the N-drift region (3); The P-well is divided into two parts: the left P-well region (5-1) and the right P-well region (5-2), which are located on the upper surfaces of the left P-well buffer layer (4-1) and the right P-well buffer layer (4-3), respectively. The P+ region is divided into two parts: the left P+ region (6-1) and the right P+ region (6-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively. The N+ source region is divided into two parts: the left N+ source region (7-1) and the right N+ source region (7-2), which are located above the left P-well (5-1) and the right P-well (5-2), respectively, and on the sides of the left P+ region (6-1) and the right P+ region (6-2). The N region is divided into two parts: the left N region (8-1) and the right N region (8-2), which are located above the left P well (5-1) and the right P well (5-2), respectively, and on the sides of the left N+ source region (7-1) and the right N+ source region (7-2). The gate oxide layer is divided into two parts: the left gate oxide layer (9-1) and the right gate oxide layer (9-2), which are located on the upper surface of the N-drift region (3), and there is a certain interval between the left gate oxide layer (7-1) and the right gate oxide layer (7-2); The polysilicon gate is divided into two parts: a left polysilicon gate (10-1) and a right gate (10-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively. The isolation oxide layer is divided into two parts: a left isolation oxide layer (11-1) and a right isolation oxide layer (11-2), which are located on the upper surfaces of the left gate oxide layer (9-1) and the right gate oxide layer (9-2), respectively. The source metal (12) is located on the upper surface of the N-drift region (3), the left P+ region (6-1), the right P+ region (6-2), part of the left N+ source region (7-1), part of the right N+ source region (7-2), the left isolation oxide layer (11-1), the right isolation oxide layer (11-2), and both sides of the left gate oxide layer (9-1) and the right gate oxide layer (9-2).

2. The irradiation-hardened depletion-mode MOSFET structure according to claim 1, characterized in that, The FS slowly varying field cutoff layer is N-type doped with either nitrogen or phosphorus as the doping element, and the doping concentration is 1×10⁻⁶. 15 ~1×10 16 cm -3 The thickness is 1~5μm.

3. The irradiation-hardened depletion-mode MOSFET structure according to claim 1, characterized in that, The P-well buffer layer is p-type doped with aluminum or boron as the doping element, and the doping concentration is 1×10⁻⁶. 16 ~1×10 17 cm -3 The thickness is 1~5μm.

4. The irradiation-hardened depletion-mode MOSFET structure according to claim 1, characterized in that, The polysilicon gate is N-type doped with phosphorus as the dopant element, and the doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 .

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