Trench gate device and preparation method thereof

Abstract

The invention provides a trench gate device and a preparation method thereof, the trench gate device comprises a semiconductor layer, a trench gate structure, a first shielding layer, a second shielding layer, a source electrode, a gate electrode and a drain electrode, the semiconductor layer comprises a drift region, a body region located on the upper surface layer of the drift region and a plurality of source regions arranged at intervals and located on the upper surface layer of the body region; the trench gate structure penetrates through the source region and the body region, and the bottom of the trench gate structure extends into the drift region; the first shielding layer is located in the drift region under the trench gate structure and is adjacent to the bottom of the trench gate structure; the second shielding layer is located in the semiconductor layer on the same side of each trench gate structure, the top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer; the source electrode, the grid electrode and the drain electrode are electrically connected with the corresponding areas respectively. The first shielding layer is arranged at the bottom of the groove, and the second shielding layer is arranged in the semiconductor layer on the same side of each groove, so that the channel density and reliability of the device are improved, and the on resistance of the device is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a trench gate device and its fabrication method. Background Technology

[0002] With the continuous development of power metal-oxide-semiconductor field-effect transistors (MOS), the advantages of trench gates have become increasingly apparent, such as reducing JFET resistance, increasing cell density, and improving avalanche withstand capability. For low-voltage silicon-based power MOS or silicon carbide MOS, the channel resistance accounts for a large proportion of the total resistance, making the application of trench gates even more necessary to reduce the channel resistance and thus the overall device resistance. In trench-gate MOS, a high electric field will appear at the bottom corner of the trench gate when the device is under breakdown voltage, causing the gate oxide layer at the bottom corner of the trench gate to be easily broken down, affecting the reliability of the device. To avoid premature breakdown of the gate oxide layer at the bottom corner of the trench gate, P-type regions are usually introduced on both sides of the trench gate to appropriately reduce the electric field strength at the bottom of the trench gate during blocking. However, the improvement effect on the electric field strength is limited, and the Miller capacitance of this device structure is relatively large. Another method involves introducing a heavily doped P-type region at the bottom of the trench gate. This heavily doped P-type region can withstand the voltage during blocking, thereby effectively protecting the gate oxide layer at the bottom of the trench gate. However, the P-type region at the bottom of the trench gate is floating, and the hole carriers in this region cannot be effectively replenished during switching, which leads to an increase in the dynamic on-resistance of the device.

[0003] Furthermore, as the switching frequency and speed of power MOSFETs increase, a high dv / dt ratio is achieved. A high dv / dt ratio can cause false turn-on of the power MOSFET, affecting device reliability. This is typically addressed by reducing the gate-drain parasitic capacitance C in the device. gd With gate-source parasitic capacitance C gs The ratio of [unspecified value] is used to reduce false turn-on. Currently, a semi-enclosed trench power MOS structure is commonly used, so that half of the channel in the device does not participate in conduction, thereby reducing the C [unspecified value] in the device. gd / C gs The ratio is increased, but this reduces the channel density in the device, resulting in a higher on-resistance. Alternatively, a dual-trench MOS structure can be used to reduce the C content in the device. gd / C gs The ratio of this structure to the source trench requires additional photolithography to etch the source trench, and its channel density is relatively low. It is also difficult to further increase the channel density, which in turn leads to a relatively high on-resistance of this device.

[0004] Therefore, there is an urgent need to find a trench gate device that can reduce the on-resistance of the device while improving the conductive channel density and reliability of the device. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate device and its fabrication method, which solves the problems of high on-resistance, low channel density and poor reliability of power MOSFET devices in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a trench gate device, comprising:

[0007] The semiconductor layer includes a source region of a first conductivity type, a drift region of a first conductivity type, and a body region of a second conductivity type. The body region is located on the upper surface of the drift region, and a plurality of spaced-apart source regions are located on the upper surface of the body region.

[0008] A trench grid structure extends through the source region and the body region, with its bottom extending into the drift region;

[0009] The second conductivity type first shielding layer is located in the drift region directly below the trench gate structure and adjacent to the bottom of the trench gate structure;

[0010] A second shielding layer of a second conductivity type is located in the semiconductor layer on the same side of each of the trench gate structures. The top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer.

[0011] The semiconductor layer comprises a source, a gate, and a drain. The source is electrically connected to the source region, the gate is electrically connected to the trench gate structure, and the drain is electrically connected to the bottom surface of the semiconductor layer.

[0012] Optionally, the semiconductor layer further includes a substrate of a first conductivity type, the drift region is stacked on the upper surface of the substrate, and the drain is electrically connected to the bottom surface of the substrate.

[0013] Optionally, the second shielding layer is adjacent to the trench grid structure near the sidewall of the trench grid structure.

[0014] Optionally, the doping concentration of the second shielding layer is lower than the doping concentration of the body region.

[0015] Optionally, the second shielding layer further includes a first conductivity type injection region, which is located on the surface of the second shielding layer near the trench gate structure, and the sidewall of the injection region near the trench gate structure is adjacent to the trench gate structure, and the top of the injection region is adjacent to the bottom surface of the source region.

[0016] Optionally, the drift region further includes a first region and a second region stacked sequentially, wherein the doping concentration of the second region is not less than the doping concentration of the first region, and the bottom surface of the first shielding layer is flush with the bottom surface of the second region.

[0017] Optionally, the semiconductor layer further includes a second conductivity type contact region, the contact region being located on the upper surface of the body region between two adjacent source regions, and the contact region being adjacent to the source regions on both sides of the source region arrangement direction.

[0018] Optionally, the trench gate structure includes a trench, a gate dielectric layer, and a gate conductive layer. The trench penetrates the body region and extends to the drift region. The gate dielectric layer covers the inner wall and bottom surface of the trench. The gate conductive layer fills the trench. The gate dielectric layer wraps the sidewalls and bottom surface of the gate conductive layer. The gate is electrically connected to the gate conductive layer.

[0019] Optionally, the trench gate device further includes an interlayer dielectric layer, the source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the trench gate structure.

[0020] This invention also provides a method for fabricating a trench gate device, comprising the following steps:

[0021] A semiconductor layer is provided, the semiconductor layer including a first conductivity type source region, a first conductivity type drift region and a second conductivity type body region, the body region being located on the upper surface of the drift region, and a plurality of spaced-apart source regions being located on the upper surface of the body region;

[0022] A trench is formed that runs through the source region and the body region and extends to the drift region at its bottom;

[0023] A first shielding layer of a second conductivity type is formed in the drift region located directly below the trench and adjacent to the bottom of the trench;

[0024] A second shielding layer of a second conductivity type is formed in a semiconductor layer on the same side of each of the trenches, the top of the second shielding layer being adjacent to the source region, and the bottom of the first shielding layer being adjacent to the second shielding layer;

[0025] A trench grid structure is formed based on the trenches;

[0026] A source electrode electrically connected to the source region, a gate electrode electrically connected to the trench gate structure, and a drain electrode electrically connected to the bottom surface of the semiconductor layer are respectively formed.

[0027] As described above, the trench gate device and its fabrication method of the present invention form a first shielding layer in the drift region at the bottom of the trench, and a second shielding layer with its bottom adjacent to the first shielding layer in the semiconductor layer on the same side of each trench, with the top of the second shielding layer adjacent to the source region. The second shielding layer is adjacent to the trench gate structure near the sidewall of the trench gate structure, thereby forming a conductive channel controlled by the gate conductive layer, which increases the conductive channel density in the device and thus reduces the on-resistance of the device. By connecting the second shielding layer, the first shielding layer is electrically connected to the source, and a superjunction is formed using a simple process, which further reduces the on-resistance of the device and improves the protection strength of the gate dielectric layer at the bottom of the trench gate structure, thereby increasing the withstand voltage of the device. By combining the first shielding layer and the second shielding layer, the cell size of the device can be further reduced, thereby further increasing the conductive channel density of the device and reducing the on-resistance of the device. By adjusting the size of the overlapping area between the trench gate structure and the drift region, the gate-drain parasitic capacitance C of the device can be adjusted. gd With gate-source parasitic capacitance C gs The ratio between these two values ​​increases the switching speed of the device, reduces the risk of accidental activation during the switching process, and improves the reliability of the device, thus having high industrial application value. Attached Figure Description

[0028] Figure 1 The diagram shown is a cross-sectional structural schematic of the trench gate device of the present invention.

[0029] Figure 2 This is a schematic diagram of another cross-sectional structure of the trench gate device of the present invention.

[0030] Figure 3 The diagram shown is a third cross-sectional view of the trench gate device of the present invention.

[0031] Figure 4 The diagram shown is a fourth cross-sectional view of the trench gate device of the present invention.

[0032] Figure 5 The diagram shows a process flow chart of the method for fabricating the trench gate device of the present invention.

[0033] Figure 6 The diagram shows a cross-sectional view of the semiconductor layer in the method for fabricating the trench gate device of the present invention.

[0034] Figure 7 The diagram shows a cross-sectional structure after trench formation in the fabrication method of the trench gate device of the present invention.

[0035] Figure 8 The diagram shows a cross-sectional structure after forming the first and second shielding layers in the method for fabricating the trench gate device of the present invention.

[0036] Figure 9 The diagram shown is a cross-sectional view of the trench gate structure after it has been formed, according to the method for fabricating the trench gate device of the present invention.

[0037] Figure 10 The diagram shown is a cross-sectional view of the trench gate device fabrication method of the present invention after the formation of the interlayer dielectric layer.

[0038] Figure 11 The diagram shown is a cross-sectional view of the trench gate device fabrication method of the present invention after the source electrode is formed.

[0039] Explanation of icon numbers

[0040] 1 Semiconductor layer

[0041] 11 Substrate

[0042] 12 Drift Zones

[0043] 121 First District

[0044] 122 Second District

[0045] 13 body areas

[0046] 14 source regions

[0047] 15 Contact Area

[0048] 2. Groove grid structure

[0049] 21. Trench

[0050] 22 Gate dielectric layer

[0051] 23 Gate conductive layer

[0052] 3 First shielding layer

[0053] 31 Second Shielding Layer

[0054] 32 Injection Zone

[0055] 4 Interlayer dielectric layer

[0056] 5 Source poles

[0057] 6 Drain Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please see Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides a trench gate device, such as Figures 1 to 4 The diagrams shown illustrate several structural designs of the trench gate device, including a semiconductor layer 1, a trench gate structure 2, a first shielding layer 3, a second shielding layer 31, a source electrode 5, a gate electrode 6, and a drain electrode 6. The semiconductor layer 1 includes a source region 14 of a first conductivity type, a drift region 12 of a first conductivity type, and a body region 13 of a second conductivity type. The body region 13 is located on the upper surface of the drift region 12, and multiple spaced source regions 14 are located on the upper surface of the body region 13. The trench gate structure 2 penetrates both the source region 14 and the body region 1. 3. The bottom extends into the drift region 12; the first shielding layer 3 is located in the drift region 12 directly below the trench gate structure 2 and is adjacent to the bottom of the trench gate structure 2; the second shielding layer 31 is located in the semiconductor layer 1 on the same side of each trench gate structure 2, the top of the second shielding layer 31 is adjacent to the source region 14, and the bottom of the second shielding layer 31 is adjacent to the first shielding layer 3; the source 5 is electrically connected to the source region 14, the gate is electrically connected to the trench gate structure 2, and the drain 6 is electrically connected to the bottom surface of the semiconductor layer 1.

[0062] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0063] Specifically, semiconductor layer 1 is usually the structure after the source region 14 of the device is formed. The position of the doped region, the doping condition of the doped region and the distribution of the doped region in the film layer can be selected according to the actual situation.

[0064] As an example, the semiconductor layer 1 also includes a first conductivity type substrate 11, a drift region 12 stacked on the upper surface of the substrate, and a drain 6 electrically connected to the bottom surface of the substrate 11.

[0065] Specifically, the substrate 11 is usually the process platform for fabricating the drift region 12 stacked on its upper surface. At the same time, the bottom surface of the substrate 11 also serves as the part electrically connected to the drain 6. Since the substrate 11 and the drain 6 are usually in an ohmic contact, the substrate needs to be heavily doped. While ensuring device performance, the thickness, size, thickness and doping concentration of the substrate 11 can be selected according to the actual situation.

[0066] Specifically, the substrate 11 may be made of silicon, silicon carbide, silicon germanium, gallium nitride, diamond, or other suitable semiconductor materials. Preferably, a silicon wafer is used as the substrate 11.

[0067] Specifically, the drift region 12 is usually used to ensure the withstand voltage of the device. Its doping concentration is generally lower than that of the substrate 11. While ensuring device performance, the thickness and doping concentration of the drift region 12 can be selected according to the actual situation.

[0068] Specifically, while ensuring device performance, the doping concentration, thickness, size, and shape of the body region 13 can be selected according to the actual situation.

[0069] Specifically, the contact type between source region 14 and source electrode 5 is an ohmic contact. The thickness, size, shape, and doping concentration of source region 14 can be selected according to actual conditions. On the upper surface of the body region 13 between two adjacent trench gate structures 2, the distance between the two source regions 14 can be selected according to actual conditions. Here, the thickness refers to the distance between the upper and lower surfaces of source region 14.

[0070] As an example, the trench gate structure 2 includes a trench 21, a gate dielectric layer 22, and a gate conductive layer 23. The trench 21 penetrates the body region 13 and extends to the drift region 12. The gate dielectric layer 22 covers the inner wall and bottom surface of the trench 21. The gate conductive layer 23 fills the trench 21. The gate dielectric layer 22 wraps the sidewall and bottom surface of the gate conductive layer 23. The gate is electrically connected to the gate conductive layer 23.

[0071] Specifically, while ensuring device performance, the opening size and shape of the trench 21 can be selected according to the actual situation; the distance between the bottom surface of the trench 21 and the bottom surface of the body region 13 can be selected according to the actual situation; the distance between two adjacent trenches 21 can be selected according to the actual situation; and the thickness of the gate dielectric layer 22 can be selected according to the actual situation.

[0072] Specifically, the material of the gate dielectric layer 22 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0073] Specifically, the bottom surface of the gate conductive layer 23 is usually lower than the bottom surface of the body region 13, and the upper surface of the gate conductive layer 23 is flush with or slightly lower than the upper surface of the source region 14 (i.e., the upper surface of the semiconductor layer 1), so as to facilitate the formation of a conductive channel in the body region 13 adjacent to the trench gate structure 2 by controlling the gate conductive layer 23. The material of the gate conductive layer 23 includes polysilicon or other suitable conductive materials.

[0074] It should be noted that the first shielding layer 3 is usually used to protect the heavily doped region at the bottom of the trench gate structure 2, and the second shielding layer 31 is used to connect the first shielding layer 3 and the body region 13. During the blocking process, as the voltage between the source 5 and the drain 6 increases, the drift region 12 between the adjacent but not adjacent first shielding layer 3 and second shielding layer 31 is gradually depleted. After the drift region 12 between the first shielding layer 3 and the second shielding layer 31 is depleted, as the voltage between the source 5 and the drain 6 further increases, the voltage will be borne by the first shielding layer 3 and the drift region 12 below it, which avoids the premature breakdown of the gate dielectric layer 22 at the bottom of the trench gate structure 2, thereby effectively ensuring the safety of the gate dielectric layer 22 at the bottom of the trench gate structure 2 and improving the withstand voltage capability of the device.

[0075] Specifically, while ensuring device performance, the doping concentration of the first shielding layer 3 can be selected according to the actual situation.

[0076] As an example, the drift region 12 also includes a first region 121 and a second region 122 stacked sequentially, wherein the doping concentration of the second region 122 is not less than the doping concentration of the first region 121, and the bottom surface of the first shielding layer 3 is flush with the bottom surface of the second region 122. Figure 2 and Figure 4 As shown.

[0077] Specifically, since the first shielding layer 3 is usually a heavily doped region, by making the bottom surface of the first shielding layer 3 flush with the bottom surface of the second region 122, a thicker first shielding layer 3 is formed, so as to further enhance the protection strength of the first shielding layer 3 for the gate dielectric layer 22 at the bottom of the trench gate structure 2, while ensuring that the doping concentration of the second region 122 is not lower than the doping concentration of the first region 121, so that the charge in the drift region 12 meets the balance condition.

[0078] As an example, the second shielding layer 31 is adjacent to the trench grid structure 2 near its sidewall, such as... Figure 1 and Figure 2 As shown.

[0079] Specifically, when the second shielding layer 31 is adjacent to the sidewall of the trench gate structure 2, the drift region 12, the body region 13 and the source region 14 adjacent to the trench gate structure 2 on the opposite sides of the trench gate structure 2 form a conductive channel controlled by the trench gate structure 2. The drift region 12, the first shielding layer 3, the second shielding layer 31 and the source region 14 form another conductive channel controlled by the trench gate structure 2, thus increasing the density of conductive channels in the device.

[0080] As an example, the doping concentration of the second shielding layer 31 is less than the doping concentration of the body region 13.

[0081] Specifically, when the second shielding layer 31 is adjacent to the trench gate structure 2 near the sidewall of the trench gate structure 2, the channel resistance of the conductive channel formed by the drift region 12, the first shielding layer 3, the second shielding layer 31 and the source region 14 can be reduced by making the doping concentration of the second shielding layer 31 less than that of the body region 13, thereby reducing the on-resistance of the device.

[0082] As an example, the second shielding layer 31 also includes a first conductivity type injection region 32. The injection region 32 is located on the surface of the second shielding layer 31 near the trench gate structure 2, and the sidewall of the injection region 32 near the trench gate structure 2 is adjacent to the trench gate structure 2. The top of the injection region 32 is adjacent to the bottom surface of the source region 14. Figure 3 and Figure 4 As shown.

[0083] Specifically, the second shielding layer 31 has an injection region 32 adjacent to the trench gate structure 2 on its sidewall. The bottom surface of the injection region 32 can be lower than the upper surface of the first shielding layer 3, i.e., the bottom of the injection region 32 is adjacent to the bottom of the first shielding layer 3, or it can be higher than the upper surface of the first shielding layer 3. When the bottom of the injection region 32 is adjacent to the first shielding layer 3, the drift region 12, the first shielding layer 3, the injection region 32 and the source region 14 constitute the conductive channel of the device. When the bottom surface of the injection region 32 is higher than the bottom surface of the first shielding layer 3, the drift region 12, the first shielding layer 3, the second shielding layer 31, the injection region 32 and the source region 14 constitute the conductive channel of the device.

[0084] Specifically, by setting the injection region 32, the channel resistance of the conductive channel containing the first shielding layer 3 and the injection region 32 (the conductive channel composed of the drift region 12, the first shielding layer 3, the second shielding layer 31, the injection region 32, and the source region 14, or the conductive channel composed of the drift region 12, the first shielding layer 3, the injection region, and the source region 14) can be reduced, thereby reducing the conductive resistance of the device. Preferably, the bottom surface of the injection region 32 is flush with the upper surface of the first shielding layer 3.

[0085] It should be noted that the injection region 32 is typically thin, making it prone to complete depletion. Therefore, the gate conductive layer 23, the first shielding layer 3, and the injection region 32 together constitute the gate-source parasitic capacitance C of the device. gs The gate-drain parasitic capacitance C of the device gd The size of the adjacent region between the trench gate structure 2 and the drift region 12 determines the reduction of the gate-drain parasitic capacitance C in the device. gd With gate-source parasitic capacitance C gs The ratio between these values ​​improves the switching speed of the device while effectively reducing the risk of accidental activation. Here, the thickness of the injection region 32 refers to the distance between the sidewall of the injection region 32 adjacent to the trench gate structure 2 and the sidewall away from the trench gate structure 2.

[0086] Specifically, the implantation region 32 can also be a heavily doped region, meaning that the implantation region 32 does not need to be in a completely depleted state. However, at this time, the doping concentration of the second shielding layer 31 also needs to be high so that it will not be completely depleted, thereby reducing the channel resistance of the conductive channel formed by the source region 14, the implantation region 32, the second shielding layer 31, and the first shielding layer 3.

[0087] As an example, the semiconductor layer 1 also includes a second conductivity type contact region 15, which is located on the upper surface of the body region 13 between two adjacent source regions 14, and the contact region 15 is adjacent to the source regions 14 on both sides of the source region 14 in the arrangement direction of the source regions 14.

[0088] Specifically, the contact type between contact region 15 and source electrode 5 is an ohmic contact. While ensuring device performance, the size, shape, thickness, and doping concentration of contact region 15 can be selected according to actual conditions. In this embodiment, the thickness of contact region 15 is the same as the thickness of source region 14. Here, thickness refers to the distance between the upper and lower surfaces of source region 14 (or contact region 15).

[0089] Specifically, through the electrical connection between the contact area 15 and the source 5 of the device, the first shielding layer 3, the second shielding layer 31, and the body region 13 are indirectly electrically connected to the source 5 through the contact area 15. At this time, the first shielding layer 3, the second shielding layer 31, and the body region 13 form a superjunction with the drift region 12. When the device withstands voltage, the drift region 12 between two adjacent trench gate structures 2 (i.e., the drift region 12 between the first shielding layer 3 and the trench gate structure 2 above it and the second shielding layer 31 adjacent to the trench gate structure 2) is gradually depleted. After the drift region 12 in this region is depleted, since the source 5 is indirectly electrically connected to the first shielding layer 3, its voltage is completely borne by the first shielding layer 3 and the drift region 12 in contact with the first shielding layer 3, which further enhances the protection strength of the first shielding layer 3 for the gate dielectric layer 22 at the bottom of the trench gate structure 2, and does not increase the dynamic on-resistance of the device, thus improving the performance of the device.

[0090] Specifically, the contact type between the source region 14 and the source electrode 5 is an ohmic contact. While ensuring device performance, the size, thickness, shape and doping concentration of each source region 14 on both sides of the trench gate structure 2 can be selected according to the actual situation.

[0091] As an example, the trench gate device also includes an interlayer dielectric layer 4, with the source 5 penetrating through the interlayer dielectric layer 4 and electrically connected to the source region 14, and the gate penetrating through the interlayer dielectric layer 4 and electrically connected to the trench gate structure 2.

[0092] Specifically, the material of the interlayer dielectric layer 4 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0093] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 4 can be selected according to the actual situation.

[0094] Specifically, the interlayer dielectric layer 4 is also provided with source contact holes and gate contact holes. The source contact holes penetrate the interlayer dielectric layer 4 and expose the contact area 15 and the source area 14 on the bottom surface. The gate contact holes penetrate the interlayer dielectric layer 4 and expose the gate conductive layer 23 on the bottom surface. The source 5 fills the source contact holes to achieve electrical connection with the source area 14 and the contact area 15. The gate fills the gate contact holes to achieve electrical connection with the gate conductive layer 23.

[0095] Specifically, while ensuring device performance, the opening size and shape of the source contact hole can be selected according to the actual situation; the opening size and shape of the gate contact hole can also be selected according to the actual situation.

[0096] Specifically, the source electrode 5 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the gate electrode is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; and the drain electrode 6 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.

[0097] Specifically, by setting a first shielding layer 3 and a second shielding layer 31 in the device, the first shielding layer 3 is located in the drift region 12 at the bottom of the trench gate structure 2 and is adjacent to the bottom of the trench gate structure 2. The second shielding layer 31 is adjacent to the sidewall on the same side of each trench gate structure 2, and the top of the second shielding layer 31 is adjacent to the source region 14, and the bottom of the second shielding layer 31 is adjacent to the first shielding layer 3. The drift region 12, the first shielding layer 3, the second shielding layer 31 and the source region 14 constitute a conductive channel of the device, which increases the conductive channel density in the device and thereby reduces the on-resistance of the device.

[0098] Specifically, due to the arrangement of the first shielding layer 3 and the second shielding layer 31, the first shielding layer 3 is electrically connected to the source electrode 5 through the contact area 15, the body area 13 and the second shielding layer 31, which further enhances the protection strength of the first shielding layer 3 for the gate dielectric layer 22 at the bottom of the trench gate structure 2. This allows the hole carriers to be replenished in a timely and effective manner during the device switching process, thereby avoiding the problem of the first shielding layer 3 being floating, which would prevent the hole carriers from being effectively replenished during the device switching process and cause an increase in the dynamic on-resistance of the device. This reduces the on-resistance of the device.

[0099] Specifically, the combination of the first shielding layer 3 and the second shielding layer 31 facilitates further reduction of the cell size of the device, thereby further increasing the density of the conductive channel and reducing the on-resistance of the device.

[0100] Specifically, by setting the first shielding layer 3 and the second shielding layer 31, the gate-source parasitic capacitance C of the device is reduced. gs Increase, while the gate-drain parasitic capacitance C of the device increases. gd The relative reduction, in turn, lowers the gate-drain parasitic capacitance C. gd With gate-source parasitic capacitance C gs The ratio between these two values ​​increases the switching speed of the device, reduces the risk of accidental activation during the switching process, and improves the reliability of the device.

[0101] This embodiment of the trench gate device improves the device structure by providing a first shielding layer 3 at the bottom of the trench gate structure 2, and a second shielding layer 31 adjacent to the trench gate structure 2 on the same side. The bottom of the second shielding layer 31 is adjacent to the first shielding layer 3, and the top of the second shielding layer 31 is adjacent to the source region 14. This increases the conductive channel density in the device, reduces the on-resistance, and simultaneously reduces the gate-drain parasitic capacitance C. gd With gate-source parasitic capacitance C gs The ratio between these two layers increases the switching speed of the device, reduces the risk of accidental activation during switching, and improves the reliability of the device. Furthermore, the combination of the first shielding layer 3 and the second shielding layer 31 further reduces the cell size of the device, thereby further increasing the channel density and reducing the on-resistance.

[0102] Example 2

[0103] This embodiment also provides a method for fabricating a trench gate device, such as... Figure 5 The diagram shown is a process flow chart of the fabrication method of the trench gate device, including the following steps:

[0104] S1: A semiconductor layer is provided, the semiconductor layer including a first conductivity type source region, a first conductivity type drift region and a second conductivity type body region, the body region being located on the upper surface of the drift region, and a plurality of spaced-apart source regions being located on the upper surface of the body region;

[0105] S2: Form a trench that runs through the source region and the body region and extends to the drift region at the bottom;

[0106] S3: Form a first shielding layer of a second conductivity type located in the drift region directly below the trench and adjacent to the bottom of the trench;

[0107] S4: A second shielding layer of a second conductivity type is formed in the semiconductor layer on the same side of each of the trenches, the top of the second shielding layer is adjacent to the source region, and the bottom of the first shielding layer is adjacent to the second shielding layer;

[0108] S5: Form a trench grid structure based on the trench;

[0109] S6: Form a source electrode electrically connected to the source region, a gate electrode electrically connected to the trench gate structure, and a drain electrode electrically connected to the bottom surface of the semiconductor layer.

[0110] Please see Figures 6 to 7 The steps S1 and S2 are performed as follows: a semiconductor layer 1 is provided, the semiconductor layer 1 includes a first conductivity type source region 14, a first conductivity type drift region 12 and a second conductivity type body region 13, the body region 13 is located on the upper surface of the drift region 12, and a plurality of spaced source regions 14 are located on the upper surface of the body region 13; a trench 21 is formed that penetrates the source region 14 and the body region 13 and extends to the bottom of the drift region 12.

[0111] Specifically, such as Figure 6 The diagram shows a cross-sectional view of semiconductor layer 1. Semiconductor layer 1 also includes a first conductivity type substrate 11, a drift region 12 formed on the upper surface of substrate 11, and a body region 13 formed on the upper surface layer of drift region 12.

[0112] It should be noted that the methods for forming the drift region 12 on the upper surface of the substrate 11 typically include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the body region 13 on the upper surface layer of the drift region 12 include ion implantation or other suitable methods; and the methods for forming the source region 14 on the upper surface layer of the body region 13 include ion implantation or other suitable methods.

[0113] Specifically, forming the trench 21 includes the following steps: forming a patterned masking layer on the upper surface of the semiconductor layer 1; forming the trench 21 based on the patterned masking layer, wherein the trench 21 penetrates the source region 14 and the body region 13 and extends its bottom surface to a predetermined distance in the drift region 12.

[0114] Specifically, the masking layer is usually a photoresist layer, a hard mask layer, or a stacked structure of a hard mask layer and a photoresist layer. Preferably, a hard mask layer or a stacked structure of a hard mask layer and a photoresist layer is used as the masking layer to avoid the photoresist layer from directly contacting the semiconductor layer 1, which could easily cause contamination of the semiconductor layer 1 in the future.

[0115] Specifically, the formation of patterned masking layers is a commonly used photolithography process, which will not be elaborated here.

[0116] Specifically, such as Figure 7 The diagram shows a cross-sectional structure after the formation of trench 21. The method for forming trench 21 based on a patterned masking layer includes dry etching, wet etching, or other suitable methods. Preferably, a dry etching process is used to etch the semiconductor layer 1 to obtain trench 21 of a predetermined depth.

[0117] Please see Figure 8 Steps S3 and S4 are executed: a first shielding layer 3 of a second conductivity type is formed in the drift region 12 located directly below the trench 21 and adjacent to the bottom of the trench 21; a second shielding layer 31 of a second conductivity type is formed in the semiconductor layer 1 on the same side of each trench 21, the top of the second shielding layer 31 is adjacent to the source region 14, and the first shielding layer 3 is adjacent to the bottom of the second shielding layer 31.

[0118] Specifically, after the trench 21 is formed, a first shielding layer can be formed in the drift area 12 below the bottom of the trench 21 based on the shielding layer.

[0119] Specifically, methods for forming the first shielding layer include ion implantation or other suitable methods.

[0120] It should be noted that during the formation of the first shielding layer, the first shielding layer 3 of a preset depth (i.e., the first shielding layer 3 of a preset thickness) can be formed by ion implantation, or the first shielding layer 3 of a deeper depth (i.e., the first shielding layer 3 of a thicker thickness) can be formed by multiple high-energy implantations.

[0121] Specifically, the drift region 12 includes a first region 121 and a second region 122 stacked sequentially. When the thickness of the first shielding layer 3 is relatively thick, the bottom surface of the first shielding layer 3 is flush with the bottom surface of the second region 122. The doping concentration of the second region 122 is not less than the doping concentration of the first region 121 to ensure charge balance in the drift region 12. The thickness of the second region 122 can be selected according to the actual situation while ensuring device performance.

[0122] Specifically, the methods for forming the second shielding layer 31 include ion implantation or other suitable methods.

[0123] It should be noted that the second shielding layer 31 is usually formed based on the shielding layer and trench 21 and through sidewall injection. In the process of forming the second shielding layer 31, the morphology and doping concentration of the second shielding layer 31 can be controlled by controlling the angle, energy and dose of sidewall injection.

[0124] Specifically, a first conductivity type injection region 32 is also formed in the second shielding layer 31. The injection region 32 is located on the surface of the second shielding layer 31 near the sidewall of the trench 21, and the top of the injection region 32 is adjacent to the source region 14.

[0125] Specifically, the methods for forming the implantation region 32 include ion implantation or other suitable methods.

[0126] It should be noted that the implantation region 32 is usually formed based on the shielding layer and trench 21 and through sidewall implantation. During the implantation process, the morphology and doping concentration of the implantation region 32 can be controlled by controlling the angle, energy and dose of the sidewall implantation.

[0127] Specifically, by forming the injection region 32, the channel resistance of the conductive channel formed by the drift region 12, the first shielding layer 3, the second shielding layer 31, the injection region 32 and the source region 14 can be reduced, thereby further reducing the on-resistance of the device.

[0128] Please see Figures 9 to 11 Steps S5 and S6 are executed: a trench gate structure 2 is formed based on the trench 21; a source 5 electrically connected to the source region 14, a gate electrically connected to the trench gate structure 2, and a drain 6 electrically connected to the bottom surface of the semiconductor layer 1 are formed respectively.

[0129] Specifically, such as Figure 9 As shown, this is a cross-sectional view of the trench gate structure 2 after it is formed. The trench gate structure 2 includes a trench 21, a gate dielectric layer 22 and a gate conductive layer 23. The gate dielectric layer 22 covers the inner wall and bottom surface of the trench 21, the gate conductive layer 23 fills the trench 21, and the gate dielectric layer 22 wraps the side wall and bottom surface of the gate conductive layer 23.

[0130] Specifically, the method for forming the gate dielectric layer 22 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. Preferably, the gate dielectric layer 22 is formed using a thermal oxidation process, and the formed gate dielectric layer 22 covers the inner wall and bottom surface of the trench, while also covering the upper surface of the semiconductor layer 1.

[0131] Specifically, the methods for forming the gate conductive layer 23 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0132] It should be noted that during the process of forming the gate conductive layer 23 that fills the trench 21, the gate conductive layer 23 usually also covers the upper surface of the gate dielectric layer 22 above the semiconductor layer 1. Therefore, after the deposition process is completed, it is necessary to remove the portion of the gate conductive layer 23 covering the upper surface of the gate dielectric layer 22 directly above the semiconductor layer 1, and only retain the portion of the gate conductive layer 23 that fills the trench 21. The method for removing the portion of the gate conductive layer 23 covering the upper surface of the gate dielectric layer 22 directly above the semiconductor layer 1 is usually chemical mechanical polishing, or it can be a combination of chemical mechanical polishing and dry etching, or a combination of chemical mechanical polishing and wet etching. During the process of removing the gate conductive layer 23, the gate dielectric layer 22 covering the upper surface of the semiconductor layer 1 can be removed or retained.

[0133] Specifically, such as Figure 10 The diagram shows a cross-sectional view of the structure after the formation of the interlayer dielectric layer 4. After the formation of the trench gate structure 2 and before the formation of the source 5 and gate of the device, the process also includes the step of forming an interlayer dielectric layer 4 that covers the upper surface of the semiconductor layer 1 and the exposed surface of the trench gate structure 2.

[0134] Specifically, the methods for forming the interlayer medium layer 4 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0135] Specifically, after forming the interlayer dielectric layer 4 and before forming the source electrode 5 and the gate electrode, the process also includes forming a source contact hole and a gate contact hole. The source contact hole penetrates the interlayer dielectric layer 4 and exposes the source region 14 at the bottom. The gate contact hole penetrates the interlayer dielectric layer 4 and exposes the gate conductive layer 23 at the bottom.

[0136] Specifically, the methods for forming source contact holes include dry etching, wet etching, or other suitable methods; the methods for forming gate contact holes include dry etching, wet etching, or other suitable methods.

[0137] Specifically, a second conductivity type contact region 15 is also formed in the semiconductor layer 1. The contact region 15 is located on the upper surface of the body region 13 between two adjacent trenches 21, and the two side walls along the arrangement direction of the trenches 21 are respectively adjacent to the source regions 14 on both sides of that direction. The contact region 15 can be formed before the trenches 21 are formed, or it can be formed after the source contact hole is formed and before the source 5 is formed.

[0138] Specifically, if the contact area 15 is formed before the trench 21 is formed, the bottom surface of the source contact hole will expose the contact area 15. If the contact area 15 is formed after the source contact hole is formed and before the source 5 is formed, ion implantation can be performed on the bottom of the source contact hole based on the source contact hole to form the contact area 15.

[0139] Specifically, the methods for forming the contact region 15 include ion implantation or other suitable methods.

[0140] Specifically, the source electrode 5 fills the source contact hole and forms an ohmic contact between the source region 14 and the contact region 15, and the gate electrode fills the gate contact hole and is electrically connected to the gate conductive layer 23.

[0141] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the source electrode 5 after its formation. The methods for forming the source electrode 5 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The methods for forming the gate electrode include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. The methods for forming the drain electrode 6 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0142] Specifically, the source 5 and the gate can be formed simultaneously or in stages. Preferably, a metal layer that fills the source contact hole and the gate contact hole and covers the upper surface of the interlayer dielectric layer 4 is formed simultaneously first, and then the metal layer on the upper surface of the interlayer dielectric layer 4 is etched to obtain the gate and the source 5 simultaneously.

[0143] Specifically, after forming trench 21 and before forming gate dielectric layer 22, a first shielding layer 3 is formed in the drift region 12 at the bottom of trench 21, adjacent to the bottom of trench 21. Then, a second shielding layer 31 is formed in the semiconductor layer 1 on the same side of each trench 21, with its sidewall adjacent to the sidewall of trench 21. The bottom of the second shielding layer 31 is adjacent to the first shielding layer 3, and the top of the second shielding layer 31 is adjacent to the source region 14. This makes the drift region 12, the first shielding layer 3, the second shielding layer 31, and the source region 14 constitute a conductive channel controlled by gate conductive layer 23, which increases the density of conductive channels in the device and reduces the on-resistance of the device.

[0144] Specifically, since the first shielding layer 3 and the second shielding layer 31 are connected and electrically connected to the source electrode 5 through the body region 13 and the contact region 15, a superjunction structure is formed in the device through a simple process, which improves the withstand voltage of the device and further reduces the on-resistance of the device. At the same time, since the first shielding layer 3 is located at the bottom of the trench 21 and the second shielding layer 31 is adjacent to the sidewall of the trench 21, the protection strength of the gate dielectric layer 22 at the bottom of the trench 21 is improved through a simple process.

[0145] Specifically, by controlling the overlap area between the trench gate structure 2 and the drift region 12, the gate-drain parasitic capacitance C of the device can be controlled. gdWith gate-source parasitic capacitance C gs The ratio between them increases the switching speed of the device and reduces the risk of accidental activation during the switching process.

[0146] The trench gate device fabrication method of this embodiment involves forming a first shielding layer 3 in the drift region 12 at the bottom of the trench 21 after the trench 21 is formed and before the gate dielectric layer 22 is formed. A second shielding layer 31 is formed in the semiconductor layer 1 on the same side of each trench 21, with its sidewalls adjacent to the sidewalls of the trench 21. The bottom of the second shielding layer 31 is adjacent to the first shielding layer 3, and its top is adjacent to the source region 14. This allows the drift region 12, the first shielding layer 3, the second shielding layer 31, and the source region 14 to form a conductive channel controlled by the gate conductive layer 23. This increases the conductive channel density in the device and reduces the on-resistance. Simultaneously, the first shielding layer 3 is indirectly electrically connected to the source 5 through the second shielding layer 31, the body region 13, and the contact region 15. A superjunction structure is formed in the device through a simple process, further reducing the on-resistance and simultaneously enhancing the protection strength of the gate dielectric layer 22 at the bottom of the trench 21.

[0147] In summary, the trench gate device and its fabrication method of the present invention improve the device structure by forming a first shielding layer in the drift region at the bottom of the trench and a second shielding layer in the semiconductor layer on one side of the trench, with its sidewall adjacent to the trench sidewall. The bottom of the second shielding layer is adjacent to the first shielding layer and its top is adjacent to the source region, so that the drift region, the first shielding layer, the second shielding layer, and the source region constitute a conductive channel controlled by the gate conductive layer, increasing the density of conductive channels in the device and reducing the on-resistance of the device. The first shielding layer is electrically connected to the source through the second shielding layer, the body region, and the contact region, forming a superjunction through a simple process, further reducing the on-resistance of the device, while improving the protection strength of the gate dielectric layer at the bottom of the trench gate structure and increasing the withstand voltage of the device. By adjusting the size of the overlapping area between the trench gate structure and the drift region, the gate-drain parasitic capacitance C of the device can be adjusted. gd With gate-source parasitic capacitance C gs The ratio between the two layers increases the switching speed of the device, reduces the risk of accidental activation during switching, and improves device reliability. Furthermore, the combination of the first and second shielding layers allows for further reduction in the device's cell size, thereby increasing the conductive channel density and reducing the on-resistance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0148] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench gate device, characterized in that, include: A semiconductor layer includes a source region of a first conductivity type, a drift region of a first conductivity type, and a body region of a second conductivity type. The body region is located on the upper surface of the drift region, and a plurality of spaced source regions are located on the upper surface of the body region. A trench gate structure penetrates the source region and the body region and extends to the drift region at its bottom. The second conductivity type first shielding layer is located in the drift region directly below the trench gate structure and adjacent to the bottom of the trench gate structure; A second shielding layer of a second conductivity type is located in the semiconductor layer on the same side of each of the trench gate structures. The top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer. The semiconductor layer comprises a source, a gate, and a drain. The source is electrically connected to the source region, the gate is electrically connected to the trench gate structure, and the drain is electrically connected to the bottom surface of the semiconductor layer.

2. The trench gate device according to claim 1, characterized in that: The semiconductor layer further includes a substrate of a first conductivity type, the drift region is stacked on the upper surface of the substrate, and the drain is electrically connected to the bottom surface of the substrate.

3. The trench gate device according to claim 1, characterized in that: The second shielding layer is adjacent to the trench grid structure near the sidewall of the trench grid structure.

4. The trench gate device according to claim 1, characterized in that: The doping concentration of the second shielding layer is lower than that of the bulk region.

5. The trench gate device according to claim 1, characterized in that: The second shielding layer also includes a first conductivity type injection region. The injection region is located on the surface of the second shielding layer near the trench gate structure, and the sidewall of the injection region near the trench gate structure is adjacent to the trench gate structure. The top of the injection region is adjacent to the bottom surface of the source region.

6. The trench gate device according to claim 1, characterized in that: The drift region further includes a first region and a second region stacked sequentially, wherein the doping concentration of the second region is not less than the doping concentration of the first region, and the bottom surface of the first shielding layer is flush with the bottom surface of the second region.

7. The trench gate device according to claim 1, characterized in that: The semiconductor layer further includes a second conductivity type contact region, which is located on the upper surface of the body region between two adjacent source regions, and the contact region is adjacent to the source regions on both sides of the source region arrangement direction.

8. The trench gate device according to claim 1, characterized in that: The trench gate structure includes a trench, a gate dielectric layer, and a gate conductive layer. The trench penetrates the body region and extends to the drift region. The gate dielectric layer covers the inner wall and bottom surface of the trench. The gate conductive layer fills the trench. The gate dielectric layer wraps the sidewalls and bottom surface of the gate conductive layer. The gate is electrically connected to the gate conductive layer.

9. The trench gate device according to claim 1, characterized in that: The trench gate device also includes an interlayer dielectric layer, the source electrode penetrates the interlayer dielectric layer and is electrically connected to the source region, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the trench gate structure.

10. A method for fabricating a trench gate device, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer including a first conductivity type source region, a first conductivity type drift region and a second conductivity type body region, the body region being located on the upper surface of the drift region, and a plurality of spaced-apart source regions being located on the upper surface of the body region; A trench is formed that runs through the source region and the body region and extends to the drift region at its bottom. A first shielding layer of a second conductivity type is formed in the drift region located directly below the trench and adjacent to the bottom of the trench; A second shielding layer of a second conductivity type is formed in the semiconductor layer on the same side of each of the trenches, the top of the second shielding layer being adjacent to the source region, and the bottom of the first shielding layer being adjacent to the second shielding layer; A trench grid structure is formed based on the trenches; A source electrode electrically connected to the source region, a gate electrode electrically connected to the trench gate structure, and a drain electrode electrically connected to the bottom surface of the semiconductor layer are respectively formed.

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