A mask rule checking method, system, and terminal based on gradient descent algorithm

Abstract

This application provides a mask rule checking method, system, and terminal based on gradient descent algorithm. It traverses all graphic edges in the chip design layout and filters one or more neighboring edges for each graphic edge. Using a proximity cost function, it calculates the proximity cost value and cost gradient value between each graphic edge and its neighboring edges to calculate the total proximity cost value of the chip design layout, determining whether mask violations exist. If mask violations exist, it calculates the adjustment amount for each graphic edge based on the cost gradient value to update each graphic edge in the chip design layout. By repeating the above operations, iteratively optimizing the position of each graphic edge until no mask violations exist in the chip design layout. Thus, by searching the entire solution space of mask rules, it achieves a globally optimal solution, simultaneously eliminating all mask violations and significantly reducing computational load and saving computational costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a mask rule checking method, system and terminal based on gradient descent algorithm. Background Technology

[0002] In semiconductor chip manufacturing, to mitigate optical interference effects during photolithography, optical proximity correction is typically performed on the design patterns in the chip design layout. This involves adding one or more fine, sub-resolution auxiliary patterns along the edges of the design patterns to ensure the final lithographic pattern matches the design pattern, thereby guaranteeing chip manufacturing performance. However, optical proximity correction results in more numerous, finer, and more complex patterns added to the chip design layout. Before the chip design layout is sent to the mask fabrication process, a mask rule check must be performed to ensure that all patterns are suitable for the mask fabrication process and can be clearly etched onto the mask.

[0003] Existing mask rule checks are mainly based on mask rules provided by mask manufacturers. The specific method includes: inputting the mask rules and the chip design layout after optical proximity correction into optical proximity correction software, and using mask rule checking algorithms to identify and eliminate illegal patterns in the chip design layout, thereby obtaining a chip design layout suitable for mask production.

[0004] Masking rules can be uniformly categorized into minimum distance-based masking rules, including: minimum linewidth rules, line spacing rules, and corner spacing rules. Existing masking rule checking algorithms typically involve traversing all edges in the chip design layout, identifying one or more masking violations based on the masking rules, and moving the relevant edges of each violation to eliminate it. For example, if two edges of a graphic violate the minimum linewidth rule, they are moved outwards by a certain distance; if the spacing between two graphic edges violates the line spacing rule, the relevant edges are moved inwards by a certain distance. However, existing masking rule checking algorithms require sequentially traversing each violation and then eliminating it, resulting in high computational complexity and a tendency to generate new violations while eliminating the current one. Furthermore, when a graphic edge violates multiple masking rules simultaneously, it is difficult to eliminate all violations at the same time.

[0005] The mask rule checking algorithm disclosed in the existing patent (CN202510066515.X) includes: filtering multiple target groups of edges for mask violations based on a cost function, and determining the movement direction and amount of each target group edge according to the sum of the cost values ​​of each target group edge, so as to move the position of each target group edge and update the current chip design pattern; iterating repeatedly until all mask violations in the current chip design pattern are eliminated. However, this mask rule checking algorithm requires repeated filtering to obtain mask violations each time it eliminates mask violations, and each target group edge needs to be moved separately, resulting in many calculation steps and a large amount of computation; moreover, moving a single target group edge can easily generate new violations, which will increase the number of iterations and further increase the computational load of the mask rule checking algorithm. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a mask rule checking method, system and terminal based on gradient descent algorithm to solve the technical problems of large computational load and difficulty in eliminating all mask violations at the same time in existing mask rule checking algorithms.

[0007] To achieve the above and other related objectives, a first aspect of this application provides a mask rule checking method based on gradient descent algorithm. The method includes: acquiring a chip design layout after optical proximity correction, and performing a neighbor edge filtering operation on the chip design layout to filter one or more neighbor edges for each graphic edge in the chip design layout; based on predefined mask rules, performing a violation checking operation on the chip design layout according to the proximity relationship between each graphic edge and its neighbor edges to determine whether the chip design layout has mask violations; when the chip design layout has mask violations, using the gradient descent algorithm to perform a violation elimination operation on the chip design layout and updating the chip design layout; performing the neighbor edge filtering operation and violation checking operation on the updated chip design layout, and if the updated chip design layout still has mask violations, performing a violation elimination operation on the updated chip design layout, iterating repeatedly until the chip design layout has no mask violations.

[0008] In some embodiments of the first aspect of this application, the method of performing a violation check operation on the chip design layout includes: constructing a proximity cost function based on the mask rules; calculating the proximity generation value and cost gradient value between each graphic edge and its neighboring edges based on the proximity cost function; and calculating the total proximity generation value of the chip design layout based on each proximity generation value to determine whether there is a mask violation in the chip design layout.

[0009] In some embodiments of the first aspect of this application, the method for determining whether a chip design layout has a mask violation includes: if the total neighbor generation value of the chip design layout is greater than 0, then the chip design layout is determined to have a mask violation; if the total neighbor generation value of the chip design layout is equal to 0, then the chip design layout is determined not to have a mask violation.

[0010] In some embodiments of the first aspect of this application, the proximity relationship between the graphic edge and its neighboring edges includes: a first proximity relationship in which they are parallel to each other within the same graphic; a second proximity relationship in which they are parallel to each other within different graphics and their projections on the same plane overlap; and a third proximity relationship in which they are parallel to each other within different graphics but their projections on the same plane do not overlap.

[0011] In some embodiments of the first aspect of this application, the calculation method for the proximity cost value between the current graphic edge and its neighboring edge includes: determining the proximity relationship between the current graphic edge and the neighboring edge; if it is a first proximity relationship, then calculating the proximity cost value between the current graphic edge and the neighboring edge based on a pre-constructed first proximity cost function; the specific calculation formula is as follows: If it is the second proximity relationship, then based on the pre-constructed second proximity cost function, the proximity cost between the current graph edge and the neighboring edge is calculated; the specific calculation formula is as follows: If it is a third neighbor relationship, then based on the pre-constructed third neighbor cost function, the neighbor cost value between the current graph edge and that neighboring edge is calculated; the specific calculation formula is as follows: ;in, , as well as These are the proximity values ​​between the current graph edge and its first, second, and third neighboring edges, respectively, where the current graph edge and its first, second, and third neighboring edges have the first, second, and third proximity relationships, respectively. , as well as These are the first mask violation weight, the second mask violation weight, and the third mask violation weight, respectively. , as well as These are the minimum line width threshold, minimum line spacing threshold, and minimum corner spacing threshold of the graphic, as defined by the masking rules, respectively. This is the line spacing between the current graphic edge and its first adjacent edge; This is the line spacing between the current graphic edge and its second neighboring edge; This represents the distance between the endpoints of the current graphic edge and its third neighboring edge. This is a parameter indicating the importance of masking violations.

[0012] In some embodiments of the first aspect of this application, the calculation method for the cost gradient value between the current graphic edge and its neighboring edge includes: determining the proximity relationship between the current graphic edge and the neighboring edge; if it is a first proximity relationship, constructing a first gradient descent function based on the first proximity cost function, and calculating the cost gradient value between the current graphic edge and the neighboring edge accordingly; the specific calculation formula is as follows: If it is the second proximity relationship, then based on the second proximity cost function, a second gradient descent function is constructed, and the cost gradient value between the current graph edge and the neighboring edge is calculated accordingly; the specific calculation formula is as follows: If it is the third nearest neighbor relationship, then a third gradient descent function is constructed based on the third nearest neighbor cost function, and the cost gradient value between the current graph edge and the nearest neighbor edge is calculated accordingly; the specific calculation formula is as follows: ;in, , as well as These are the cost gradient values ​​between the current graph edge and its first neighboring edge, second neighboring edge, and third neighboring edge, respectively, where the current graph edge and its first neighboring edge, second neighboring edge, and third neighboring edge are respectively in a first neighboring relationship, a second neighboring relationship, and a third neighboring relationship; , as well as These are the first mask violation weight, the second mask violation weight, and the third mask violation weight, respectively. , as well as These are the minimum line width threshold, minimum line spacing threshold, and minimum corner spacing threshold of the graphic, as defined by the masking rules, respectively. This is the line spacing between the current graphic edge and its first adjacent edge; This is the line spacing between the current graphic edge and its second neighboring edge; This represents the distance between the endpoints of the current graphic edge and its third neighboring edge. This is a parameter indicating the importance of masking violations.

[0013] In some embodiments of the first aspect of this application, the formula for calculating the total proximity cost value is as follows: ;in, The total neighboring generation value of the chip design layout; For the first The first edge of the graphic The neighboring value between the first nearest edges; For the first The first edge of the graphic The neighboring value between the second nearest edges; For the first The first edge of the graphic The neighboring value between the third and nearest edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

[0014] In some embodiments of the first aspect of this application, the method of performing violation elimination operation on the chip design layout includes: calculating the adjustment amount of each graphic edge according to the cost gradient value between each graphic edge and its neighboring edges, so as to update each graphic edge of the chip design layout; wherein, the calculation formula for the adjustment amount of the current graphic edge is: ; ;in, For the first The first edge of the graphic Second adjustment amount For the first The first edge of the graphic The adjustment amount; The learning rate; For the first The total cost gradient value of the edges of the graph; For the first The first edge of the graphic The cost gradient value between the first neighboring edges; For the first The first edge of the graphic The cost gradient value between the second nearest edges; For the first The first edge of the graphic The cost gradient value between the third neighboring edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

[0015] To achieve the above and other related objectives, a second aspect of this application provides a mask rule checking system based on gradient descent algorithm. The system includes: a neighboring edge filtering module, used to acquire a chip design layout after optical proximity correction and perform a neighboring edge filtering operation on the chip design layout, filtering one or more neighboring edges of each graphic edge in the chip design layout; and a violation identification module, connected to the neighboring edge filtering module, used to perform a violation checking operation on the chip design layout based on predefined mask rules and the proximity relationship between each graphic edge and its neighboring edges, to determine whether the chip design layout contains violations. The mask violation and violation elimination module is connected to the violation identification module. When a mask violation exists in the chip design layout, it uses a gradient descent algorithm to perform a violation elimination operation on the chip design layout and updates the chip design layout. The violation elimination module is also connected to the neighboring edge filtering module. It sends the updated chip design layout to the neighboring edge filtering module to perform a neighboring edge filtering operation and a violation check operation on the updated chip design layout. If a mask violation still exists in the updated chip design layout, a violation elimination operation is performed on the updated chip design layout. This process is repeated iteratively until there are no mask violations in the chip design layout.

[0016] To achieve the above and other related objectives, a third aspect of this application provides a mask rule checking terminal based on the gradient descent algorithm. The mask rule checking terminal based on the gradient descent algorithm includes: a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory to enable the terminal to implement the mask rule checking method based on the gradient descent algorithm as described in any of the above embodiments.

[0017] As described above, this application provides a mask rule checking method, system, and terminal based on gradient descent algorithm. It traverses all graphic edges in the chip design layout and filters one or more neighboring edges for each graphic edge. Using a proximity cost function, it calculates the proximity cost value and cost gradient value between each graphic edge and its neighboring edges to calculate the total proximity cost value of the chip design layout, determining whether mask violations exist. If mask violations exist, it calculates the adjustment amount for each graphic edge based on the cost gradient values ​​to update each graphic edge of the chip design layout. By repeating the above operations, iteratively optimizing the position of each graphic edge until no mask violations exist in the chip design layout. Therefore, this application has the following beneficial effects: by searching the entire solution space of mask rules, it achieves a globally optimal solution, simultaneously eliminating all mask violations and greatly reducing computational load and saving computational costs, thus solving the technical problems of existing mask rule checking algorithms having high computational load and difficulty in simultaneously eliminating all mask violations. Attached Figure Description

[0018] Figure 1 The diagram shown is a flowchart of a mask rule checking method based on gradient descent algorithm in one embodiment of this application.

[0019] Figure 2 This is a schematic diagram showing the adjacent edges of the current graphic edge in one embodiment of this application.

[0020] Figure 3 The diagram shown is a schematic representation of a mask rule checking system based on gradient descent algorithm in one embodiment of this application.

[0021] Figure 4 The diagram shown is a schematic representation of a mask rule checking terminal based on the gradient descent algorithm in one embodiment of this application. Detailed Implementation

[0022] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0023] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first adjacent edge" and "second adjacent edge" are only used to distinguish different adjacent edges and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily imply that they are different.

[0024] To address the problems mentioned above, this application provides a mask rule checking method, system, and terminal based on gradient descent algorithm. The aim is to perform neighbor edge filtering and violation checking operations on a chip design layout after optical proximity correction. When mask violations exist in the chip design layout, gradient descent algorithm is used to perform violation elimination operations and update the chip design layout. This process is repeated iteratively to optimize the position of each graphic edge until no mask violations exist in the chip design layout. This solves the technical problems of existing mask rule checking algorithms having high computational complexity and difficulty in simultaneously eliminating all mask violations.

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.

[0026] like Figure 1 The diagram illustrates a flowchart of a mask rule checking method based on gradient descent algorithm according to an embodiment of this application. The mask rule checking method based on gradient descent algorithm in this embodiment mainly includes the following steps.

[0027] Step S1: Obtain the chip design layout after optical proximity correction, and perform a neighbor edge filtering operation on the chip design layout to filter one or more neighbor edges of each graphic edge in the chip design layout.

[0028] It should be understood that a chip design layout is the output file of the physical design of integrated circuits during the semiconductor chip manufacturing process, and includes multiple design patterns. To improve optical interference effects during photolithography, multiple auxiliary patterns are added to the original chip design layout to perform optical proximity correction. Therefore, a chip design layout with optical proximity correction includes multiple design patterns and multiple auxiliary patterns.

[0029] The design graphic and the auxiliary graphic are polygons, and each pair of adjacent sides of the polygon is at a right angle or a 45° angle, such as a long rectangle, a square, an isosceles right triangle, etc.

[0030] In one embodiment, the method for performing a neighbor edge filtering operation on a chip design layout after optical proximity correction includes: traversing each edge of a plurality of graphics in the chip design layout, and filtering one or more neighbor edges of each graphic edge from a target search range. The target search range can be determined based on a preset search distance; preferably, the search distance can be set to twice the maximum distance threshold in a predefined masking rule. However, it should be noted that the search distance can be set by the user according to their needs, and this application is not specifically limited to it.

[0031] The neighboring edges of the obtained graphic edge include: a first neighboring edge, a second neighboring edge, and a third neighboring edge. The first neighboring edge is a parallel edge to the graphic edge in the same graphic; the second neighboring edge is an edge in another graphic that is parallel to the graphic edge and whose projection on the same plane overlaps; the third neighboring edge is an edge in another graphic that is parallel to the graphic edge but whose projection on the same plane does not overlap.

[0032] That is, the proximity relationship between the edge of a figure and its neighboring edges includes: the first proximity relationship in the same figure where they are parallel to each other; the second proximity relationship in different figures where they are parallel to each other and their projections on the same plane overlap; and the third proximity relationship in different figures where they are parallel to each other but their projections on the same plane do not overlap.

[0033] For example, such as Figure 2 As shown, the current graphic edge includes three neighboring edges: the first neighboring edge, the second neighboring edge, and the third neighboring edge. The first neighboring edge is located in the same graphic as the current graphic edge and is parallel to it; the second neighboring edge is located in a different graphic and is parallel to it, but their projections on the same plane overlap; the third neighboring edge is located in a different graphic and is parallel to it, but their projections on the same plane do not overlap.

[0034] Step S2: Based on predefined masking rules, perform a violation check on the chip design layout according to the proximity relationship between each graphic edge and its neighboring edges to determine whether there are masking violations in the chip design layout.

[0035] The masking rules include: a minimum linewidth threshold, a minimum line spacing threshold, and a minimum corner spacing threshold. These thresholds specify the minimum distance between opposite edges of the same design pattern or auxiliary pattern, the minimum edge spacing between different patterns, and the minimum endpoint spacing in the chip design layout. In other words, the masking rules define the minimum distance between adjacent edges with different proximity relationships and the edge of the current pattern, used to identify non-compliant edges of the current pattern and support violation checking operations on the chip design layout.

[0036] It should be noted that the minimum line width threshold, minimum line spacing threshold, and minimum corner spacing threshold of the mask rules can be set by the user according to their needs, and this application does not specifically limit them.

[0037] In one embodiment, the method for performing a violation check on the chip design layout includes: constructing a proximity cost function based on the mask rules; calculating the proximity generation value and cost gradient value between each graphic edge and its neighboring edges based on the proximity cost function; and calculating the total proximity generation value of the chip design layout based on each proximity generation value to determine whether there is a mask violation in the chip design layout.

[0038] Specifically, based on the minimum line width threshold of the graphic in the masking rules, a first proximity cost function is constructed to calculate the proximity cost value between each graphic edge and its first neighboring edge; based on the minimum line spacing threshold of the graphic in the masking rules, a second proximity cost function is constructed to calculate the proximity cost value between each graphic edge and its second neighboring edge; based on the minimum corner spacing threshold of the graphic in the masking rules, a third proximity cost function is constructed to calculate the proximity cost value between each graphic edge and its third neighboring edge.

[0039] Each graph edge is traversed, and the proximity cost value between each graph edge and its neighboring edges is calculated based on the constructed proximity cost functions. In one embodiment, the calculation method for the proximity cost value between the current graph edge and its neighboring edges includes: determining the proximity relationship between the current graph edge and the neighboring edge; if it is a first proximity relationship, then calculating the proximity cost value between the current graph edge and the neighboring edge based on the pre-constructed first proximity cost function; if it is a second proximity relationship, then calculating the proximity cost value between the current graph edge and the neighboring edge based on the pre-constructed second proximity cost function; if it is a third proximity relationship, then calculating the proximity cost value between the current graph edge and the neighboring edge based on the pre-constructed third proximity cost function.

[0040] The formula for calculating the first proximity cost function is as follows:

[0041] ;Formula (1)

[0042] in, The proximity value is the value between the current graph edge and the first neighboring edge, and the current graph edge and the first neighboring edge have a first proximity relationship; The weight for the first mask violation; The minimum linewidth threshold for the graphic defined by the mask rule; The line spacing between the current graphic edge and its first adjacent edge, such as... Figure 2 As shown; This is a parameter indicating the importance of masking violations.

[0043] It should be understood that, according to the first proximity cost function, if the line spacing between the current graph edge and the first neighboring edge... Less than the minimum line width threshold of the graphic That is, the first neighboring edge violates the masking rules, resulting in a masking violation. In this case, the proximity value between the current graphic edge and the first neighboring edge is... If the line spacing between the current graphic edge and the first adjacent edge... Greater than or equal to the minimum line width threshold of the graphic If the first neighboring edge conforms to the masking rules and there is no masking violation, then the proximity value between the current graphic edge and the first neighboring edge is... .

[0044] The formula for calculating the second proximity cost function is as follows:

[0045] ;Formula (2)

[0046] in, The proximity value is the value between the current graph edge and the second neighboring edge, indicating that the current graph edge and the second neighboring edge have a second proximity relationship. Weighting for the second mask violation; The minimum line spacing threshold for the graphic defined by the mask rule; The line spacing between the current graphic edge and its second nearest edge, such as... Figure 2 As shown; This is a parameter indicating the importance of masking violations.

[0047] It should be understood that, according to the second proximity cost function, if the line spacing between the current graph edge and the second neighboring edge... Less than the minimum line spacing threshold of the graphic That is, the second neighboring edge violates the masking rules, resulting in a masking violation. In this case, the proximity value between the current graphic edge and the second neighboring edge is... If the line spacing between the current graphic edge and the second adjacent edge... Greater than or equal to the minimum line spacing threshold of the graphic If the second neighboring edge conforms to the masking rules and there is no masking violation, then the proximity value between the current graphic edge and the second neighboring edge is... .

[0048] The formula for calculating the third proximity cost function is as follows:

[0049] ;Formula (3)

[0050] in, The proximity value is the value between the current graph edge and the third neighboring edge, where the current graph edge and the third neighboring edge are in a third-nearest relationship. Weighting for third mask violations; The minimum corner spacing threshold for the graphic defined by the mask rule; The distance between the endpoints of the current graphic edge and its third neighboring edge, such as Figure 2 As shown, it should be noted that The minimum endpoint spacing between multiple endpoints of the current graph edge and its third neighboring edge; This is a parameter indicating the importance of masking violations.

[0051] It should be understood that, according to the third neighbor cost function, if the endpoint spacing between the current graph edge and the third neighbor edge... Less than the minimum corner spacing threshold of the graphic That is, the third neighboring edge violates the masking rules, resulting in a masking violation. In this case, the proximity value between the current graphic edge and the third neighboring edge is... If the distance between the endpoints of the current graphic edge and the third neighboring edge is... Greater than or equal to the minimum corner spacing threshold of the graphic If the third neighboring edge conforms to the masking rules and there is no masking violation, then the proximity value between the current graphic edge and the third neighboring edge is... .

[0052] In one embodiment, the first mask violation weight Second mask violation weight and the weight of third mask violation The same mask violation weight can be used; preferably, the length value of the current graphic edge can be selected as the mask violation weight. The mask violation importance parameter... Positive integers can be selected, and they must be even. Preferably, the following can be selected: 4 or 6.

[0053] It should be noted that users can select and set the values ​​of each mask violation weight and mask violation importance parameter according to their needs; this application does not specifically limit them.

[0054] Simultaneously, while calculating the value of each neighboring generation, a gradient descent function is constructed based on the constructed neighbor cost function; based on the gradient descent function, the cost gradient value between each graph edge and each of its neighboring edges is calculated respectively, so as to perform violation elimination operation on the chip design layout using the gradient descent algorithm.

[0055] In one embodiment, the method for calculating the cost gradient value between the current graphic edge and its neighboring edges includes: determining the proximity relationship between the current graphic edge and the neighboring edge; if it is a first proximity relationship, constructing a first gradient descent function based on the first proximity cost function, and calculating the cost gradient value between the current graphic edge and the neighboring edge accordingly; if it is a second proximity relationship, constructing a second gradient descent function based on the second proximity cost function, and calculating the cost gradient value between the current graphic edge and the neighboring edge accordingly; if it is a third proximity relationship, constructing a third gradient descent function based on the third proximity cost function, and calculating the cost gradient value between the current graphic edge and the neighboring edge accordingly.

[0056] The formula for calculating the first gradient descent function is:

[0057] ;Formula (4)

[0058] in, This is the cost gradient value between the current graph edge and the first neighboring edge, where the current graph edge and the first neighboring edge have a first proximity relationship. The weight for the first mask violation; The minimum linewidth threshold for the graphic defined by the mask rule; The line spacing between the current graphic edge and its first adjacent edge, such as... Figure 2 As shown; This is a parameter indicating the importance of masking violations.

[0059] The formula for calculating the second gradient descent function is as follows:

[0060] ;Formula (5)

[0061] in, This is the cost gradient value between the current graph edge and the second neighboring edge, where the current graph edge and the second neighboring edge are in a second proximity relationship. Weighting for the second mask violation; The minimum line spacing threshold for the graphic defined by the mask rule; The line spacing between the current graphic edge and its second nearest edge, such as... Figure 2 As shown; This is a parameter indicating the importance of masking violations.

[0062] The formula for calculating the third gradient descent function is as follows:

[0063] ;Formula (6)

[0064] in, This represents the cost gradient value between the current graph edge and its third neighbor edge, where the current graph edge and its third neighbor edge are in a third-neighbor relationship. Weighting for third mask violations; The minimum corner spacing threshold for the graphic defined by the mask rule; The distance between the endpoints of the current graphic edge and its third neighboring edge, such as Figure 2 As shown; This is a parameter indicating the importance of masking violations.

[0065] After traversing each edge of the graph and calculating the neighbor generation value and cost gradient value between each edge and its neighboring edges, the total neighbor generation value of the chip design layout is calculated based on the neighbor generation values. The formula for calculating the total neighbor cost value is as follows:

[0066] ;Formula (7)

[0067] in, The total neighboring generation value of the chip design layout; For the first The first edge of the graphic The neighboring value between the first nearest edges; For the first The first edge of the graphic The neighboring value between the second nearest edges; For the first The first edge of the graphic The neighboring value between the third and nearest edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

[0068] After calculating the total neighbor generation value of the chip design layout, it can be used to determine whether there are mask violations in the chip design layout. Specifically, if the total neighbor generation value of the chip design layout is greater than 0, then a mask violation is determined to exist in the chip design layout; if the total neighbor generation value of the chip design layout is equal to 0, then no mask violation is determined to exist in the chip design layout. In this case, the chip design layout has completed the mask rule check, and this chip design layout can be output as the target chip design layout for mask production.

[0069] Step S3: When there is a mask violation in the chip design layout, the gradient descent algorithm is used to perform violation elimination operation on the chip design layout and update the chip design layout.

[0070] In one embodiment, the violation elimination operation on the chip design layout includes: calculating the adjustment amount of each graphic edge based on the cost gradient value between each graphic edge and its neighboring edges, so as to update each graphic edge of the chip design layout.

[0071] Specifically, the formula for calculating the adjustment amount of the current graphic edge is:

[0072] ;Formula (8)

[0073] ;Formula (9)

[0074] in, For the first The first edge of the graphic Second adjustment amount For the first The first edge of the graphic The adjustment amount; The learning rate; For the first The total cost gradient value of the edges of the graph; For the first The first edge of the graphic The cost gradient value between the first neighboring edges; For the first The first edge of the graphic The cost gradient value between the second nearest edges; For the first The first edge of the graphic The cost gradient value between the third neighboring edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

[0075] It should be understood that, according to the first gradient descent function, if a first neighboring edge of the current graphic edge violates the masking rule, that is, the line spacing between the current graphic edge and the first neighboring edge... Less than the minimum line width threshold of the graphic Then at this time Based on the gradient descent algorithm, the edges of the current shape need to be moved outwards by a certain amount. For example, ... Figure 2 As shown, it needs to be moved down by a certain amount of adjustment, away from the first adjacent edge of the violation.

[0076] According to the second gradient descent function, if a second neighboring edge of the current graphic edge violates the masking rule, that is, the line spacing between the current graphic edge and the second neighboring edge... Less than the minimum line spacing threshold of the graphic Then at this time Based on the gradient descent algorithm, the current edge of the graphic needs to be moved inward by a certain amount. For example, ... Figure 2 As shown, it needs to be moved upwards by a certain amount of adjustment, away from the second adjacent edge of the violation.

[0077] According to the third gradient descent function, if the third neighboring edge of the current graphic edge violates the masking rule, that is, the endpoint spacing between the current graphic edge and the third neighboring edge... Less than the minimum corner spacing threshold of the graphic Then at this time Based on the gradient descent algorithm, the current edge of the graph needs to be moved away from the third neighboring edge by a certain amount of adjustment.

[0078] Simultaneously, if the current graphic edge has multiple adjacent edges or adjacent edges with different proximity relationships that violate the masking rules, the adjustment amounts are accumulated to obtain the total adjustment amount, and the current graphic edge is adjusted accordingly. After traversing all graphic edges, each graphic edge is adjusted based on the calculated adjustment amount, thereby updating the chip design layout.

[0079] Step S4: Perform adjacent edge filtering and violation checking operations on the updated chip design layout. If mask violations still exist in the updated chip design layout, perform violation elimination operations on the updated chip design layout. Repeat this process until there are no mask violations in the chip design layout.

[0080] That is, each graphic edge in the updated chip design layout is re-traversed, and one or more new neighboring edges for each graphic edge are selected from the target search range of each graphic edge; based on the constructed proximity cost function, the neighbor generation value and cost gradient value between each graphic edge and each of its neighboring edges are calculated; based on each neighbor generation value, the total neighbor generation value of the updated chip design layout is calculated, and it is determined again whether the updated chip design layout still has mask violations; if the chip design layout still has mask violations, the adjustment amount of each graphic edge is calculated based on the cost gradient value between each graphic edge and each of its neighboring edges, and each graphic edge is updated again; the above operation is repeated to iteratively optimize the position of each graphic edge until there are no mask violations in the chip design layout. At this time, the chip design layout is the target chip design layout, which can be used for mask production.

[0081] This application employs an iterative optimization scheme based on the proximity cost function and gradient descent algorithm to solve mask rule violations. Mask violations are identified by the total proximity cost of all graphic edges, and each graphic edge is iteratively adjusted. This allows for a search of the entire solution space, making it easier to find the global optimal solution and thus simultaneously eliminate all mask violations, including many complex mask violations.

[0082] Furthermore, this application calculates the cost gradient value of each graphic edge while traversing each graphic edge and calculating the neighbor cost value of each graphic edge, so as to adjust the graphic edges with mask violations. This avoids the large amount of computation required by existing mask rule checking algorithms to identify each mask violation in turn and then traverse each mask violation to eliminate the violation, thus saving computational costs.

[0083] like Figure 3 The diagram shows a schematic representation of a mask rule checking system 300 based on gradient descent algorithm according to an embodiment of this application. The mask rule checking system 300 based on gradient descent algorithm in this embodiment mainly includes: a neighboring edge filtering module 301, a violation identification module 302, and a violation elimination module 303.

[0084] like Figure 3As shown, the neighbor edge filtering module 301, the violation identification module 302, and the violation elimination module 303 are connected in sequence, and the violation elimination module 303 is connected to the neighbor edge filtering module 301.

[0085] The neighbor edge filtering module 301 is used to obtain the chip design layout after optical proximity correction, and perform a neighbor edge filtering operation on the chip design layout to filter one or more neighbor edges of each graphic edge in the chip design layout.

[0086] The violation identification module 302 is used to perform a violation check operation on the chip design layout based on predefined mask rules and the proximity relationship between each graphic edge and its neighboring edges, to determine whether there are mask violations in the chip design layout.

[0087] The violation elimination module 303 is used to perform violation elimination operation on the chip design layout and update the chip design layout when there is a mask violation in the chip design layout.

[0088] Furthermore, the violation elimination module 303 is also used to send the updated chip design layout to the neighboring edge filtering module 301 to continue to perform neighboring edge filtering and violation checking operations on the updated chip design layout. When the updated chip design layout still has mask violations, the violation elimination operation is performed on the updated chip design layout. This process is repeated iteratively until there are no mask violations in the chip design layout.

[0089] It should be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor or functional module, exist as separate physical entities, or be divided into more functional modules. The integrated modules or units described above can be implemented in hardware or as software functional modules.

[0090] It should also be understood that the mask rule checking system based on gradient descent algorithm provided in the above embodiments and the mask rule checking method embodiment based on gradient descent algorithm belong to the same concept. The specific implementation methods and steps of each functional module are detailed in the method embodiment, and will not be repeated here.

[0091] Figure 4 This is a schematic diagram of the structure of a mask rule checking terminal 400 based on the gradient descent algorithm provided in an embodiment of this application. Figure 4As shown, the mask rule checking terminal 400 based on gradient descent algorithm includes: at least one processor 401, a memory 402, at least one network interface 403, and a user interface 405. The various components in the terminal are coupled together via a bus system 404 to implement the mask rule checking method based on gradient descent algorithm described in the above embodiments. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 4 The general will label all buses as bus systems.

[0092] The user interface 405 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0093] It is understood that memory 402 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this application are intended to include, but are not limited to, these and any other suitable categories of memory.

[0094] In this embodiment, the memory 402 is used to store various types of data to support the operation of the gradient descent-based mask rule checking terminal 400. Examples of this data include any executable program that operates on the gradient descent-based mask rule checking terminal 400, such as the operating system 4021 and application program 4022. The operating system 4021 includes various system programs, such as the framework layer, core library layer, and driver layer, for implementing various basic services and handling hardware-based tasks. The application program 4022 may include various applications, such as a media player and a browser, for implementing various application services. The implementation of the gradient descent-based mask rule checking method provided in this embodiment can be included in the application program 4022.

[0095] The mask rule checking method based on gradient descent algorithm disclosed in the above embodiments of this application can be applied to processor 401, or implemented by processor 401. Processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the mask rule checking method based on gradient descent algorithm can be completed by the integrated logic circuit of the hardware in processor 401 or by instructions in the form of software. The processor 401 mentioned above may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 401 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. General-purpose processor 401 may be a microprocessor or any conventional processor, etc. The steps of the mask rule checking method based on gradient descent algorithm provided in the embodiments of this application can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0096] In an exemplary embodiment, the mask rule checking terminal 400 based on the gradient descent algorithm can be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to perform the aforementioned method.

[0097] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0098] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact optical discs (CDs), laser optical discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0099] In summary, this application provides a mask rule checking method, system, and terminal based on gradient descent algorithm. It traverses all graphic edges in the chip design layout and filters one or more neighboring edges for each graphic edge. Using a proximity cost function, it calculates the proximity cost value and cost gradient value between each graphic edge and its neighboring edges to calculate the total proximity cost value of the chip design layout, thus determining whether mask violations exist. When mask violations exist, it calculates the adjustment amount for each graphic edge based on the cost gradient values ​​to update each graphic edge of the chip design layout. By repeating the above operations, iteratively optimizing the position of each graphic edge until no mask violations exist in the chip design layout. Therefore, this application has the following beneficial effects: by searching the entire solution space of mask rules, it achieves a globally optimal solution, simultaneously eliminating all mask violations and greatly reducing computational load and saving computational costs, thereby solving the technical problems of existing mask rule checking algorithms having high computational load and difficulty in simultaneously eliminating all mask violations.

[0100] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0101] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A mask rule checking method based on gradient descent algorithm, characterized in that, include: Obtain the chip design layout after optical proximity correction, and perform a neighbor edge filtering operation on the chip design layout to filter one or more neighbor edges of each graphic edge in the chip design layout; Based on predefined masking rules, and according to the proximity relationship between each graphic edge and its neighboring edges, a violation check is performed on the chip design layout to determine whether there are masking violations in the chip design layout. When a mask violation exists in the chip design layout, the gradient descent algorithm is used to perform violation elimination operation on the chip design layout and update the chip design layout. The updated chip design layout is subjected to adjacent edge filtering and violation checking operations. If mask violations still exist in the updated chip design layout, a violation elimination operation is performed on the updated chip design layout. This process is repeated until there are no mask violations in the chip design layout. The method for performing violation checks on the chip design layout includes: constructing a proximity cost function based on the mask rules; calculating the proximity generation value and cost gradient value between each graphic edge and its neighboring edges based on the proximity cost function; and calculating the total proximity generation value of the chip design layout based on the proximity generation value to determine whether there are mask violations in the chip design layout. The calculation method for the cost gradient value between the current graph edge and its neighboring edges includes: determining the proximity relationship between the current graph edge and the neighboring edge; if it is a first proximity relationship, then constructing a first gradient descent function based on the pre-constructed first proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly; if it is a second proximity relationship, then constructing a second gradient descent function based on the pre-constructed second proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly; if it is a third proximity relationship, then constructing a third gradient descent function based on the pre-constructed third proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly. The method for performing violation elimination operations on the chip design layout includes: calculating the adjustment amount for each graphic edge based on the cost gradient value between each graphic edge and its neighboring edges, so as to update each graphic edge of the chip design layout.

2. The mask rule checking method based on gradient descent algorithm according to claim 1, characterized in that, The methods for determining whether a chip design layout has a mask violation include: if the total neighbor generation value of the chip design layout is greater than 0, then the chip design layout is determined to have a mask violation; if the total neighbor generation value of the chip design layout is equal to 0, then the chip design layout is determined not to have a mask violation.

3. The mask rule checking method based on gradient descent algorithm according to claim 1, characterized in that, The proximity relationships between the edges of a graphic and their neighboring edges include: a first proximity relationship where they are parallel to each other within the same graphic; a second proximity relationship where they are parallel to each other within different graphics and their projections on the same plane overlap; and a third proximity relationship where they are parallel to each other within different graphics but their projections on the same plane do not overlap.

4. The mask rule checking method based on gradient descent algorithm according to claim 3, characterized in that, The methods for calculating the proximity cost between a current graph edge and its neighboring edges include: Determine the proximity relationship between the current edge of the graphic and its neighboring edge; If it is the first proximity relationship, then based on the pre-constructed first proximity cost function, the proximity cost value between the current graph edge and the adjacent edge is calculated; the specific calculation formula is as follows: ; If it is the second proximity relationship, then based on the pre-constructed second proximity cost function, the proximity cost value between the current graph edge and the neighboring edge is calculated; the specific calculation formula is as follows: ; If it is the third nearest neighbor relationship, then based on the pre-constructed third nearest neighbor cost function, the neighbor cost value between the current graph edge and that neighboring edge is calculated; the specific calculation formula is as follows: ; in, , as well as These are the proximity values ​​between the current graph edge and its first, second, and third neighboring edges, respectively, where the current graph edge and its first, second, and third neighboring edges have the first, second, and third proximity relationships, respectively. , as well as These are the first mask violation weight, the second mask violation weight, and the third mask violation weight, respectively. , as well as These are the minimum line width threshold, minimum line spacing threshold, and minimum corner spacing threshold of the graphic, as defined by the masking rules, respectively. This is the line spacing between the current graphic edge and its first adjacent edge; This is the line spacing between the current graphic edge and its second neighboring edge; This represents the distance between the endpoints of the current graphic edge and its third neighboring edge. This is a parameter indicating the importance of masking violations.

5. The mask rule checking method based on gradient descent algorithm according to claim 4, characterized in that, The specific formula for calculating the first gradient descent function is as follows: ; The specific formula for calculating the second gradient descent function is as follows: ; The specific formula for calculating the third gradient descent function is as follows: ; in, , as well as These are the cost gradient values ​​between the current graph edge and its first neighboring edge, second neighboring edge, and third neighboring edge, respectively, where the current graph edge and its first neighboring edge, second neighboring edge, and third neighboring edge are respectively in a first neighboring relationship, a second neighboring relationship, and a third neighboring relationship; , as well as These are the first mask violation weight, the second mask violation weight, and the third mask violation weight, respectively. , as well as These are the minimum line width threshold, minimum line spacing threshold, and minimum corner spacing threshold of the graphic, as defined by the masking rules, respectively. This is the line spacing between the current graphic edge and its first adjacent edge; This is the line spacing between the current graphic edge and its second neighboring edge; This represents the distance between the endpoints of the current graphic edge and its third neighboring edge. This is a parameter indicating the importance of masking violations.

6. The mask rule checking method based on gradient descent algorithm according to claim 4, characterized in that, The formula for calculating the total proximity cost is as follows: ； in, The total neighboring generation value of the chip design layout; For the first The first edge of the graphic The neighboring value between the first nearest edges; For the first The first edge of the graphic The neighboring value between the second nearest edges; For the first The first edge of the graphic The neighboring value between the third and nearest edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

7. The mask rule checking method based on gradient descent algorithm according to claim 5, characterized in that, The formula for calculating the adjustment amount of the current graphic edge is: ； ； in, For the first The first edge of the graphic Second adjustment amount For the first The first edge of the graphic The adjustment amount; The learning rate; For the first The total cost gradient value of the edges of the graph; For the first The first edge of the graphic The cost gradient value between the first neighboring edges; For the first The first edge of the graphic The cost gradient value between the second nearest edges; For the first The first edge of the graphic The cost gradient value between the third neighboring edges; For the first The number of first neighboring edges of a graph; For the first The number of second neighboring edges of a graph; For the first The number of third neighboring edges of a graph; This refers to the number of graphic edges within the chip design layout.

8. A mask rule checking system based on gradient descent algorithm, characterized in that, include: The neighboring edge filtering module is used to obtain the chip design layout after optical proximity correction and perform a neighboring edge filtering operation on the chip design layout to filter one or more neighboring edges of each graphic edge in the chip design layout. The violation identification module is connected to the neighboring edge filtering module. It is used to perform a violation check operation on the chip design layout based on predefined masking rules and the proximity relationship between each graphic edge and its neighboring edges to determine whether there are mask violations in the chip design layout. The violation elimination module, connected to the violation identification module, is used to perform violation elimination operations on the chip design layout using the gradient descent algorithm when a mask violation exists in the chip design layout, and to update the chip design layout. The violation elimination module is also connected to the neighboring edge filtering module, which sends the updated chip design layout to the neighboring edge filtering module to perform neighboring edge filtering and violation checking operations on the updated chip design layout. When the updated chip design layout still has mask violations, the violation elimination operation is performed on the updated chip design layout. This process is repeated until there are no mask violations in the chip design layout. The method for performing violation checks on the chip design layout includes: constructing a proximity cost function based on the mask rules; calculating the proximity generation value and cost gradient value between each graphic edge and its neighboring edges based on the proximity cost function; and calculating the total proximity generation value of the chip design layout based on the proximity generation value to determine whether there are mask violations in the chip design layout. The calculation method for the cost gradient value between the current graph edge and its neighboring edges includes: determining the proximity relationship between the current graph edge and the neighboring edge; if it is a first proximity relationship, then constructing a first gradient descent function based on the pre-constructed first proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly; if it is a second proximity relationship, then constructing a second gradient descent function based on the pre-constructed second proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly; if it is a third proximity relationship, then constructing a third gradient descent function based on the pre-constructed third proximity cost function, and calculating the cost gradient value between the current graph edge and the neighboring edge accordingly. The method for performing violation elimination operations on the chip design layout includes: calculating the adjustment amount for each graphic edge based on the cost gradient value between each graphic edge and its neighboring edges, so as to update each graphic edge of the chip design layout.

9. A mask rule checking terminal based on gradient descent algorithm, characterized in that, include: Memory and processor; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory to enable the terminal to implement the mask rule checking method based on the gradient descent algorithm as described in any one of claims 1 to 7.

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