A method, apparatus, device, and readable storage medium for configuring DPU resources.

Abstract

This specification provides a method, apparatus, device, and readable storage medium for configuring DPU resources. The method includes: accessing a preset path of a target server through a set channel to obtain the PCI resource configuration information of the target server's current hardware; calculating the amount of allocated hardware resources in the target server's hardware resources based on the obtained PCI resource configuration information; and calculating a critical value for the maximum reserved hardware resources based on the allocated hardware resources. The target server includes a DPU device. This technical solution automatically obtains the server's PCI resource configuration and calculates the maximum reserved resource critical value, effectively avoiding the tedious process of repeatedly restarting the server to gradually approach the critical value in traditional manual testing, significantly improving testing efficiency. Simultaneously, this method ensures the accuracy of the critical value results through precise system resource analysis, providing a reliable basis for resource reservation under the DPU.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a DPU resource configuration method, apparatus, device, and readable storage medium. Background Technology

[0002] In the context of the rapid development of data center and cloud computing technologies, the Data Processing Unit (DPU), as a dedicated coprocessor, is becoming increasingly important. The core design goal of the DPU is to offload computing tasks such as networking, storage, security, and virtualization from the Central Processing Unit (CPU), thereby significantly improving the efficiency and performance of the entire system. In terms of specific hardware implementation, a DPU card typically provides one or more PCIe switches for a server, and each PCIe switch further provides multiple PCIe downstream ports (DSPs). This architecture allows users to flexibly and dynamically adjust computing resources by hot-plugging various storage, network, and other types of PCIe devices onto the DSP ports, achieving elastic scaling to quickly respond to changing business needs. To ensure that this hot-plugging operation can be performed smoothly, the system's Basic Input / Output System (BIOS) must reserve or allocate sufficient memory-mapped input / output (MMIO) and other critical resources for each DSP during the system startup initialization phase, so that newly connected devices can immediately obtain the address space necessary for their operation when a hot-plugging event occurs.

[0003] At the BIOS startup and initialization point, it cannot know in advance which specific DSPs will be hot-plugged with devices in the future, nor can it predict how much base address register (BAR) space these devices will require. To address this uncertainty, a common BIOS implementation strategy is to combine static allocation with dynamic expansion: initially, a fixed-size MMIO resource is allocated to each DSP; when the resources required by subsequent hot-plugged devices exceed this pre-allocated value, the BIOS attempts to dynamically increase the amount of reserved resources allocated to that DSP until the system's resource limit can no longer be increased. While this mechanism ensures functionality to a certain extent, it poses significant challenges to system testing and verification. During testing, to ensure system stability and reliability, testers must accurately identify the maximum reserved resource threshold that the BIOS can successfully allocate and conduct thorough verification within different resource ranges around this threshold (e.g., just meeting, slightly below, reaching, or exceeding the threshold). Because server platforms have diverse hardware configuration options (such as different CPU models, memory capacities, and installed expansion cards), these configuration differences directly affect the total MMIO address space size of the system and the amount of resources already occupied by other system components. This results in significant differences in the maximum reservable resource threshold of the DSP under the DPU for servers with different configurations.

[0004] Currently, testers need to manually configure relevant registers by repeatedly entering command-line instructions within the DPU's operating system (OS) environment to simulate allocating resources of different sizes to the DSP. Each time resource allocation is completed, the entire server system must be restarted, and then it must be observed whether the resources can be allocated correctly under the current settings. Through this iterative cycle of "manual configuration - restart verification - gradually increasing resource values," testers attempt to gradually approach and ultimately find the maximum resource reservation threshold. This method is essentially a linear search process based on trial and error, and its limitations are particularly prominent. Especially when testing combinations of various hardware configurations, or when verifying that multiple DSPs simultaneously reserve resources and their sum exceeds the threshold, the number of restarts required increases dramatically, making the entire process extremely cumbersome and time-consuming. Extensive manual intervention not only introduces the possibility of human error, but more seriously, it severely limits the coverage and efficiency of testing, becoming a key constraint affecting the development and testing cycle of DPU-related products. Summary of the Invention

[0005] In view of this, this specification provides a DPU resource configuration method, apparatus, device, and readable storage medium to improve the aforementioned problem of low efficiency in identifying hardware resource thresholds.

[0006] The specific technical solution is as follows: This specification provides a DPU resource configuration method for managing devices. The method includes: accessing a preset path of a target server through a set channel to obtain the PCI resource configuration information of the target server's current hardware; calculating the amount of allocated hardware resources in the target server's hardware resources based on the obtained PCI resource configuration information, wherein the hardware resources can be allocated to PCIe devices connected to the DPU device for PCIe device operation; and calculating a threshold value for the maximum reserved hardware resources based on the allocated hardware resources; wherein the target server includes a DPU device.

[0007] As a technical solution, the PCI resource configuration information includes the address range and allocated information of the PCI bus, I / O ports, MMIO32, and MMIO64.

[0008] As a technical solution, the step of calculating the critical value of the maximum reserved hardware resources based on the allocated hardware resources includes: calculating the amount of unallocated hardware resources based on the allocated hardware resources, calling QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configuring hardware resources for the virtual PCIe devices based on the amount of unallocated hardware resources, verifying whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirming the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

[0009] As a technical solution, the PCI resource configuration information of the target server's current hardware is obtained by setting a channel to access the target server's preset path. This includes: logging into the target server system via an SSH channel, using the dm esg and lspci commands, and accessing the system directory to obtain the PCI resource configuration information of the target server's current hardware.

[0010] This specification also provides a DPU resource configuration device for use in management devices. The device includes: a first module for accessing a preset path of a target server through a set channel to obtain the PCI resource configuration information of the target server's current hardware; a second module for calculating the amount of allocated hardware resources in the target server's hardware resources based on the obtained PCI resource configuration information, wherein the hardware resources can be allocated to PCIe devices connected to the DPU device for PCIe device operation; and a third module for calculating the threshold value of the maximum reserved hardware resources based on the allocated hardware resources. The target server includes a DPU device.

[0011] As a technical solution, the PCI resource configuration information includes the address range and allocated information of the PCI bus, I / O ports, MMIO32, and MMIO64.

[0012] As a technical solution, the step of calculating the critical value of the maximum reserved hardware resources based on the allocated hardware resources includes: calculating the amount of unallocated hardware resources based on the allocated hardware resources, calling QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configuring hardware resources for the virtual PCIe devices based on the amount of unallocated hardware resources, verifying whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirming the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

[0013] As a technical solution, the PCI resource configuration information of the target server's current hardware is obtained by setting a channel to access the target server's preset path. This includes: logging into the target server system via an SSH channel, using the dm esg and lspci commands, and accessing the system directory to obtain the PCI resource configuration information of the target server's current hardware.

[0014] This specification also provides an electronic device, including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned DPU resource configuration method.

[0015] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned DPU resource configuration method.

[0016] The technical solutions provided in this specification offer at least the following beneficial effects: By automatically acquiring the server's PCI resource configuration and calculating the maximum reserved resource threshold, this method effectively avoids the tedious process of repeatedly restarting the server to gradually approach the threshold in traditional manual testing, significantly improving testing efficiency. Simultaneously, this method ensures the accuracy of the threshold results through precise system resource analysis, providing a reliable basis for resource reservation under DPU. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.

[0018] Figure 1 This is a flowchart of a DPU resource configuration method in one embodiment of this specification; Figure 2 This is a flowchart of one embodiment of this specification; Figure 3 This is a structural diagram of a DPU resource configuration device according to one embodiment of this specification; Figure 4 This is a hardware structure diagram of an electronic device according to one embodiment of this specification.

[0019] Reference numerals: Module 1 21, Module 22, Module 3 23. Detailed Implementation

[0020] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0022] This specification provides a method, apparatus, device, and readable storage medium for configuring DPU resources to at least improve one of the aforementioned technical problems.

[0023] The specific technical solution is described below.

[0024] In one embodiment, this specification provides a DPU resource configuration method applied to a management device. The method includes: accessing a preset path of a target server through a set channel to obtain the PCI resource configuration information of the target server's current hardware; calculating the amount of allocated hardware resources in the target server's hardware resources based on the obtained PCI resource configuration information, wherein the hardware resources can be allocated to PCIe devices connected to the DPU device for the operation of the PCIe devices; and calculating a threshold value for the maximum reserved hardware resources based on the allocated hardware resource amount; wherein the target server includes a DPU device.

[0025] This method is deployed in a separate management device, which can be a dedicated server in a data center operations and maintenance platform, an out-of-band management controller (such as a BMC), an automated testing industrial control computer, or a resource scheduling node in a cloud management platform. Its core objective is to accurately assess the hardware resource configuration capabilities of a target server containing a Data Processing Unit (DPU), with a particular focus on system-level hardware resources available for connecting PCIe hot-swappable devices to the DPU—primarily including the MMIO (Memory-Mapped I / O) address space, I / O port address space, and PCI bus number resources. These resources are uniformly allocated by the system firmware (such as BIOS / UEFI) during the boot phase and directly affect the successful enumeration and normal operation of subsequent hot-swappable devices. Therefore, the management device needs to securely and efficiently access the target server's internal PCI configuration space through a pre-defined communication channel to obtain the current actual resource allocation topology.

[0026] Specifically, such as Figure 1 This includes the following steps, the order of which can be changed depending on the needs of the actual application scenario: Step S11: Access the target server's preset path through the set channel to obtain the target server's current hardware PCI resource configuration information.

[0027] In practical deployments, this "configuration channel" is typically built upon IPMI (Intelligent Platform Management Interface), Redfish API, SSH remote command channels, or dedicated PCIe configuration space agent services. For example, in large-scale data center scenarios, each target server is equipped with a BMC module supporting the IPMI 2.0 protocol. Management devices can send standard IPMI commands to the target server's BMC via the local area network, thereby triggering a scan operation on the local PCIe bus. Alternatively, if the target server has a lightweight agent installed, which resides in the operating system kernel or user space and listens on a specific port, the management device can call the agent via an SSH tunnel or HTTPS interface to execute deep scan commands such as lspci -v -vv -xxxx and return the raw PCI configuration space data in a structured manner. Regardless of the channel used, the key is to ensure that the acquired data accurately reflects the current PCI resource allocation status of the system (especially since the most recent boot), including the size, type (32-bit / 64-bit), prefetchability, and MMIO base address and length occupied by all root complexes, PCIe switches, DPU devices themselves, and their downstream ports (DSPs). Furthermore, it is necessary to obtain overall system resource pool information, such as the ECAM (Enhanced Configuration Access Mechanism) region range defined by the ACPI table (especially the MCFG table) under x86 architecture, which directly limits the total available MMIO space of the entire system.

[0028] Step S12: Calculate the amount of hardware resources already allocated in the target server's hardware resources based on the obtained PCI resource configuration information of the target server.

[0029] This step doesn't simply involve accumulating the BAR values ​​of all devices; it requires layered parsing and deduplication based on the PCIe topology. For example, suppose the target server has an Intel Sapphire Rapids CPU, and its integrated PCIe Root Port is connected to an NVIDIA BlueField-3 DPU card. This DPU integrates two PCIe Switches, each connected to four DSP ports. The management device first needs to identify the DPU's Vendor ID and Device ID to confirm its model and internal topology capabilities. Then, it iterates through all downstream ports, extracting whether a device is currently plugged into each port and the BAR requirements of the plugged-in device (e.g., NVMe SSDs typically request 128MB or 256MB of 64-bit prefetchable MMIO space). Simultaneously, it also needs to calculate the resources used by the DPU itself as an upstream device (e.g., BAR0 for control plane communication, BAR2 for the DMA engine, etc.). More importantly, the hierarchical nature of resource allocation must be considered: the upstream port (USP) of a PCIe switch aggregates resource requests from all its downstream ports and requests contiguous and aligned address blocks from the next higher level. Therefore, the calculation of allocated resources must trace back from the leaf node (i.e., the last PCIe device), merging adjacent or mergeable address ranges level by level, and deducting internal fragmentation caused by alignment requirements (such as 4KB or 1MB boundary alignment). For example, if a switch has two devices requesting 64MB and 96MB of MMIO space respectively, because the PCIe specification requires that the window allocated by the switch to its downstream devices must be a power of 2 and aligned to its own size, the system may actually allocate a contiguous window of 256MB, of which only 160MB is effectively used, with the remaining 96MB used for alignment padding. When calculating the "allocated amount," the entire 256MB window should be included, as this portion of address space has been reserved and cannot be allocated to other branches. Through this refined topology-aware computing, the management device can determine the total number of MMIOs, the total number of I / O ports, and the number of PCI bus numbers actually used by various devices in the current system (including non-DPU devices such as GPUs, network cards, RAID cards, etc.).

[0030] Step S13: Calculate the critical value of the maximum reserved hardware resources based on the amount of allocated hardware resources.

[0031] This threshold value is not a fixed constant, but rather dynamically depends on the hardware platform characteristics and current load status of the target server. Taking MMIO resources as an example, modern x86 servers typically reserve a segment of high memory address space (such as 0x38000000000 to 0x3FFFFFFFFFF) as a PCIe MMIO window through the CPU's memory controller. The total capacity may be 32GB, 64GB, or even higher. The specific value is automatically set by the BIOS based on the memory layout and recorded in the ACPI MCFG table. The management device first parses this total capacity T_total from the acquired configuration information; then it subtracts the previously calculated allocated amount T_used to obtain the theoretical remaining space T_remain = T_total - T_used.

[0032] The advantage of this method lies not only in static evaluation but also in its ability to be embedded in an automated testing loop. Management devices can automatically perform the aforementioned resource configuration analysis on multiple servers with different configurations (such as different CPUs, memory, and installed device combinations), generating a critical value matrix for each model. The test script then uses this matrix to precisely construct boundary test cases—for example, simulating the insertion of a virtual device requesting a 3.9GB BAR on a DSP to verify whether the system can successfully allocate the device; then attempting 4.1GB to verify whether it is correctly rejected and to record the error log. This intelligent testing based on real hardware conditions completely replaces the traditional blindly incremental manual restart testing, reducing the single verification cycle from hours to minutes. Furthermore, this method can also be used for capacity planning in production environments: when operations personnel allocate virtual machines or containers to customers, if the customer requests the mounting of high-performance PCIe devices, the resource scheduler can query the DPU port critical values ​​of the corresponding physical server in real time to ensure that the allocation request is within a safe range, thereby avoiding runtime failures.

[0033] In one implementation, the management device first establishes a configuration channel with the target server, preferably using a Secure Shell protocol. The management device establishes a remote session connection with the target server's operating system via a Shell (SSH) encrypted communication link. This connection is achieved through pre-configured authentication credentials or key pairs and the network infrastructure, ensuring the security and integrity of data transmission. Once the channel is established, the management device sends system-level query commands to the target server, accessing preset paths exposed by the operating system kernel to obtain the PCI resource configuration information of the current hardware. These preset paths include, but are not limited to, the / proc / bus / pci directory tree, the / sys / bus / pci / devices directory and its subdirectories in the virtual file system, and the system log files under the / var / log directory. Combined with the text output obtained by executing the lspci command and the kernel ring buffer information captured by the dmesg command, a complete PCI resource topology view is constructed. Within these paths, each folder under / sys / bus / pci / devices corresponds to a specific PCI functional device, containing a resource file that details the device's memory-mapped input / output (MMIO) address range, I / O port range, and bus number. The vvv option of the lspci command reveals the base address register in the PCI configuration space. The Register (BAR) provides detailed configuration, capability register status, and mapping relationship between devices and system memory. The dmesg log provides timing records of the BIOS or UE firmware enumerating and allocating resources on the PCI bus during system startup, including key events such as initial address space allocation, rebalance operations, and error reports.

[0034] After the acquired raw PCI resource configuration information is structured and parsed, the management device extracts key data regarding the allocated status of hardware resources. Specifically, this includes quantitative statistics on the occupancy of MMIO32 address space (32-bit addressable memory-mapped I / O space), MMIO64 address space (64-bit addressable memory-mapped I / O space, supporting the Prefetchable attribute), and traditional I / O port space. For each identified PCI device, the management device reads the value of its BAR register, decodes the length of the address range requested and actually obtained by the device, and records the start and end addresses of this range. Special attention is paid to distinguishing the attributes of different types of resources, such as the difference between Prefetchable memory and ordinary memory, and whether the device supports 64-bit addressing. During the statistical process, the management device also needs to identify and exclude non-reallocatable spaces occupied by system reserved areas, chipset reserved areas, and firmware-specific functions to ensure that the subsequent baseline data accurately reflects the actual resource reserve available for dynamic allocation to PCIe devices connected to the DPU. For the DPU device itself, the management device parses its PCIe... The configuration register of the downstream port (DSP) of the switch is used to obtain the reserved resource window size preset by the current BIOS for each DSP. These preset values ​​are usually stored in the Device Capabilities Register and Slot Capabilities Register of PCIe capabilities, reflecting the maximum hot-swappable device resource requirements that each downstream port can theoretically support under the current system configuration.

[0035] Based on the precise statistics of the allocated hardware resources mentioned above, the management device executes the calculation logic for the maximum reserved hardware resource threshold. This calculation process first determines the total address space supported by the target server platform, which depends on the CPU architecture, chipset memory controller configuration, and BIOS PCI resource allocation strategy. For example, in x86 architecture servers, MMIO32 space is typically limited to an address range below 4GB, while MMIO64 space can be expanded to the TB level. The management device then deducts the aforementioned allocated resources from the total available space, including resources statically allocated to other PCIe devices unrelated to the DPU during system startup, resources occupied by fixed devices integrated on the motherboard, and resources already allocated by the operating system and drivers. The difference between the marked address ranges is theoretically the maximum resource pool that can be reserved for hot-plugging of DSPs under the DPU. However, the actual allocable threshold also needs to consider the alignment requirements specified by the PCIe protocol. That is, resource allocation must be aligned to the boundary according to 4KB, 1MB or other architecture-specific granularities, while a certain safety margin must be reserved for PCIe bus enumeration overhead and address decoding buffer during system operation. Therefore, the management device will apply the corresponding alignment algorithm and margin deduction mechanism when calculating, and finally generate a maximum reserved resource threshold that satisfies hardware alignment constraints and ensures stable system operation. This value represents the maximum BAR space requirement of hot-pluggable devices that a single DSP or DSP combination can support without causing resource conflicts.

[0036] In one implementation, the PCI resource configuration information includes the address range and allocated information of the PCI bus, I / O ports, MMIO32, and MMIO64.

[0037] In one implementation, the step of calculating the critical value of the maximum reserved hardware resources based on the allocated hardware resources includes: calculating the amount of unallocated hardware resources based on the allocated hardware resources, calling QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configuring hardware resources for the virtual PCIe devices based on the amount of unallocated hardware resources, verifying whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirming the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

[0038] To further improve the accuracy of threshold determination and the reliability of system compatibility verification, this progressive solution introduces a dynamic verification mechanism based on virtualization simulation. Specifically, after calculating the amount of unallocated hardware resources (i.e., the remaining amount after subtracting allocated resources from the total available resources of the system), this remaining amount or its proportionally reduced value is not directly used as the threshold for the maximum reserved hardware resources. Instead, a highly simulated PCIe hot-plug test environment is built locally on the management device or target server by calling the open-source hardware virtualization platform QEMU. In this environment, multiple virtual PCIe devices are inserted into several downstream ports (DSPs) connected to the simulated DPU devices. These virtual devices can be configured as NVMe controllers, Ethernet controllers, or other typical PCIe terminal devices with specific BAR types, sizes, and numbers. Their resource requirement parameters can be flexibly set according to the actual application scenario. For example, a single virtual device can be set to request 512MB, 1GB, or even 4GB of 64-bit prefetchable MMIO space.

[0039] Subsequently, based on the previously calculated amount of unallocated hardware resources, the system attempts to allocate corresponding hardware resources to these virtual PCIe devices, including MMIO address ranges, I / O port ranges, and necessary PCI bus numbers. This allocation process strictly adheres to the PCIe specification requirements regarding address alignment, window continuity, and switch-level aggregation, and strives to reproduce the resource allocation logic of the target server BIOS in a real hot-plugging scenario. After resource allocation is completed, the QEMU virtual machine is started and a lightweight operating system (such as Linux or a customized UEFI Shell) is loaded. Device enumeration, driver binding, and basic I / O operations (such as reading and writing BAR registers, initiating DMA transfers, etc.) are performed to comprehensively verify whether the entire PCIe subsystem can operate stably under this resource configuration, and whether there are any issues such as address conflicts, device suspension due to insufficient resources, system crashes, or firmware errors. If the verification is successful, it indicates that the total amount of resources currently configured is still within the system's tolerance range. The number of virtual devices or the resource request amount of a single device is then gradually increased, and the above simulation and verification process is repeated. If the verification fails, the system reverts to the previous successful configuration, which serves as the safety boundary.

[0040] The number of verifications mentioned above is significantly less than that of technical solutions that deviate from the pre-calculated allocation of hardware resources.

[0041] In one implementation, the PCI resource configuration information of the target server's current hardware is obtained by setting a channel to access a preset path of the target server. This includes: logging into the target server system via an SSH channel, using the dm esg and lspci commands, and accessing the system directory to obtain the PCI resource configuration information of the target server's current hardware.

[0042] In one implementation, such as Figure 2 Log in to the Server OS via SSH and use the `dm esg`, `lspci` commands, and access the ` / proc` path to obtain PCI resource configuration information (including PCI bus, I / O ports, MMIO32 and MMIO64 address ranges and allocations). Filter the information using shell commands or scripts, calculate the amount of resources already used in the Server, and determine the maximum allocatable resource threshold. Configure an automated script to use QEMU to simulate device insertion, such as simulating the insertion of a multi-level switch configuration under the DSP, increasing the number of downstream devices. The number of buses added is equal to the maximum allocatable threshold of the system bus. After restarting, verify whether the SEL log reporting and resource allocation meet expectations under the current threshold.

[0043] In one implementation, such as Figure 3 This specification also provides a DPU resource configuration device for use in management devices. The device includes: a first module for accessing a preset path of a target server through a set channel to obtain the PCI resource configuration information of the target server's current hardware; a second module for calculating the amount of allocated hardware resources in the target server's hardware resources based on the obtained PCI resource configuration information, wherein the hardware resources can be allocated to PCIe devices connected to the DPU device for PCIe device operation; and a third module for calculating the threshold value of the maximum reserved hardware resources based on the allocated hardware resource amount; wherein the target server includes a DPU device.

[0044] In one implementation, the PCI resource configuration information includes the address range and allocated information of the PCI bus, I / O ports, MMIO32, and MMIO64.

[0045] In one implementation, the step of calculating the critical value of the maximum reserved hardware resources based on the allocated hardware resources includes: calculating the amount of unallocated hardware resources based on the allocated hardware resources, calling QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configuring hardware resources for the virtual PCIe devices based on the amount of unallocated hardware resources, verifying whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirming the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

[0046] In one implementation, the PCI resource configuration information of the target server's current hardware is obtained by setting a channel to access a preset path of the target server. This includes: logging into the target server system via an SSH channel, using the dm esg and lspci commands, and accessing the system directory to obtain the PCI resource configuration information of the target server's current hardware.

[0047] This specification also provides an electronic device, including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned DPU resource configuration method.

[0048] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned DPU resource configuration method.

[0049] The implementation methods of the apparatus are the same as or similar to the corresponding implementation methods, and will not be described again here.

[0050] In one embodiment, this specification provides an electronic device including a processor and a readable storage medium storing machine-executable instructions executable by the processor. The processor executes the machine-executable instructions to implement the aforementioned DPU resource allocation method. From a hardware perspective, a hardware architecture diagram can be found... Figure 4 As shown.

[0051] In one embodiment, this specification provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned DPU resource configuration method.

[0052] Here, a readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0053] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0054] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0055] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0056] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments thereof. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0057] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0058] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0059] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0060] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A method for configuring DPU resources, characterized in that, Applied to the management of equipment, the method includes: By setting a channel to access the target server's preset path, the PCI resource configuration information of the target server's current hardware can be obtained; Based on the obtained PCI resource configuration information of the target server, the amount of hardware resources already allocated in the hardware resources of the target server is calculated. The hardware resources can be allocated to the PCIe devices connected to the DPU device for the operation of the PCIe devices. Calculate the critical value of the maximum reserved hardware resources based on the amount of allocated hardware resources; The target server includes a DPU device.

2. The method according to claim 1, characterized in that, The PCI resource configuration information includes the address range and allocated information for the PCI bus, I / O ports, MMIO32, and MMIO64.

3. The method according to claim 1, characterized in that, The calculation of the critical value for the maximum reserved hardware resources based on the allocated hardware resources includes: Calculate the amount of unallocated hardware resources based on the allocated hardware resources, call QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configure hardware resources for the virtual PCIe devices according to the amount of unallocated hardware resources, verify whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirm the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

4. The method according to claim 1, characterized in that, By configuring a channel to access the target server's preset path, the system obtains the target server's current hardware PCI resource configuration information, including: Log in to the target server system via SSH tunnel and use the dm esg and lspci commands to access the system directory and obtain the PCI resource configuration information of the target server's current hardware.

5. A DPU resource allocation device, characterized in that, Applied to management equipment, the device includes: The first module is used to access the preset path of the target server through a set channel and obtain the PCI resource configuration information of the target server's current hardware. The second module is used to calculate the amount of hardware resources already allocated in the hardware resources of the target server based on the obtained PCI resource configuration information of the target server. The hardware resources can be allocated to the PCIe devices connected to the DPU device for the operation of the PCIe devices. The third module is used to calculate the critical value of the maximum reserved hardware resources based on the amount of allocated hardware resources. The target server includes a DPU device.

6. The apparatus according to claim 5, characterized in that, The PCI resource configuration information includes the address range and allocated information for the PCI bus, I / O ports, MMIO32, and MMIO64.

7. The apparatus according to claim 5, characterized in that, The calculation of the critical value for the maximum reserved hardware resources based on the allocated hardware resources includes: Calculate the amount of unallocated hardware resources based on the allocated hardware resources, call QEMU to simulate inserting several virtual PCIe devices through the DSP of the DPU device, configure hardware resources for the virtual PCIe devices according to the amount of unallocated hardware resources, verify whether the server can run normally after configuring hardware resources for the virtual PCIe devices, and confirm the critical value of the maximum reserved hardware resources based on the verification result of normal operation.

8. The apparatus according to claim 5, characterized in that, By configuring a channel to access the target server's preset path, the system obtains the target server's current hardware PCI resource configuration information, including: Log in to the target server system via SSH tunnel and use the dm esg and lspci commands to access the system directory and obtain the PCI resource configuration information of the target server's current hardware.

9. An electronic device, characterized in that, include: A processor and a readable storage medium storing machine-executable instructions that can be executed by the processor to implement the method of any one of claims 1-4.

10. A readable storage medium, characterized in that, The readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method described in any one of claims 1-4.

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